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authorNicolin Chen <Guangyu.Chen@freescale.com>2014-04-04 03:09:47 -0400
committerMark Brown <broonie@linaro.org>2014-04-08 07:49:55 -0400
commitef33bc3217c7aa9868f497c4f797cc50ad3ce357 (patch)
tree4ff0dc41289efc0ebd06aa984555f1b20624bae8 /sound
parente2681a1bf5ae053426a6c5c1daaed17b2f95efe6 (diff)
ASoC: fsl_sai: Fix Bit Clock Polarity configurations
The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. For all formats currently supported in the fsl_sai driver, they're exactly sending data on the falling edge and sampling on the rising edge. However, the driver clears this BCP bit for all of them which results click noise when working with SGTL5000 and big noise with WM8962. Thus this patch corrects the BCP settings for all the formats here to fix the nosie issue. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/fsl/fsl_sai.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 0bc98bb21810..56da8c8c5960 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -179,7 +179,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
179 * that is, together with the last bit of the previous 179 * that is, together with the last bit of the previous
180 * data word. 180 * data word.
181 */ 181 */
182 val_cr2 &= ~FSL_SAI_CR2_BCP; 182 val_cr2 |= FSL_SAI_CR2_BCP;
183 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 183 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
184 break; 184 break;
185 case SND_SOC_DAIFMT_LEFT_J: 185 case SND_SOC_DAIFMT_LEFT_J:
@@ -187,7 +187,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
187 * Frame high, one word length for frame sync, 187 * Frame high, one word length for frame sync,
188 * frame sync asserts with the first bit of the frame. 188 * frame sync asserts with the first bit of the frame.
189 */ 189 */
190 val_cr2 &= ~FSL_SAI_CR2_BCP; 190 val_cr2 |= FSL_SAI_CR2_BCP;
191 val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP); 191 val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
192 break; 192 break;
193 case SND_SOC_DAIFMT_DSP_A: 193 case SND_SOC_DAIFMT_DSP_A:
@@ -197,7 +197,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
197 * that is, together with the last bit of the previous 197 * that is, together with the last bit of the previous
198 * data word. 198 * data word.
199 */ 199 */
200 val_cr2 &= ~FSL_SAI_CR2_BCP; 200 val_cr2 |= FSL_SAI_CR2_BCP;
201 val_cr4 &= ~FSL_SAI_CR4_FSP; 201 val_cr4 &= ~FSL_SAI_CR4_FSP;
202 val_cr4 |= FSL_SAI_CR4_FSE; 202 val_cr4 |= FSL_SAI_CR4_FSE;
203 sai->is_dsp_mode = true; 203 sai->is_dsp_mode = true;
@@ -207,7 +207,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
207 * Frame high, one bit for frame sync, 207 * Frame high, one bit for frame sync,
208 * frame sync asserts with the first bit of the frame. 208 * frame sync asserts with the first bit of the frame.
209 */ 209 */
210 val_cr2 &= ~FSL_SAI_CR2_BCP; 210 val_cr2 |= FSL_SAI_CR2_BCP;
211 val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP); 211 val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
212 sai->is_dsp_mode = true; 212 sai->is_dsp_mode = true;
213 break; 213 break;