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authorStephen Warren <swarren@nvidia.com>2012-04-06 12:30:52 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-04-06 12:36:15 -0400
commit896637ac1be95a239b68dbe61c12a8a9bc00a9a3 (patch)
treebd6bfa8f1ecb71d1307634354eb6e674576abd93 /sound
parentef280d3907cea21b6093802398bbe4193e221a64 (diff)
ASoC: tegra: complete Tegra->Tegra20 renaming
Rename Tegra20-specific Kconfig variables, module filenames, all internal symbol names, clocks, and platform devices, to reflect the fact the DAS and I2S drivers are for a specific HW version. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/tegra/Kconfig20
-rw-r--r--sound/soc/tegra/Makefile6
-rw-r--r--sound/soc/tegra/tegra20_das.c134
-rw-r--r--sound/soc/tegra/tegra20_das.h124
-rw-r--r--sound/soc/tegra/tegra20_i2s.c204
-rw-r--r--sound/soc/tegra/tegra20_i2s.h246
-rw-r--r--sound/soc/tegra/tegra20_spdif.c140
-rw-r--r--sound/soc/tegra/tegra20_spdif.h398
-rw-r--r--sound/soc/tegra/tegra_wm8903.c4
-rw-r--r--sound/soc/tegra/trimslice.c4
10 files changed, 640 insertions, 640 deletions
diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
index d51945e78017..556cac29ea15 100644
--- a/sound/soc/tegra/Kconfig
+++ b/sound/soc/tegra/Kconfig
@@ -4,29 +4,29 @@ config SND_SOC_TEGRA
4 help 4 help
5 Say Y or M here if you want support for SoC audio on Tegra. 5 Say Y or M here if you want support for SoC audio on Tegra.
6 6
7config SND_SOC_TEGRA_DAS 7config SND_SOC_TEGRA20_DAS
8 tristate 8 tristate
9 depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC 9 depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC
10 help 10 help
11 Say Y or M if you want to add support for the Tegra DAS module. 11 Say Y or M if you want to add support for the Tegra20 DAS module.
12 You will also need to select the individual machine drivers to 12 You will also need to select the individual machine drivers to
13 support below. 13 support below.
14 14
15config SND_SOC_TEGRA_I2S 15config SND_SOC_TEGRA20_I2S
16 tristate 16 tristate
17 depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC 17 depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC
18 select SND_SOC_TEGRA_DAS 18 select SND_SOC_TEGRA20_DAS
19 help 19 help
20 Say Y or M if you want to add support for codecs attached to the 20 Say Y or M if you want to add support for codecs attached to the
21 Tegra I2S interface. You will also need to select the individual 21 Tegra20 I2S interface. You will also need to select the individual
22 machine drivers to support below. 22 machine drivers to support below.
23 23
24config SND_SOC_TEGRA_SPDIF 24config SND_SOC_TEGRA20_SPDIF
25 tristate 25 tristate
26 depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC 26 depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC
27 default m 27 default m
28 help 28 help
29 Say Y or M if you want to add support for the SPDIF interface. 29 Say Y or M if you want to add support for the Tegra20 SPDIF interface.
30 You will also need to select the individual machine drivers to support 30 You will also need to select the individual machine drivers to support
31 below. 31 below.
32 32
@@ -41,7 +41,7 @@ config SND_SOC_TEGRA_WM8903
41 tristate "SoC Audio support for Tegra boards using a WM8903 codec" 41 tristate "SoC Audio support for Tegra boards using a WM8903 codec"
42 depends on SND_SOC_TEGRA && I2C 42 depends on SND_SOC_TEGRA && I2C
43 depends on MACH_HAS_SND_SOC_TEGRA_WM8903 43 depends on MACH_HAS_SND_SOC_TEGRA_WM8903
44 select SND_SOC_TEGRA_I2S if ARCH_TEGRA_2x_SOC 44 select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC
45 select SND_SOC_WM8903 45 select SND_SOC_WM8903
46 help 46 help
47 Say Y or M here if you want to add support for SoC audio on Tegra 47 Say Y or M here if you want to add support for SoC audio on Tegra
@@ -51,7 +51,7 @@ config SND_SOC_TEGRA_WM8903
51config SND_SOC_TEGRA_TRIMSLICE 51config SND_SOC_TEGRA_TRIMSLICE
52 tristate "SoC Audio support for TrimSlice board" 52 tristate "SoC Audio support for TrimSlice board"
53 depends on SND_SOC_TEGRA && MACH_TRIMSLICE && I2C 53 depends on SND_SOC_TEGRA && MACH_TRIMSLICE && I2C
54 select SND_SOC_TEGRA_I2S if ARCH_TEGRA_2x_SOC 54 select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC
55 select SND_SOC_TLV320AIC23 55 select SND_SOC_TLV320AIC23
56 help 56 help
57 Say Y or M here if you want to add support for SoC audio on the 57 Say Y or M here if you want to add support for SoC audio on the
@@ -60,7 +60,7 @@ config SND_SOC_TEGRA_TRIMSLICE
60config SND_SOC_TEGRA_ALC5632 60config SND_SOC_TEGRA_ALC5632
61 tristate "SoC Audio support for Tegra boards using an ALC5632 codec" 61 tristate "SoC Audio support for Tegra boards using an ALC5632 codec"
62 depends on SND_SOC_TEGRA && I2C 62 depends on SND_SOC_TEGRA && I2C
63 select SND_SOC_TEGRA_I2S if ARCH_TEGRA_2x_SOC 63 select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC
64 select SND_SOC_ALC5632 64 select SND_SOC_ALC5632
65 help 65 help
66 Say Y or M here if you want to add support for SoC audio on the 66 Say Y or M here if you want to add support for SoC audio on the
diff --git a/sound/soc/tegra/Makefile b/sound/soc/tegra/Makefile
index 4a33884115f8..4726b909664d 100644
--- a/sound/soc/tegra/Makefile
+++ b/sound/soc/tegra/Makefile
@@ -7,9 +7,9 @@ snd-soc-tegra20-spdif-objs := tegra20_spdif.o
7 7
8obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-pcm.o 8obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-pcm.o
9obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-utils.o 9obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-utils.o
10obj-$(CONFIG_SND_SOC_TEGRA_DAS) += snd-soc-tegra20-das.o 10obj-$(CONFIG_SND_SOC_TEGRA20_DAS) += snd-soc-tegra20-das.o
11obj-$(CONFIG_SND_SOC_TEGRA_I2S) += snd-soc-tegra20-i2s.o 11obj-$(CONFIG_SND_SOC_TEGRA20_I2S) += snd-soc-tegra20-i2s.o
12obj-$(CONFIG_SND_SOC_TEGRA_SPDIF) += snd-soc-tegra20-spdif.o 12obj-$(CONFIG_SND_SOC_TEGRA20_SPDIF) += snd-soc-tegra20-spdif.o
13 13
14# Tegra machine Support 14# Tegra machine Support
15snd-soc-tegra-wm8903-objs := tegra_wm8903.o 15snd-soc-tegra-wm8903-objs := tegra_wm8903.o
diff --git a/sound/soc/tegra/tegra20_das.c b/sound/soc/tegra/tegra20_das.c
index b5e369820cb3..486d7b245cf4 100644
--- a/sound/soc/tegra/tegra20_das.c
+++ b/sound/soc/tegra/tegra20_das.c
@@ -31,21 +31,21 @@
31#include <sound/soc.h> 31#include <sound/soc.h>
32#include "tegra20_das.h" 32#include "tegra20_das.h"
33 33
34#define DRV_NAME "tegra-das" 34#define DRV_NAME "tegra20-das"
35 35
36static struct tegra_das *das; 36static struct tegra20_das *das;
37 37
38static inline void tegra_das_write(u32 reg, u32 val) 38static inline void tegra20_das_write(u32 reg, u32 val)
39{ 39{
40 __raw_writel(val, das->regs + reg); 40 __raw_writel(val, das->regs + reg);
41} 41}
42 42
43static inline u32 tegra_das_read(u32 reg) 43static inline u32 tegra20_das_read(u32 reg)
44{ 44{
45 return __raw_readl(das->regs + reg); 45 return __raw_readl(das->regs + reg);
46} 46}
47 47
48int tegra_das_connect_dap_to_dac(int dap, int dac) 48int tegra20_das_connect_dap_to_dac(int dap, int dac)
49{ 49{
50 u32 addr; 50 u32 addr;
51 u32 reg; 51 u32 reg;
@@ -53,18 +53,18 @@ int tegra_das_connect_dap_to_dac(int dap, int dac)
53 if (!das) 53 if (!das)
54 return -ENODEV; 54 return -ENODEV;
55 55
56 addr = TEGRA_DAS_DAP_CTRL_SEL + 56 addr = TEGRA20_DAS_DAP_CTRL_SEL +
57 (dap * TEGRA_DAS_DAP_CTRL_SEL_STRIDE); 57 (dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
58 reg = dac << TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P; 58 reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P;
59 59
60 tegra_das_write(addr, reg); 60 tegra20_das_write(addr, reg);
61 61
62 return 0; 62 return 0;
63} 63}
64EXPORT_SYMBOL_GPL(tegra_das_connect_dap_to_dac); 64EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dac);
65 65
66int tegra_das_connect_dap_to_dap(int dap, int otherdap, int master, 66int tegra20_das_connect_dap_to_dap(int dap, int otherdap, int master,
67 int sdata1rx, int sdata2rx) 67 int sdata1rx, int sdata2rx)
68{ 68{
69 u32 addr; 69 u32 addr;
70 u32 reg; 70 u32 reg;
@@ -72,20 +72,20 @@ int tegra_das_connect_dap_to_dap(int dap, int otherdap, int master,
72 if (!das) 72 if (!das)
73 return -ENODEV; 73 return -ENODEV;
74 74
75 addr = TEGRA_DAS_DAP_CTRL_SEL + 75 addr = TEGRA20_DAS_DAP_CTRL_SEL +
76 (dap * TEGRA_DAS_DAP_CTRL_SEL_STRIDE); 76 (dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
77 reg = otherdap << TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P | 77 reg = otherdap << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P |
78 !!sdata2rx << TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P | 78 !!sdata2rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P |
79 !!sdata1rx << TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P | 79 !!sdata1rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P |
80 !!master << TEGRA_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P; 80 !!master << TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P;
81 81
82 tegra_das_write(addr, reg); 82 tegra20_das_write(addr, reg);
83 83
84 return 0; 84 return 0;
85} 85}
86EXPORT_SYMBOL_GPL(tegra_das_connect_dap_to_dap); 86EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dap);
87 87
88int tegra_das_connect_dac_to_dap(int dac, int dap) 88int tegra20_das_connect_dac_to_dap(int dac, int dap)
89{ 89{
90 u32 addr; 90 u32 addr;
91 u32 reg; 91 u32 reg;
@@ -93,78 +93,78 @@ int tegra_das_connect_dac_to_dap(int dac, int dap)
93 if (!das) 93 if (!das)
94 return -ENODEV; 94 return -ENODEV;
95 95
96 addr = TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL + 96 addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
97 (dac * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE); 97 (dac * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
98 reg = dap << TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P | 98 reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P |
99 dap << TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P | 99 dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P |
100 dap << TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P; 100 dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P;
101 101
102 tegra_das_write(addr, reg); 102 tegra20_das_write(addr, reg);
103 103
104 return 0; 104 return 0;
105} 105}
106EXPORT_SYMBOL_GPL(tegra_das_connect_dac_to_dap); 106EXPORT_SYMBOL_GPL(tegra20_das_connect_dac_to_dap);
107 107
108#ifdef CONFIG_DEBUG_FS 108#ifdef CONFIG_DEBUG_FS
109static int tegra_das_show(struct seq_file *s, void *unused) 109static int tegra20_das_show(struct seq_file *s, void *unused)
110{ 110{
111 int i; 111 int i;
112 u32 addr; 112 u32 addr;
113 u32 reg; 113 u32 reg;
114 114
115 for (i = 0; i < TEGRA_DAS_DAP_CTRL_SEL_COUNT; i++) { 115 for (i = 0; i < TEGRA20_DAS_DAP_CTRL_SEL_COUNT; i++) {
116 addr = TEGRA_DAS_DAP_CTRL_SEL + 116 addr = TEGRA20_DAS_DAP_CTRL_SEL +
117 (i * TEGRA_DAS_DAP_CTRL_SEL_STRIDE); 117 (i * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
118 reg = tegra_das_read(addr); 118 reg = tegra20_das_read(addr);
119 seq_printf(s, "TEGRA_DAS_DAP_CTRL_SEL[%d] = %08x\n", i, reg); 119 seq_printf(s, "TEGRA20_DAS_DAP_CTRL_SEL[%d] = %08x\n", i, reg);
120 } 120 }
121 121
122 for (i = 0; i < TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT; i++) { 122 for (i = 0; i < TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT; i++) {
123 addr = TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL + 123 addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
124 (i * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE); 124 (i * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
125 reg = tegra_das_read(addr); 125 reg = tegra20_das_read(addr);
126 seq_printf(s, "TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL[%d] = %08x\n", 126 seq_printf(s, "TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL[%d] = %08x\n",
127 i, reg); 127 i, reg);
128 } 128 }
129 129
130 return 0; 130 return 0;
131} 131}
132 132
133static int tegra_das_debug_open(struct inode *inode, struct file *file) 133static int tegra20_das_debug_open(struct inode *inode, struct file *file)
134{ 134{
135 return single_open(file, tegra_das_show, inode->i_private); 135 return single_open(file, tegra20_das_show, inode->i_private);
136} 136}
137 137
138static const struct file_operations tegra_das_debug_fops = { 138static const struct file_operations tegra20_das_debug_fops = {
139 .open = tegra_das_debug_open, 139 .open = tegra20_das_debug_open,
140 .read = seq_read, 140 .read = seq_read,
141 .llseek = seq_lseek, 141 .llseek = seq_lseek,
142 .release = single_release, 142 .release = single_release,
143}; 143};
144 144
145static void tegra_das_debug_add(struct tegra_das *das) 145static void tegra20_das_debug_add(struct tegra20_das *das)
146{ 146{
147 das->debug = debugfs_create_file(DRV_NAME, S_IRUGO, 147 das->debug = debugfs_create_file(DRV_NAME, S_IRUGO,
148 snd_soc_debugfs_root, das, 148 snd_soc_debugfs_root, das,
149 &tegra_das_debug_fops); 149 &tegra20_das_debug_fops);
150} 150}
151 151
152static void tegra_das_debug_remove(struct tegra_das *das) 152static void tegra20_das_debug_remove(struct tegra20_das *das)
153{ 153{
154 if (das->debug) 154 if (das->debug)
155 debugfs_remove(das->debug); 155 debugfs_remove(das->debug);
156} 156}
157#else 157#else
158static inline void tegra_das_debug_add(struct tegra_das *das) 158static inline void tegra20_das_debug_add(struct tegra20_das *das)
159{ 159{
160} 160}
161 161
162static inline void tegra_das_debug_remove(struct tegra_das *das) 162static inline void tegra20_das_debug_remove(struct tegra20_das *das)
163{ 163{
164} 164}
165#endif 165#endif
166 166
167static int __devinit tegra_das_probe(struct platform_device *pdev) 167static int __devinit tegra20_das_probe(struct platform_device *pdev)
168{ 168{
169 struct resource *res, *region; 169 struct resource *res, *region;
170 int ret = 0; 170 int ret = 0;
@@ -172,9 +172,9 @@ static int __devinit tegra_das_probe(struct platform_device *pdev)
172 if (das) 172 if (das)
173 return -ENODEV; 173 return -ENODEV;
174 174
175 das = devm_kzalloc(&pdev->dev, sizeof(struct tegra_das), GFP_KERNEL); 175 das = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_das), GFP_KERNEL);
176 if (!das) { 176 if (!das) {
177 dev_err(&pdev->dev, "Can't allocate tegra_das\n"); 177 dev_err(&pdev->dev, "Can't allocate tegra20_das\n");
178 ret = -ENOMEM; 178 ret = -ENOMEM;
179 goto err; 179 goto err;
180 } 180 }
@@ -202,20 +202,20 @@ static int __devinit tegra_das_probe(struct platform_device *pdev)
202 goto err; 202 goto err;
203 } 203 }
204 204
205 ret = tegra_das_connect_dap_to_dac(TEGRA_DAS_DAP_ID_1, 205 ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_1,
206 TEGRA_DAS_DAP_SEL_DAC1); 206 TEGRA20_DAS_DAP_SEL_DAC1);
207 if (ret) { 207 if (ret) {
208 dev_err(&pdev->dev, "Can't set up DAS DAP connection\n"); 208 dev_err(&pdev->dev, "Can't set up DAS DAP connection\n");
209 goto err; 209 goto err;
210 } 210 }
211 ret = tegra_das_connect_dac_to_dap(TEGRA_DAS_DAC_ID_1, 211 ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_1,
212 TEGRA_DAS_DAC_SEL_DAP1); 212 TEGRA20_DAS_DAC_SEL_DAP1);
213 if (ret) { 213 if (ret) {
214 dev_err(&pdev->dev, "Can't set up DAS DAC connection\n"); 214 dev_err(&pdev->dev, "Can't set up DAS DAC connection\n");
215 goto err; 215 goto err;
216 } 216 }
217 217
218 tegra_das_debug_add(das); 218 tegra20_das_debug_add(das);
219 219
220 platform_set_drvdata(pdev, das); 220 platform_set_drvdata(pdev, das);
221 221
@@ -226,36 +226,36 @@ err:
226 return ret; 226 return ret;
227} 227}
228 228
229static int __devexit tegra_das_remove(struct platform_device *pdev) 229static int __devexit tegra20_das_remove(struct platform_device *pdev)
230{ 230{
231 if (!das) 231 if (!das)
232 return -ENODEV; 232 return -ENODEV;
233 233
234 tegra_das_debug_remove(das); 234 tegra20_das_debug_remove(das);
235 235
236 das = NULL; 236 das = NULL;
237 237
238 return 0; 238 return 0;
239} 239}
240 240
241static const struct of_device_id tegra_das_of_match[] __devinitconst = { 241static const struct of_device_id tegra20_das_of_match[] __devinitconst = {
242 { .compatible = "nvidia,tegra20-das", }, 242 { .compatible = "nvidia,tegra20-das", },
243 {}, 243 {},
244}; 244};
245 245
246static struct platform_driver tegra_das_driver = { 246static struct platform_driver tegra20_das_driver = {
247 .probe = tegra_das_probe, 247 .probe = tegra20_das_probe,
248 .remove = __devexit_p(tegra_das_remove), 248 .remove = __devexit_p(tegra20_das_remove),
249 .driver = { 249 .driver = {
250 .name = DRV_NAME, 250 .name = DRV_NAME,
251 .owner = THIS_MODULE, 251 .owner = THIS_MODULE,
252 .of_match_table = tegra_das_of_match, 252 .of_match_table = tegra20_das_of_match,
253 }, 253 },
254}; 254};
255module_platform_driver(tegra_das_driver); 255module_platform_driver(tegra20_das_driver);
256 256
257MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 257MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
258MODULE_DESCRIPTION("Tegra DAS driver"); 258MODULE_DESCRIPTION("Tegra20 DAS driver");
259MODULE_LICENSE("GPL"); 259MODULE_LICENSE("GPL");
260MODULE_ALIAS("platform:" DRV_NAME); 260MODULE_ALIAS("platform:" DRV_NAME);
261MODULE_DEVICE_TABLE(of, tegra_das_of_match); 261MODULE_DEVICE_TABLE(of, tegra20_das_of_match);
diff --git a/sound/soc/tegra/tegra20_das.h b/sound/soc/tegra/tegra20_das.h
index 896bf031a801..ade4fe080c45 100644
--- a/sound/soc/tegra/tegra20_das.h
+++ b/sound/soc/tegra/tegra20_das.h
@@ -2,7 +2,7 @@
2 * tegra20_das.h - Definitions for Tegra20 DAS driver 2 * tegra20_das.h - Definitions for Tegra20 DAS driver
3 * 3 *
4 * Author: Stephen Warren <swarren@nvidia.com> 4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2010 - NVIDIA, Inc. 5 * Copyright (C) 2010,2012 - NVIDIA, Inc.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License 8 * modify it under the terms of the GNU General Public License
@@ -20,70 +20,70 @@
20 * 20 *
21 */ 21 */
22 22
23#ifndef __TEGRA_DAS_H__ 23#ifndef __TEGRA20_DAS_H__
24#define __TEGRA_DAS_H__ 24#define __TEGRA20_DAS_H__
25 25
26/* Register TEGRA_DAS_DAP_CTRL_SEL */ 26/* Register TEGRA20_DAS_DAP_CTRL_SEL */
27#define TEGRA_DAS_DAP_CTRL_SEL 0x00 27#define TEGRA20_DAS_DAP_CTRL_SEL 0x00
28#define TEGRA_DAS_DAP_CTRL_SEL_COUNT 5 28#define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
29#define TEGRA_DAS_DAP_CTRL_SEL_STRIDE 4 29#define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
30#define TEGRA_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31 30#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
31#define TEGRA_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1 31#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
32#define TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30 32#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
33#define TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1 33#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
34#define TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29 34#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
35#define TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1 35#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
36#define TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0 36#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
37#define TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5 37#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
38 38
39/* Values for field TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */ 39/* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
40#define TEGRA_DAS_DAP_SEL_DAC1 0 40#define TEGRA20_DAS_DAP_SEL_DAC1 0
41#define TEGRA_DAS_DAP_SEL_DAC2 1 41#define TEGRA20_DAS_DAP_SEL_DAC2 1
42#define TEGRA_DAS_DAP_SEL_DAC3 2 42#define TEGRA20_DAS_DAP_SEL_DAC3 2
43#define TEGRA_DAS_DAP_SEL_DAP1 16 43#define TEGRA20_DAS_DAP_SEL_DAP1 16
44#define TEGRA_DAS_DAP_SEL_DAP2 17 44#define TEGRA20_DAS_DAP_SEL_DAP2 17
45#define TEGRA_DAS_DAP_SEL_DAP3 18 45#define TEGRA20_DAS_DAP_SEL_DAP3 18
46#define TEGRA_DAS_DAP_SEL_DAP4 19 46#define TEGRA20_DAS_DAP_SEL_DAP4 19
47#define TEGRA_DAS_DAP_SEL_DAP5 20 47#define TEGRA20_DAS_DAP_SEL_DAP5 20
48 48
49/* Register TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL */ 49/* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
50#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL 0x40 50#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
51#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3 51#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
52#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4 52#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
53#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28 53#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
54#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4 54#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
55#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24 55#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
56#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4 56#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
57#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0 57#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
58#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4 58#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
59 59
60/* 60/*
61 * Values for: 61 * Values for:
62 * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL 62 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
63 * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL 63 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
64 * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL 64 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
65 */ 65 */
66#define TEGRA_DAS_DAC_SEL_DAP1 0 66#define TEGRA20_DAS_DAC_SEL_DAP1 0
67#define TEGRA_DAS_DAC_SEL_DAP2 1 67#define TEGRA20_DAS_DAC_SEL_DAP2 1
68#define TEGRA_DAS_DAC_SEL_DAP3 2 68#define TEGRA20_DAS_DAC_SEL_DAP3 2
69#define TEGRA_DAS_DAC_SEL_DAP4 3 69#define TEGRA20_DAS_DAC_SEL_DAP4 3
70#define TEGRA_DAS_DAC_SEL_DAP5 4 70#define TEGRA20_DAS_DAC_SEL_DAP5 4
71 71
72/* 72/*
73 * Names/IDs of the DACs/DAPs. 73 * Names/IDs of the DACs/DAPs.
74 */ 74 */
75 75
76#define TEGRA_DAS_DAP_ID_1 0 76#define TEGRA20_DAS_DAP_ID_1 0
77#define TEGRA_DAS_DAP_ID_2 1 77#define TEGRA20_DAS_DAP_ID_2 1
78#define TEGRA_DAS_DAP_ID_3 2 78#define TEGRA20_DAS_DAP_ID_3 2
79#define TEGRA_DAS_DAP_ID_4 3 79#define TEGRA20_DAS_DAP_ID_4 3
80#define TEGRA_DAS_DAP_ID_5 4 80#define TEGRA20_DAS_DAP_ID_5 4
81 81
82#define TEGRA_DAS_DAC_ID_1 0 82#define TEGRA20_DAS_DAC_ID_1 0
83#define TEGRA_DAS_DAC_ID_2 1 83#define TEGRA20_DAS_DAC_ID_2 1
84#define TEGRA_DAS_DAC_ID_3 2 84#define TEGRA20_DAS_DAC_ID_3 2
85 85
86struct tegra_das { 86struct tegra20_das {
87 struct device *dev; 87 struct device *dev;
88 void __iomem *regs; 88 void __iomem *regs;
89 struct dentry *debug; 89 struct dentry *debug;
@@ -107,29 +107,29 @@ struct tegra_das {
107 107
108/* 108/*
109 * Connect a DAP to to a DAC 109 * Connect a DAP to to a DAC
110 * dap_id: DAP to connect: TEGRA_DAS_DAP_ID_* 110 * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
111 * dac_sel: DAC to connect to: TEGRA_DAS_DAP_SEL_DAC* 111 * dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC*
112 */ 112 */
113extern int tegra_das_connect_dap_to_dac(int dap_id, int dac_sel); 113extern int tegra20_das_connect_dap_to_dac(int dap_id, int dac_sel);
114 114
115/* 115/*
116 * Connect a DAP to to another DAP 116 * Connect a DAP to to another DAP
117 * dap_id: DAP to connect: TEGRA_DAS_DAP_ID_* 117 * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
118 * other_dap_sel: DAP to connect to: TEGRA_DAS_DAP_SEL_DAP* 118 * other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP*
119 * master: Is this DAP the master (1) or slave (0) 119 * master: Is this DAP the master (1) or slave (0)
120 * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0) 120 * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0)
121 * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0) 121 * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0)
122 */ 122 */
123extern int tegra_das_connect_dap_to_dap(int dap_id, int other_dap_sel, 123extern int tegra20_das_connect_dap_to_dap(int dap_id, int other_dap_sel,
124 int master, int sdata1rx, 124 int master, int sdata1rx,
125 int sdata2rx); 125 int sdata2rx);
126 126
127/* 127/*
128 * Connect a DAC's input to a DAP 128 * Connect a DAC's input to a DAP
129 * (DAC outputs are selected by the DAP) 129 * (DAC outputs are selected by the DAP)
130 * dac_id: DAC ID to connect: TEGRA_DAS_DAC_ID_* 130 * dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_*
131 * dap_sel: DAP to receive input from: TEGRA_DAS_DAC_SEL_DAP* 131 * dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP*
132 */ 132 */
133extern int tegra_das_connect_dac_to_dap(int dac_id, int dap_sel); 133extern int tegra20_das_connect_dac_to_dap(int dac_id, int dap_sel);
134 134
135#endif 135#endif
diff --git a/sound/soc/tegra/tegra20_i2s.c b/sound/soc/tegra/tegra20_i2s.c
index e24759ae291b..878798c89e49 100644
--- a/sound/soc/tegra/tegra20_i2s.c
+++ b/sound/soc/tegra/tegra20_i2s.c
@@ -45,86 +45,86 @@
45 45
46#include "tegra20_i2s.h" 46#include "tegra20_i2s.h"
47 47
48#define DRV_NAME "tegra-i2s" 48#define DRV_NAME "tegra20-i2s"
49 49
50static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val) 50static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val)
51{ 51{
52 __raw_writel(val, i2s->regs + reg); 52 __raw_writel(val, i2s->regs + reg);
53} 53}
54 54
55static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg) 55static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg)
56{ 56{
57 return __raw_readl(i2s->regs + reg); 57 return __raw_readl(i2s->regs + reg);
58} 58}
59 59
60#ifdef CONFIG_DEBUG_FS 60#ifdef CONFIG_DEBUG_FS
61static int tegra_i2s_show(struct seq_file *s, void *unused) 61static int tegra20_i2s_show(struct seq_file *s, void *unused)
62{ 62{
63#define REG(r) { r, #r } 63#define REG(r) { r, #r }
64 static const struct { 64 static const struct {
65 int offset; 65 int offset;
66 const char *name; 66 const char *name;
67 } regs[] = { 67 } regs[] = {
68 REG(TEGRA_I2S_CTRL), 68 REG(TEGRA20_I2S_CTRL),
69 REG(TEGRA_I2S_STATUS), 69 REG(TEGRA20_I2S_STATUS),
70 REG(TEGRA_I2S_TIMING), 70 REG(TEGRA20_I2S_TIMING),
71 REG(TEGRA_I2S_FIFO_SCR), 71 REG(TEGRA20_I2S_FIFO_SCR),
72 REG(TEGRA_I2S_PCM_CTRL), 72 REG(TEGRA20_I2S_PCM_CTRL),
73 REG(TEGRA_I2S_NW_CTRL), 73 REG(TEGRA20_I2S_NW_CTRL),
74 REG(TEGRA_I2S_TDM_CTRL), 74 REG(TEGRA20_I2S_TDM_CTRL),
75 REG(TEGRA_I2S_TDM_TX_RX_CTRL), 75 REG(TEGRA20_I2S_TDM_TX_RX_CTRL),
76 }; 76 };
77#undef REG 77#undef REG
78 78
79 struct tegra_i2s *i2s = s->private; 79 struct tegra20_i2s *i2s = s->private;
80 int i; 80 int i;
81 81
82 for (i = 0; i < ARRAY_SIZE(regs); i++) { 82 for (i = 0; i < ARRAY_SIZE(regs); i++) {
83 u32 val = tegra_i2s_read(i2s, regs[i].offset); 83 u32 val = tegra20_i2s_read(i2s, regs[i].offset);
84 seq_printf(s, "%s = %08x\n", regs[i].name, val); 84 seq_printf(s, "%s = %08x\n", regs[i].name, val);
85 } 85 }
86 86
87 return 0; 87 return 0;
88} 88}
89 89
90static int tegra_i2s_debug_open(struct inode *inode, struct file *file) 90static int tegra20_i2s_debug_open(struct inode *inode, struct file *file)
91{ 91{
92 return single_open(file, tegra_i2s_show, inode->i_private); 92 return single_open(file, tegra20_i2s_show, inode->i_private);
93} 93}
94 94
95static const struct file_operations tegra_i2s_debug_fops = { 95static const struct file_operations tegra20_i2s_debug_fops = {
96 .open = tegra_i2s_debug_open, 96 .open = tegra20_i2s_debug_open,
97 .read = seq_read, 97 .read = seq_read,
98 .llseek = seq_lseek, 98 .llseek = seq_lseek,
99 .release = single_release, 99 .release = single_release,
100}; 100};
101 101
102static void tegra_i2s_debug_add(struct tegra_i2s *i2s) 102static void tegra20_i2s_debug_add(struct tegra20_i2s *i2s)
103{ 103{
104 i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO, 104 i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO,
105 snd_soc_debugfs_root, i2s, 105 snd_soc_debugfs_root, i2s,
106 &tegra_i2s_debug_fops); 106 &tegra20_i2s_debug_fops);
107} 107}
108 108
109static void tegra_i2s_debug_remove(struct tegra_i2s *i2s) 109static void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
110{ 110{
111 if (i2s->debug) 111 if (i2s->debug)
112 debugfs_remove(i2s->debug); 112 debugfs_remove(i2s->debug);
113} 113}
114#else 114#else
115static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id) 115static inline void tegra20_i2s_debug_add(struct tegra20_i2s *i2s, int id)
116{ 116{
117} 117}
118 118
119static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s) 119static inline void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
120{ 120{
121} 121}
122#endif 122#endif
123 123
124static int tegra_i2s_set_fmt(struct snd_soc_dai *dai, 124static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
125 unsigned int fmt) 125 unsigned int fmt)
126{ 126{
127 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai); 127 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
128 128
129 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 129 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
130 case SND_SOC_DAIFMT_NB_NF: 130 case SND_SOC_DAIFMT_NB_NF:
@@ -133,10 +133,10 @@ static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
133 return -EINVAL; 133 return -EINVAL;
134 } 134 }
135 135
136 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE; 136 i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE;
137 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 137 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
138 case SND_SOC_DAIFMT_CBS_CFS: 138 case SND_SOC_DAIFMT_CBS_CFS:
139 i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE; 139 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
140 break; 140 break;
141 case SND_SOC_DAIFMT_CBM_CFM: 141 case SND_SOC_DAIFMT_CBM_CFM:
142 break; 142 break;
@@ -144,28 +144,28 @@ static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
144 return -EINVAL; 144 return -EINVAL;
145 } 145 }
146 146
147 i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK | 147 i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
148 TEGRA_I2S_CTRL_LRCK_MASK); 148 TEGRA20_I2S_CTRL_LRCK_MASK);
149 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 149 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
150 case SND_SOC_DAIFMT_DSP_A: 150 case SND_SOC_DAIFMT_DSP_A:
151 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP; 151 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
152 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW; 152 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
153 break; 153 break;
154 case SND_SOC_DAIFMT_DSP_B: 154 case SND_SOC_DAIFMT_DSP_B:
155 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP; 155 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
156 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW; 156 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
157 break; 157 break;
158 case SND_SOC_DAIFMT_I2S: 158 case SND_SOC_DAIFMT_I2S:
159 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S; 159 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
160 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW; 160 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
161 break; 161 break;
162 case SND_SOC_DAIFMT_RIGHT_J: 162 case SND_SOC_DAIFMT_RIGHT_J:
163 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM; 163 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
164 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW; 164 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
165 break; 165 break;
166 case SND_SOC_DAIFMT_LEFT_J: 166 case SND_SOC_DAIFMT_LEFT_J:
167 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM; 167 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
168 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW; 168 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
169 break; 169 break;
170 default: 170 default:
171 return -EINVAL; 171 return -EINVAL;
@@ -174,27 +174,27 @@ static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
174 return 0; 174 return 0;
175} 175}
176 176
177static int tegra_i2s_hw_params(struct snd_pcm_substream *substream, 177static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
178 struct snd_pcm_hw_params *params, 178 struct snd_pcm_hw_params *params,
179 struct snd_soc_dai *dai) 179 struct snd_soc_dai *dai)
180{ 180{
181 struct device *dev = substream->pcm->card->dev; 181 struct device *dev = substream->pcm->card->dev;
182 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai); 182 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
183 u32 reg; 183 u32 reg;
184 int ret, sample_size, srate, i2sclock, bitcnt; 184 int ret, sample_size, srate, i2sclock, bitcnt;
185 185
186 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK; 186 i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
187 switch (params_format(params)) { 187 switch (params_format(params)) {
188 case SNDRV_PCM_FORMAT_S16_LE: 188 case SNDRV_PCM_FORMAT_S16_LE:
189 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16; 189 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_16;
190 sample_size = 16; 190 sample_size = 16;
191 break; 191 break;
192 case SNDRV_PCM_FORMAT_S24_LE: 192 case SNDRV_PCM_FORMAT_S24_LE:
193 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24; 193 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_24;
194 sample_size = 24; 194 sample_size = 24;
195 break; 195 break;
196 case SNDRV_PCM_FORMAT_S32_LE: 196 case SNDRV_PCM_FORMAT_S32_LE:
197 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32; 197 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_32;
198 sample_size = 32; 198 sample_size = 32;
199 break; 199 break;
200 default: 200 default:
@@ -213,54 +213,54 @@ static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
213 } 213 }
214 214
215 bitcnt = (i2sclock / (2 * srate)) - 1; 215 bitcnt = (i2sclock / (2 * srate)) - 1;
216 if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US) 216 if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
217 return -EINVAL; 217 return -EINVAL;
218 reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT; 218 reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
219 219
220 if (i2sclock % (2 * srate)) 220 if (i2sclock % (2 * srate))
221 reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE; 221 reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
222 222
223 clk_enable(i2s->clk_i2s); 223 clk_enable(i2s->clk_i2s);
224 224
225 tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg); 225 tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg);
226 226
227 tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR, 227 tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR,
228 TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | 228 TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
229 TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); 229 TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
230 230
231 clk_disable(i2s->clk_i2s); 231 clk_disable(i2s->clk_i2s);
232 232
233 return 0; 233 return 0;
234} 234}
235 235
236static void tegra_i2s_start_playback(struct tegra_i2s *i2s) 236static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
237{ 237{
238 i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE; 238 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO1_ENABLE;
239 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl); 239 tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
240} 240}
241 241
242static void tegra_i2s_stop_playback(struct tegra_i2s *i2s) 242static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
243{ 243{
244 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE; 244 i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE;
245 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl); 245 tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
246} 246}
247 247
248static void tegra_i2s_start_capture(struct tegra_i2s *i2s) 248static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
249{ 249{
250 i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE; 250 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO2_ENABLE;
251 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl); 251 tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
252} 252}
253 253
254static void tegra_i2s_stop_capture(struct tegra_i2s *i2s) 254static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
255{ 255{
256 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE; 256 i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE;
257 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl); 257 tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
258} 258}
259 259
260static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 260static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
261 struct snd_soc_dai *dai) 261 struct snd_soc_dai *dai)
262{ 262{
263 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai); 263 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
264 264
265 switch (cmd) { 265 switch (cmd) {
266 case SNDRV_PCM_TRIGGER_START: 266 case SNDRV_PCM_TRIGGER_START:
@@ -268,17 +268,17 @@ static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
268 case SNDRV_PCM_TRIGGER_RESUME: 268 case SNDRV_PCM_TRIGGER_RESUME:
269 clk_enable(i2s->clk_i2s); 269 clk_enable(i2s->clk_i2s);
270 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 270 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
271 tegra_i2s_start_playback(i2s); 271 tegra20_i2s_start_playback(i2s);
272 else 272 else
273 tegra_i2s_start_capture(i2s); 273 tegra20_i2s_start_capture(i2s);
274 break; 274 break;
275 case SNDRV_PCM_TRIGGER_STOP: 275 case SNDRV_PCM_TRIGGER_STOP:
276 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 276 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
277 case SNDRV_PCM_TRIGGER_SUSPEND: 277 case SNDRV_PCM_TRIGGER_SUSPEND:
278 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 278 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
279 tegra_i2s_stop_playback(i2s); 279 tegra20_i2s_stop_playback(i2s);
280 else 280 else
281 tegra_i2s_stop_capture(i2s); 281 tegra20_i2s_stop_capture(i2s);
282 clk_disable(i2s->clk_i2s); 282 clk_disable(i2s->clk_i2s);
283 break; 283 break;
284 default: 284 default:
@@ -288,9 +288,9 @@ static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
288 return 0; 288 return 0;
289} 289}
290 290
291static int tegra_i2s_probe(struct snd_soc_dai *dai) 291static int tegra20_i2s_probe(struct snd_soc_dai *dai)
292{ 292{
293 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai); 293 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
294 294
295 dai->capture_dma_data = &i2s->capture_dma_data; 295 dai->capture_dma_data = &i2s->capture_dma_data;
296 dai->playback_dma_data = &i2s->playback_dma_data; 296 dai->playback_dma_data = &i2s->playback_dma_data;
@@ -298,14 +298,14 @@ static int tegra_i2s_probe(struct snd_soc_dai *dai)
298 return 0; 298 return 0;
299} 299}
300 300
301static const struct snd_soc_dai_ops tegra_i2s_dai_ops = { 301static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
302 .set_fmt = tegra_i2s_set_fmt, 302 .set_fmt = tegra20_i2s_set_fmt,
303 .hw_params = tegra_i2s_hw_params, 303 .hw_params = tegra20_i2s_hw_params,
304 .trigger = tegra_i2s_trigger, 304 .trigger = tegra20_i2s_trigger,
305}; 305};
306 306
307static const struct snd_soc_dai_driver tegra_i2s_dai_template = { 307static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
308 .probe = tegra_i2s_probe, 308 .probe = tegra20_i2s_probe,
309 .playback = { 309 .playback = {
310 .channels_min = 2, 310 .channels_min = 2,
311 .channels_max = 2, 311 .channels_max = 2,
@@ -318,27 +318,27 @@ static const struct snd_soc_dai_driver tegra_i2s_dai_template = {
318 .rates = SNDRV_PCM_RATE_8000_96000, 318 .rates = SNDRV_PCM_RATE_8000_96000,
319 .formats = SNDRV_PCM_FMTBIT_S16_LE, 319 .formats = SNDRV_PCM_FMTBIT_S16_LE,
320 }, 320 },
321 .ops = &tegra_i2s_dai_ops, 321 .ops = &tegra20_i2s_dai_ops,
322 .symmetric_rates = 1, 322 .symmetric_rates = 1,
323}; 323};
324 324
325static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev) 325static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev)
326{ 326{
327 struct tegra_i2s *i2s; 327 struct tegra20_i2s *i2s;
328 struct resource *mem, *memregion, *dmareq; 328 struct resource *mem, *memregion, *dmareq;
329 u32 of_dma[2]; 329 u32 of_dma[2];
330 u32 dma_ch; 330 u32 dma_ch;
331 int ret; 331 int ret;
332 332
333 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra_i2s), GFP_KERNEL); 333 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
334 if (!i2s) { 334 if (!i2s) {
335 dev_err(&pdev->dev, "Can't allocate tegra_i2s\n"); 335 dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
336 ret = -ENOMEM; 336 ret = -ENOMEM;
337 goto err; 337 goto err;
338 } 338 }
339 dev_set_drvdata(&pdev->dev, i2s); 339 dev_set_drvdata(&pdev->dev, i2s);
340 340
341 i2s->dai = tegra_i2s_dai_template; 341 i2s->dai = tegra20_i2s_dai_template;
342 i2s->dai.name = dev_name(&pdev->dev); 342 i2s->dai.name = dev_name(&pdev->dev);
343 343
344 i2s->clk_i2s = clk_get(&pdev->dev, NULL); 344 i2s->clk_i2s = clk_get(&pdev->dev, NULL);
@@ -384,17 +384,17 @@ static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
384 goto err_clk_put; 384 goto err_clk_put;
385 } 385 }
386 386
387 i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2; 387 i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
388 i2s->capture_dma_data.wrap = 4; 388 i2s->capture_dma_data.wrap = 4;
389 i2s->capture_dma_data.width = 32; 389 i2s->capture_dma_data.width = 32;
390 i2s->capture_dma_data.req_sel = dma_ch; 390 i2s->capture_dma_data.req_sel = dma_ch;
391 391
392 i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1; 392 i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
393 i2s->playback_dma_data.wrap = 4; 393 i2s->playback_dma_data.wrap = 4;
394 i2s->playback_dma_data.width = 32; 394 i2s->playback_dma_data.width = 32;
395 i2s->playback_dma_data.req_sel = dma_ch; 395 i2s->playback_dma_data.req_sel = dma_ch;
396 396
397 i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED; 397 i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
398 398
399 ret = snd_soc_register_dai(&pdev->dev, &i2s->dai); 399 ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
400 if (ret) { 400 if (ret) {
@@ -409,7 +409,7 @@ static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
409 goto err_unregister_dai; 409 goto err_unregister_dai;
410 } 410 }
411 411
412 tegra_i2s_debug_add(i2s); 412 tegra20_i2s_debug_add(i2s);
413 413
414 return 0; 414 return 0;
415 415
@@ -421,38 +421,38 @@ err:
421 return ret; 421 return ret;
422} 422}
423 423
424static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev) 424static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev)
425{ 425{
426 struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev); 426 struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);
427 427
428 tegra_pcm_platform_unregister(&pdev->dev); 428 tegra_pcm_platform_unregister(&pdev->dev);
429 snd_soc_unregister_dai(&pdev->dev); 429 snd_soc_unregister_dai(&pdev->dev);
430 430
431 tegra_i2s_debug_remove(i2s); 431 tegra20_i2s_debug_remove(i2s);
432 432
433 clk_put(i2s->clk_i2s); 433 clk_put(i2s->clk_i2s);
434 434
435 return 0; 435 return 0;
436} 436}
437 437
438static const struct of_device_id tegra_i2s_of_match[] __devinitconst = { 438static const struct of_device_id tegra20_i2s_of_match[] __devinitconst = {
439 { .compatible = "nvidia,tegra20-i2s", }, 439 { .compatible = "nvidia,tegra20-i2s", },
440 {}, 440 {},
441}; 441};
442 442
443static struct platform_driver tegra_i2s_driver = { 443static struct platform_driver tegra20_i2s_driver = {
444 .driver = { 444 .driver = {
445 .name = DRV_NAME, 445 .name = DRV_NAME,
446 .owner = THIS_MODULE, 446 .owner = THIS_MODULE,
447 .of_match_table = tegra_i2s_of_match, 447 .of_match_table = tegra20_i2s_of_match,
448 }, 448 },
449 .probe = tegra_i2s_platform_probe, 449 .probe = tegra20_i2s_platform_probe,
450 .remove = __devexit_p(tegra_i2s_platform_remove), 450 .remove = __devexit_p(tegra20_i2s_platform_remove),
451}; 451};
452module_platform_driver(tegra_i2s_driver); 452module_platform_driver(tegra20_i2s_driver);
453 453
454MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 454MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
455MODULE_DESCRIPTION("Tegra I2S ASoC driver"); 455MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
456MODULE_LICENSE("GPL"); 456MODULE_LICENSE("GPL");
457MODULE_ALIAS("platform:" DRV_NAME); 457MODULE_ALIAS("platform:" DRV_NAME);
458MODULE_DEVICE_TABLE(of, tegra_i2s_of_match); 458MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);
diff --git a/sound/soc/tegra/tegra20_i2s.h b/sound/soc/tegra/tegra20_i2s.h
index 56f1e0f87c0b..86ab327dbd26 100644
--- a/sound/soc/tegra/tegra20_i2s.h
+++ b/sound/soc/tegra/tegra20_i2s.h
@@ -2,7 +2,7 @@
2 * tegra20_i2s.h - Definitions for Tegra20 I2S driver 2 * tegra20_i2s.h - Definitions for Tegra20 I2S driver
3 * 3 *
4 * Author: Stephen Warren <swarren@nvidia.com> 4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2010 - NVIDIA, Inc. 5 * Copyright (C) 2010,2012 - NVIDIA, Inc.
6 * 6 *
7 * Based on code copyright/by: 7 * Based on code copyright/by:
8 * 8 *
@@ -28,131 +28,131 @@
28 * 28 *
29 */ 29 */
30 30
31#ifndef __TEGRA_I2S_H__ 31#ifndef __TEGRA20_I2S_H__
32#define __TEGRA_I2S_H__ 32#define __TEGRA20_I2S_H__
33 33
34#include "tegra_pcm.h" 34#include "tegra_pcm.h"
35 35
36/* Register offsets from TEGRA_I2S1_BASE and TEGRA_I2S2_BASE */ 36/* Register offsets from TEGRA20_I2S1_BASE and TEGRA20_I2S2_BASE */
37 37
38#define TEGRA_I2S_CTRL 0x00 38#define TEGRA20_I2S_CTRL 0x00
39#define TEGRA_I2S_STATUS 0x04 39#define TEGRA20_I2S_STATUS 0x04
40#define TEGRA_I2S_TIMING 0x08 40#define TEGRA20_I2S_TIMING 0x08
41#define TEGRA_I2S_FIFO_SCR 0x0c 41#define TEGRA20_I2S_FIFO_SCR 0x0c
42#define TEGRA_I2S_PCM_CTRL 0x10 42#define TEGRA20_I2S_PCM_CTRL 0x10
43#define TEGRA_I2S_NW_CTRL 0x14 43#define TEGRA20_I2S_NW_CTRL 0x14
44#define TEGRA_I2S_TDM_CTRL 0x20 44#define TEGRA20_I2S_TDM_CTRL 0x20
45#define TEGRA_I2S_TDM_TX_RX_CTRL 0x24 45#define TEGRA20_I2S_TDM_TX_RX_CTRL 0x24
46#define TEGRA_I2S_FIFO1 0x40 46#define TEGRA20_I2S_FIFO1 0x40
47#define TEGRA_I2S_FIFO2 0x80 47#define TEGRA20_I2S_FIFO2 0x80
48 48
49/* Fields in TEGRA_I2S_CTRL */ 49/* Fields in TEGRA20_I2S_CTRL */
50 50
51#define TEGRA_I2S_CTRL_FIFO2_TX_ENABLE (1 << 30) 51#define TEGRA20_I2S_CTRL_FIFO2_TX_ENABLE (1 << 30)
52#define TEGRA_I2S_CTRL_FIFO1_ENABLE (1 << 29) 52#define TEGRA20_I2S_CTRL_FIFO1_ENABLE (1 << 29)
53#define TEGRA_I2S_CTRL_FIFO2_ENABLE (1 << 28) 53#define TEGRA20_I2S_CTRL_FIFO2_ENABLE (1 << 28)
54#define TEGRA_I2S_CTRL_FIFO1_RX_ENABLE (1 << 27) 54#define TEGRA20_I2S_CTRL_FIFO1_RX_ENABLE (1 << 27)
55#define TEGRA_I2S_CTRL_FIFO_LPBK_ENABLE (1 << 26) 55#define TEGRA20_I2S_CTRL_FIFO_LPBK_ENABLE (1 << 26)
56#define TEGRA_I2S_CTRL_MASTER_ENABLE (1 << 25) 56#define TEGRA20_I2S_CTRL_MASTER_ENABLE (1 << 25)
57 57
58#define TEGRA_I2S_LRCK_LEFT_LOW 0 58#define TEGRA20_I2S_LRCK_LEFT_LOW 0
59#define TEGRA_I2S_LRCK_RIGHT_LOW 1 59#define TEGRA20_I2S_LRCK_RIGHT_LOW 1
60 60
61#define TEGRA_I2S_CTRL_LRCK_SHIFT 24 61#define TEGRA20_I2S_CTRL_LRCK_SHIFT 24
62#define TEGRA_I2S_CTRL_LRCK_MASK (1 << TEGRA_I2S_CTRL_LRCK_SHIFT) 62#define TEGRA20_I2S_CTRL_LRCK_MASK (1 << TEGRA20_I2S_CTRL_LRCK_SHIFT)
63#define TEGRA_I2S_CTRL_LRCK_L_LOW (TEGRA_I2S_LRCK_LEFT_LOW << TEGRA_I2S_CTRL_LRCK_SHIFT) 63#define TEGRA20_I2S_CTRL_LRCK_L_LOW (TEGRA20_I2S_LRCK_LEFT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)
64#define TEGRA_I2S_CTRL_LRCK_R_LOW (TEGRA_I2S_LRCK_RIGHT_LOW << TEGRA_I2S_CTRL_LRCK_SHIFT) 64#define TEGRA20_I2S_CTRL_LRCK_R_LOW (TEGRA20_I2S_LRCK_RIGHT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)
65 65
66#define TEGRA_I2S_BIT_FORMAT_I2S 0 66#define TEGRA20_I2S_BIT_FORMAT_I2S 0
67#define TEGRA_I2S_BIT_FORMAT_RJM 1 67#define TEGRA20_I2S_BIT_FORMAT_RJM 1
68#define TEGRA_I2S_BIT_FORMAT_LJM 2 68#define TEGRA20_I2S_BIT_FORMAT_LJM 2
69#define TEGRA_I2S_BIT_FORMAT_DSP 3 69#define TEGRA20_I2S_BIT_FORMAT_DSP 3
70 70
71#define TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT 10 71#define TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT 10
72#define TEGRA_I2S_CTRL_BIT_FORMAT_MASK (3 << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT) 72#define TEGRA20_I2S_CTRL_BIT_FORMAT_MASK (3 << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
73#define TEGRA_I2S_CTRL_BIT_FORMAT_I2S (TEGRA_I2S_BIT_FORMAT_I2S << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT) 73#define TEGRA20_I2S_CTRL_BIT_FORMAT_I2S (TEGRA20_I2S_BIT_FORMAT_I2S << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
74#define TEGRA_I2S_CTRL_BIT_FORMAT_RJM (TEGRA_I2S_BIT_FORMAT_RJM << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT) 74#define TEGRA20_I2S_CTRL_BIT_FORMAT_RJM (TEGRA20_I2S_BIT_FORMAT_RJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
75#define TEGRA_I2S_CTRL_BIT_FORMAT_LJM (TEGRA_I2S_BIT_FORMAT_LJM << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT) 75#define TEGRA20_I2S_CTRL_BIT_FORMAT_LJM (TEGRA20_I2S_BIT_FORMAT_LJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
76#define TEGRA_I2S_CTRL_BIT_FORMAT_DSP (TEGRA_I2S_BIT_FORMAT_DSP << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT) 76#define TEGRA20_I2S_CTRL_BIT_FORMAT_DSP (TEGRA20_I2S_BIT_FORMAT_DSP << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
77 77
78#define TEGRA_I2S_BIT_SIZE_16 0 78#define TEGRA20_I2S_BIT_SIZE_16 0
79#define TEGRA_I2S_BIT_SIZE_20 1 79#define TEGRA20_I2S_BIT_SIZE_20 1
80#define TEGRA_I2S_BIT_SIZE_24 2 80#define TEGRA20_I2S_BIT_SIZE_24 2
81#define TEGRA_I2S_BIT_SIZE_32 3 81#define TEGRA20_I2S_BIT_SIZE_32 3
82 82
83#define TEGRA_I2S_CTRL_BIT_SIZE_SHIFT 8 83#define TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT 8
84#define TEGRA_I2S_CTRL_BIT_SIZE_MASK (3 << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT) 84#define TEGRA20_I2S_CTRL_BIT_SIZE_MASK (3 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
85#define TEGRA_I2S_CTRL_BIT_SIZE_16 (TEGRA_I2S_BIT_SIZE_16 << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT) 85#define TEGRA20_I2S_CTRL_BIT_SIZE_16 (TEGRA20_I2S_BIT_SIZE_16 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
86#define TEGRA_I2S_CTRL_BIT_SIZE_20 (TEGRA_I2S_BIT_SIZE_20 << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT) 86#define TEGRA20_I2S_CTRL_BIT_SIZE_20 (TEGRA20_I2S_BIT_SIZE_20 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
87#define TEGRA_I2S_CTRL_BIT_SIZE_24 (TEGRA_I2S_BIT_SIZE_24 << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT) 87#define TEGRA20_I2S_CTRL_BIT_SIZE_24 (TEGRA20_I2S_BIT_SIZE_24 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
88#define TEGRA_I2S_CTRL_BIT_SIZE_32 (TEGRA_I2S_BIT_SIZE_32 << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT) 88#define TEGRA20_I2S_CTRL_BIT_SIZE_32 (TEGRA20_I2S_BIT_SIZE_32 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
89 89
90#define TEGRA_I2S_FIFO_16_LSB 0 90#define TEGRA20_I2S_FIFO_16_LSB 0
91#define TEGRA_I2S_FIFO_20_LSB 1 91#define TEGRA20_I2S_FIFO_20_LSB 1
92#define TEGRA_I2S_FIFO_24_LSB 2 92#define TEGRA20_I2S_FIFO_24_LSB 2
93#define TEGRA_I2S_FIFO_32 3 93#define TEGRA20_I2S_FIFO_32 3
94#define TEGRA_I2S_FIFO_PACKED 7 94#define TEGRA20_I2S_FIFO_PACKED 7
95 95
96#define TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT 4 96#define TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT 4
97#define TEGRA_I2S_CTRL_FIFO_FORMAT_MASK (7 << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT) 97#define TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK (7 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
98#define TEGRA_I2S_CTRL_FIFO_FORMAT_16_LSB (TEGRA_I2S_FIFO_16_LSB << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT) 98#define TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB (TEGRA20_I2S_FIFO_16_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
99#define TEGRA_I2S_CTRL_FIFO_FORMAT_20_LSB (TEGRA_I2S_FIFO_20_LSB << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT) 99#define TEGRA20_I2S_CTRL_FIFO_FORMAT_20_LSB (TEGRA20_I2S_FIFO_20_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
100#define TEGRA_I2S_CTRL_FIFO_FORMAT_24_LSB (TEGRA_I2S_FIFO_24_LSB << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT) 100#define TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB (TEGRA20_I2S_FIFO_24_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
101#define TEGRA_I2S_CTRL_FIFO_FORMAT_32 (TEGRA_I2S_FIFO_32 << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT) 101#define TEGRA20_I2S_CTRL_FIFO_FORMAT_32 (TEGRA20_I2S_FIFO_32 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
102#define TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED (TEGRA_I2S_FIFO_PACKED << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT) 102#define TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED (TEGRA20_I2S_FIFO_PACKED << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
103 103
104#define TEGRA_I2S_CTRL_IE_FIFO1_ERR (1 << 3) 104#define TEGRA20_I2S_CTRL_IE_FIFO1_ERR (1 << 3)
105#define TEGRA_I2S_CTRL_IE_FIFO2_ERR (1 << 2) 105#define TEGRA20_I2S_CTRL_IE_FIFO2_ERR (1 << 2)
106#define TEGRA_I2S_CTRL_QE_FIFO1 (1 << 1) 106#define TEGRA20_I2S_CTRL_QE_FIFO1 (1 << 1)
107#define TEGRA_I2S_CTRL_QE_FIFO2 (1 << 0) 107#define TEGRA20_I2S_CTRL_QE_FIFO2 (1 << 0)
108 108
109/* Fields in TEGRA_I2S_STATUS */ 109/* Fields in TEGRA20_I2S_STATUS */
110 110
111#define TEGRA_I2S_STATUS_FIFO1_RDY (1 << 31) 111#define TEGRA20_I2S_STATUS_FIFO1_RDY (1 << 31)
112#define TEGRA_I2S_STATUS_FIFO2_RDY (1 << 30) 112#define TEGRA20_I2S_STATUS_FIFO2_RDY (1 << 30)
113#define TEGRA_I2S_STATUS_FIFO1_BSY (1 << 29) 113#define TEGRA20_I2S_STATUS_FIFO1_BSY (1 << 29)
114#define TEGRA_I2S_STATUS_FIFO2_BSY (1 << 28) 114#define TEGRA20_I2S_STATUS_FIFO2_BSY (1 << 28)
115#define TEGRA_I2S_STATUS_FIFO1_ERR (1 << 3) 115#define TEGRA20_I2S_STATUS_FIFO1_ERR (1 << 3)
116#define TEGRA_I2S_STATUS_FIFO2_ERR (1 << 2) 116#define TEGRA20_I2S_STATUS_FIFO2_ERR (1 << 2)
117#define TEGRA_I2S_STATUS_QS_FIFO1 (1 << 1) 117#define TEGRA20_I2S_STATUS_QS_FIFO1 (1 << 1)
118#define TEGRA_I2S_STATUS_QS_FIFO2 (1 << 0) 118#define TEGRA20_I2S_STATUS_QS_FIFO2 (1 << 0)
119 119
120/* Fields in TEGRA_I2S_TIMING */ 120/* Fields in TEGRA20_I2S_TIMING */
121 121
122#define TEGRA_I2S_TIMING_NON_SYM_ENABLE (1 << 12) 122#define TEGRA20_I2S_TIMING_NON_SYM_ENABLE (1 << 12)
123#define TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0 123#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0
124#define TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7fff 124#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7fff
125#define TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT) 125#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
126 126
127/* Fields in TEGRA_I2S_FIFO_SCR */ 127/* Fields in TEGRA20_I2S_FIFO_SCR */
128 128
129#define TEGRA_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24 129#define TEGRA20_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24
130#define TEGRA_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16 130#define TEGRA20_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16
131#define TEGRA_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK 0x3f 131#define TEGRA20_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK 0x3f
132 132
133#define TEGRA_I2S_FIFO_SCR_FIFO2_CLR (1 << 12) 133#define TEGRA20_I2S_FIFO_SCR_FIFO2_CLR (1 << 12)
134#define TEGRA_I2S_FIFO_SCR_FIFO1_CLR (1 << 8) 134#define TEGRA20_I2S_FIFO_SCR_FIFO1_CLR (1 << 8)
135 135
136#define TEGRA_I2S_FIFO_ATN_LVL_ONE_SLOT 0 136#define TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT 0
137#define TEGRA_I2S_FIFO_ATN_LVL_FOUR_SLOTS 1 137#define TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS 1
138#define TEGRA_I2S_FIFO_ATN_LVL_EIGHT_SLOTS 2 138#define TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS 2
139#define TEGRA_I2S_FIFO_ATN_LVL_TWELVE_SLOTS 3 139#define TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS 3
140 140
141#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT 4 141#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT 4
142#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK (3 << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT) 142#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
143#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT (TEGRA_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT) 143#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
144#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS (TEGRA_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT) 144#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
145#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS (TEGRA_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT) 145#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
146#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS (TEGRA_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT) 146#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
147 147
148#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT 0 148#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT 0
149#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK (3 << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT) 149#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
150#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT (TEGRA_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT) 150#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
151#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS (TEGRA_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT) 151#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
152#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS (TEGRA_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT) 152#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
153#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS (TEGRA_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT) 153#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
154 154
155struct tegra_i2s { 155struct tegra20_i2s {
156 struct snd_soc_dai_driver dai; 156 struct snd_soc_dai_driver dai;
157 struct clk *clk_i2s; 157 struct clk *clk_i2s;
158 struct tegra_pcm_dma_params capture_dma_data; 158 struct tegra_pcm_dma_params capture_dma_data;
diff --git a/sound/soc/tegra/tegra20_spdif.c b/sound/soc/tegra/tegra20_spdif.c
index ed1fd502ef8d..052bff816c4d 100644
--- a/sound/soc/tegra/tegra20_spdif.c
+++ b/sound/soc/tegra/tegra20_spdif.c
@@ -36,105 +36,105 @@
36 36
37#include "tegra20_spdif.h" 37#include "tegra20_spdif.h"
38 38
39#define DRV_NAME "tegra-spdif" 39#define DRV_NAME "tegra20-spdif"
40 40
41static inline void tegra_spdif_write(struct tegra_spdif *spdif, u32 reg, 41static inline void tegra20_spdif_write(struct tegra20_spdif *spdif, u32 reg,
42 u32 val) 42 u32 val)
43{ 43{
44 __raw_writel(val, spdif->regs + reg); 44 __raw_writel(val, spdif->regs + reg);
45} 45}
46 46
47static inline u32 tegra_spdif_read(struct tegra_spdif *spdif, u32 reg) 47static inline u32 tegra20_spdif_read(struct tegra20_spdif *spdif, u32 reg)
48{ 48{
49 return __raw_readl(spdif->regs + reg); 49 return __raw_readl(spdif->regs + reg);
50} 50}
51 51
52#ifdef CONFIG_DEBUG_FS 52#ifdef CONFIG_DEBUG_FS
53static int tegra_spdif_show(struct seq_file *s, void *unused) 53static int tegra20_spdif_show(struct seq_file *s, void *unused)
54{ 54{
55#define REG(r) { r, #r } 55#define REG(r) { r, #r }
56 static const struct { 56 static const struct {
57 int offset; 57 int offset;
58 const char *name; 58 const char *name;
59 } regs[] = { 59 } regs[] = {
60 REG(TEGRA_SPDIF_CTRL), 60 REG(TEGRA20_SPDIF_CTRL),
61 REG(TEGRA_SPDIF_STATUS), 61 REG(TEGRA20_SPDIF_STATUS),
62 REG(TEGRA_SPDIF_STROBE_CTRL), 62 REG(TEGRA20_SPDIF_STROBE_CTRL),
63 REG(TEGRA_SPDIF_DATA_FIFO_CSR), 63 REG(TEGRA20_SPDIF_DATA_FIFO_CSR),
64 REG(TEGRA_SPDIF_CH_STA_RX_A), 64 REG(TEGRA20_SPDIF_CH_STA_RX_A),
65 REG(TEGRA_SPDIF_CH_STA_RX_B), 65 REG(TEGRA20_SPDIF_CH_STA_RX_B),
66 REG(TEGRA_SPDIF_CH_STA_RX_C), 66 REG(TEGRA20_SPDIF_CH_STA_RX_C),
67 REG(TEGRA_SPDIF_CH_STA_RX_D), 67 REG(TEGRA20_SPDIF_CH_STA_RX_D),
68 REG(TEGRA_SPDIF_CH_STA_RX_E), 68 REG(TEGRA20_SPDIF_CH_STA_RX_E),
69 REG(TEGRA_SPDIF_CH_STA_RX_F), 69 REG(TEGRA20_SPDIF_CH_STA_RX_F),
70 REG(TEGRA_SPDIF_CH_STA_TX_A), 70 REG(TEGRA20_SPDIF_CH_STA_TX_A),
71 REG(TEGRA_SPDIF_CH_STA_TX_B), 71 REG(TEGRA20_SPDIF_CH_STA_TX_B),
72 REG(TEGRA_SPDIF_CH_STA_TX_C), 72 REG(TEGRA20_SPDIF_CH_STA_TX_C),
73 REG(TEGRA_SPDIF_CH_STA_TX_D), 73 REG(TEGRA20_SPDIF_CH_STA_TX_D),
74 REG(TEGRA_SPDIF_CH_STA_TX_E), 74 REG(TEGRA20_SPDIF_CH_STA_TX_E),
75 REG(TEGRA_SPDIF_CH_STA_TX_F), 75 REG(TEGRA20_SPDIF_CH_STA_TX_F),
76 }; 76 };
77#undef REG 77#undef REG
78 78
79 struct tegra_spdif *spdif = s->private; 79 struct tegra20_spdif *spdif = s->private;
80 int i; 80 int i;
81 81
82 for (i = 0; i < ARRAY_SIZE(regs); i++) { 82 for (i = 0; i < ARRAY_SIZE(regs); i++) {
83 u32 val = tegra_spdif_read(spdif, regs[i].offset); 83 u32 val = tegra20_spdif_read(spdif, regs[i].offset);
84 seq_printf(s, "%s = %08x\n", regs[i].name, val); 84 seq_printf(s, "%s = %08x\n", regs[i].name, val);
85 } 85 }
86 86
87 return 0; 87 return 0;
88} 88}
89 89
90static int tegra_spdif_debug_open(struct inode *inode, struct file *file) 90static int tegra20_spdif_debug_open(struct inode *inode, struct file *file)
91{ 91{
92 return single_open(file, tegra_spdif_show, inode->i_private); 92 return single_open(file, tegra20_spdif_show, inode->i_private);
93} 93}
94 94
95static const struct file_operations tegra_spdif_debug_fops = { 95static const struct file_operations tegra20_spdif_debug_fops = {
96 .open = tegra_spdif_debug_open, 96 .open = tegra20_spdif_debug_open,
97 .read = seq_read, 97 .read = seq_read,
98 .llseek = seq_lseek, 98 .llseek = seq_lseek,
99 .release = single_release, 99 .release = single_release,
100}; 100};
101 101
102static void tegra_spdif_debug_add(struct tegra_spdif *spdif) 102static void tegra20_spdif_debug_add(struct tegra20_spdif *spdif)
103{ 103{
104 spdif->debug = debugfs_create_file(DRV_NAME, S_IRUGO, 104 spdif->debug = debugfs_create_file(DRV_NAME, S_IRUGO,
105 snd_soc_debugfs_root, spdif, 105 snd_soc_debugfs_root, spdif,
106 &tegra_spdif_debug_fops); 106 &tegra20_spdif_debug_fops);
107} 107}
108 108
109static void tegra_spdif_debug_remove(struct tegra_spdif *spdif) 109static void tegra20_spdif_debug_remove(struct tegra20_spdif *spdif)
110{ 110{
111 if (spdif->debug) 111 if (spdif->debug)
112 debugfs_remove(spdif->debug); 112 debugfs_remove(spdif->debug);
113} 113}
114#else 114#else
115static inline void tegra_spdif_debug_add(struct tegra_spdif *spdif) 115static inline void tegra20_spdif_debug_add(struct tegra20_spdif *spdif)
116{ 116{
117} 117}
118 118
119static inline void tegra_spdif_debug_remove(struct tegra_spdif *spdif) 119static inline void tegra20_spdif_debug_remove(struct tegra20_spdif *spdif)
120{ 120{
121} 121}
122#endif 122#endif
123 123
124static int tegra_spdif_hw_params(struct snd_pcm_substream *substream, 124static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
125 struct snd_pcm_hw_params *params, 125 struct snd_pcm_hw_params *params,
126 struct snd_soc_dai *dai) 126 struct snd_soc_dai *dai)
127{ 127{
128 struct device *dev = substream->pcm->card->dev; 128 struct device *dev = substream->pcm->card->dev;
129 struct tegra_spdif *spdif = snd_soc_dai_get_drvdata(dai); 129 struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
130 int ret, spdifclock; 130 int ret, spdifclock;
131 131
132 spdif->reg_ctrl &= ~TEGRA_SPDIF_CTRL_PACK; 132 spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_PACK;
133 spdif->reg_ctrl &= ~TEGRA_SPDIF_CTRL_BIT_MODE_MASK; 133 spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
134 switch (params_format(params)) { 134 switch (params_format(params)) {
135 case SNDRV_PCM_FORMAT_S16_LE: 135 case SNDRV_PCM_FORMAT_S16_LE:
136 spdif->reg_ctrl |= TEGRA_SPDIF_CTRL_PACK; 136 spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_PACK;
137 spdif->reg_ctrl |= TEGRA_SPDIF_CTRL_BIT_MODE_16BIT; 137 spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
138 break; 138 break;
139 default: 139 default:
140 return -EINVAL; 140 return -EINVAL;
@@ -175,34 +175,34 @@ static int tegra_spdif_hw_params(struct snd_pcm_substream *substream,
175 return 0; 175 return 0;
176} 176}
177 177
178static void tegra_spdif_start_playback(struct tegra_spdif *spdif) 178static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
179{ 179{
180 spdif->reg_ctrl |= TEGRA_SPDIF_CTRL_TX_EN; 180 spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_TX_EN;
181 tegra_spdif_write(spdif, TEGRA_SPDIF_CTRL, spdif->reg_ctrl); 181 tegra20_spdif_write(spdif, TEGRA20_SPDIF_CTRL, spdif->reg_ctrl);
182} 182}
183 183
184static void tegra_spdif_stop_playback(struct tegra_spdif *spdif) 184static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
185{ 185{
186 spdif->reg_ctrl &= ~TEGRA_SPDIF_CTRL_TX_EN; 186 spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_TX_EN;
187 tegra_spdif_write(spdif, TEGRA_SPDIF_CTRL, spdif->reg_ctrl); 187 tegra20_spdif_write(spdif, TEGRA20_SPDIF_CTRL, spdif->reg_ctrl);
188} 188}
189 189
190static int tegra_spdif_trigger(struct snd_pcm_substream *substream, int cmd, 190static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
191 struct snd_soc_dai *dai) 191 struct snd_soc_dai *dai)
192{ 192{
193 struct tegra_spdif *spdif = snd_soc_dai_get_drvdata(dai); 193 struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
194 194
195 switch (cmd) { 195 switch (cmd) {
196 case SNDRV_PCM_TRIGGER_START: 196 case SNDRV_PCM_TRIGGER_START:
197 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 197 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
198 case SNDRV_PCM_TRIGGER_RESUME: 198 case SNDRV_PCM_TRIGGER_RESUME:
199 clk_enable(spdif->clk_spdif_out); 199 clk_enable(spdif->clk_spdif_out);
200 tegra_spdif_start_playback(spdif); 200 tegra20_spdif_start_playback(spdif);
201 break; 201 break;
202 case SNDRV_PCM_TRIGGER_STOP: 202 case SNDRV_PCM_TRIGGER_STOP:
203 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 203 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
204 case SNDRV_PCM_TRIGGER_SUSPEND: 204 case SNDRV_PCM_TRIGGER_SUSPEND:
205 tegra_spdif_stop_playback(spdif); 205 tegra20_spdif_stop_playback(spdif);
206 clk_disable(spdif->clk_spdif_out); 206 clk_disable(spdif->clk_spdif_out);
207 break; 207 break;
208 default: 208 default:
@@ -212,9 +212,9 @@ static int tegra_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
212 return 0; 212 return 0;
213} 213}
214 214
215static int tegra_spdif_probe(struct snd_soc_dai *dai) 215static int tegra20_spdif_probe(struct snd_soc_dai *dai)
216{ 216{
217 struct tegra_spdif *spdif = snd_soc_dai_get_drvdata(dai); 217 struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
218 218
219 dai->capture_dma_data = NULL; 219 dai->capture_dma_data = NULL;
220 dai->playback_dma_data = &spdif->playback_dma_data; 220 dai->playback_dma_data = &spdif->playback_dma_data;
@@ -222,14 +222,14 @@ static int tegra_spdif_probe(struct snd_soc_dai *dai)
222 return 0; 222 return 0;
223} 223}
224 224
225static const struct snd_soc_dai_ops tegra_spdif_dai_ops = { 225static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
226 .hw_params = tegra_spdif_hw_params, 226 .hw_params = tegra20_spdif_hw_params,
227 .trigger = tegra_spdif_trigger, 227 .trigger = tegra20_spdif_trigger,
228}; 228};
229 229
230static struct snd_soc_dai_driver tegra_spdif_dai = { 230static struct snd_soc_dai_driver tegra20_spdif_dai = {
231 .name = DRV_NAME, 231 .name = DRV_NAME,
232 .probe = tegra_spdif_probe, 232 .probe = tegra20_spdif_probe,
233 .playback = { 233 .playback = {
234 .channels_min = 2, 234 .channels_min = 2,
235 .channels_max = 2, 235 .channels_max = 2,
@@ -237,18 +237,18 @@ static struct snd_soc_dai_driver tegra_spdif_dai = {
237 SNDRV_PCM_RATE_48000, 237 SNDRV_PCM_RATE_48000,
238 .formats = SNDRV_PCM_FMTBIT_S16_LE, 238 .formats = SNDRV_PCM_FMTBIT_S16_LE,
239 }, 239 },
240 .ops = &tegra_spdif_dai_ops, 240 .ops = &tegra20_spdif_dai_ops,
241}; 241};
242 242
243static __devinit int tegra_spdif_platform_probe(struct platform_device *pdev) 243static __devinit int tegra20_spdif_platform_probe(struct platform_device *pdev)
244{ 244{
245 struct tegra_spdif *spdif; 245 struct tegra20_spdif *spdif;
246 struct resource *mem, *memregion, *dmareq; 246 struct resource *mem, *memregion, *dmareq;
247 int ret; 247 int ret;
248 248
249 spdif = kzalloc(sizeof(struct tegra_spdif), GFP_KERNEL); 249 spdif = kzalloc(sizeof(struct tegra20_spdif), GFP_KERNEL);
250 if (!spdif) { 250 if (!spdif) {
251 dev_err(&pdev->dev, "Can't allocate tegra_spdif\n"); 251 dev_err(&pdev->dev, "Can't allocate tegra20_spdif\n");
252 ret = -ENOMEM; 252 ret = -ENOMEM;
253 goto exit; 253 goto exit;
254 } 254 }
@@ -290,12 +290,12 @@ static __devinit int tegra_spdif_platform_probe(struct platform_device *pdev)
290 goto err_release; 290 goto err_release;
291 } 291 }
292 292
293 spdif->playback_dma_data.addr = mem->start + TEGRA_SPDIF_DATA_OUT; 293 spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
294 spdif->playback_dma_data.wrap = 4; 294 spdif->playback_dma_data.wrap = 4;
295 spdif->playback_dma_data.width = 32; 295 spdif->playback_dma_data.width = 32;
296 spdif->playback_dma_data.req_sel = dmareq->start; 296 spdif->playback_dma_data.req_sel = dmareq->start;
297 297
298 ret = snd_soc_register_dai(&pdev->dev, &tegra_spdif_dai); 298 ret = snd_soc_register_dai(&pdev->dev, &tegra20_spdif_dai);
299 if (ret) { 299 if (ret) {
300 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); 300 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
301 ret = -ENOMEM; 301 ret = -ENOMEM;
@@ -308,7 +308,7 @@ static __devinit int tegra_spdif_platform_probe(struct platform_device *pdev)
308 goto err_unregister_dai; 308 goto err_unregister_dai;
309 } 309 }
310 310
311 tegra_spdif_debug_add(spdif); 311 tegra20_spdif_debug_add(spdif);
312 312
313 return 0; 313 return 0;
314 314
@@ -326,15 +326,15 @@ exit:
326 return ret; 326 return ret;
327} 327}
328 328
329static int __devexit tegra_spdif_platform_remove(struct platform_device *pdev) 329static int __devexit tegra20_spdif_platform_remove(struct platform_device *pdev)
330{ 330{
331 struct tegra_spdif *spdif = dev_get_drvdata(&pdev->dev); 331 struct tegra20_spdif *spdif = dev_get_drvdata(&pdev->dev);
332 struct resource *res; 332 struct resource *res;
333 333
334 tegra_pcm_platform_unregister(&pdev->dev); 334 tegra_pcm_platform_unregister(&pdev->dev);
335 snd_soc_unregister_dai(&pdev->dev); 335 snd_soc_unregister_dai(&pdev->dev);
336 336
337 tegra_spdif_debug_remove(spdif); 337 tegra20_spdif_debug_remove(spdif);
338 338
339 iounmap(spdif->regs); 339 iounmap(spdif->regs);
340 340
@@ -348,18 +348,18 @@ static int __devexit tegra_spdif_platform_remove(struct platform_device *pdev)
348 return 0; 348 return 0;
349} 349}
350 350
351static struct platform_driver tegra_spdif_driver = { 351static struct platform_driver tegra20_spdif_driver = {
352 .driver = { 352 .driver = {
353 .name = DRV_NAME, 353 .name = DRV_NAME,
354 .owner = THIS_MODULE, 354 .owner = THIS_MODULE,
355 }, 355 },
356 .probe = tegra_spdif_platform_probe, 356 .probe = tegra20_spdif_platform_probe,
357 .remove = __devexit_p(tegra_spdif_platform_remove), 357 .remove = __devexit_p(tegra20_spdif_platform_remove),
358}; 358};
359 359
360module_platform_driver(tegra_spdif_driver); 360module_platform_driver(tegra20_spdif_driver);
361 361
362MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 362MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
363MODULE_DESCRIPTION("Tegra SPDIF ASoC driver"); 363MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
364MODULE_LICENSE("GPL"); 364MODULE_LICENSE("GPL");
365MODULE_ALIAS("platform:" DRV_NAME); 365MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/tegra/tegra20_spdif.h b/sound/soc/tegra/tegra20_spdif.h
index 001f9dcd2033..823af4c6bb7c 100644
--- a/sound/soc/tegra/tegra20_spdif.h
+++ b/sound/soc/tegra/tegra20_spdif.h
@@ -23,83 +23,83 @@
23 * 23 *
24 */ 24 */
25 25
26#ifndef __TEGRA_SPDIF_H__ 26#ifndef __TEGRA20_SPDIF_H__
27#define __TEGRA_SPDIF_H__ 27#define __TEGRA20_SPDIF_H__
28 28
29#include "tegra_pcm.h" 29#include "tegra_pcm.h"
30 30
31/* Offsets from TEGRA_SPDIF_BASE */ 31/* Offsets from TEGRA20_SPDIF_BASE */
32 32
33#define TEGRA_SPDIF_CTRL 0x0 33#define TEGRA20_SPDIF_CTRL 0x0
34#define TEGRA_SPDIF_STATUS 0x4 34#define TEGRA20_SPDIF_STATUS 0x4
35#define TEGRA_SPDIF_STROBE_CTRL 0x8 35#define TEGRA20_SPDIF_STROBE_CTRL 0x8
36#define TEGRA_SPDIF_DATA_FIFO_CSR 0x0C 36#define TEGRA20_SPDIF_DATA_FIFO_CSR 0x0C
37#define TEGRA_SPDIF_DATA_OUT 0x40 37#define TEGRA20_SPDIF_DATA_OUT 0x40
38#define TEGRA_SPDIF_DATA_IN 0x80 38#define TEGRA20_SPDIF_DATA_IN 0x80
39#define TEGRA_SPDIF_CH_STA_RX_A 0x100 39#define TEGRA20_SPDIF_CH_STA_RX_A 0x100
40#define TEGRA_SPDIF_CH_STA_RX_B 0x104 40#define TEGRA20_SPDIF_CH_STA_RX_B 0x104
41#define TEGRA_SPDIF_CH_STA_RX_C 0x108 41#define TEGRA20_SPDIF_CH_STA_RX_C 0x108
42#define TEGRA_SPDIF_CH_STA_RX_D 0x10C 42#define TEGRA20_SPDIF_CH_STA_RX_D 0x10C
43#define TEGRA_SPDIF_CH_STA_RX_E 0x110 43#define TEGRA20_SPDIF_CH_STA_RX_E 0x110
44#define TEGRA_SPDIF_CH_STA_RX_F 0x114 44#define TEGRA20_SPDIF_CH_STA_RX_F 0x114
45#define TEGRA_SPDIF_CH_STA_TX_A 0x140 45#define TEGRA20_SPDIF_CH_STA_TX_A 0x140
46#define TEGRA_SPDIF_CH_STA_TX_B 0x144 46#define TEGRA20_SPDIF_CH_STA_TX_B 0x144
47#define TEGRA_SPDIF_CH_STA_TX_C 0x148 47#define TEGRA20_SPDIF_CH_STA_TX_C 0x148
48#define TEGRA_SPDIF_CH_STA_TX_D 0x14C 48#define TEGRA20_SPDIF_CH_STA_TX_D 0x14C
49#define TEGRA_SPDIF_CH_STA_TX_E 0x150 49#define TEGRA20_SPDIF_CH_STA_TX_E 0x150
50#define TEGRA_SPDIF_CH_STA_TX_F 0x154 50#define TEGRA20_SPDIF_CH_STA_TX_F 0x154
51#define TEGRA_SPDIF_USR_STA_RX_A 0x180 51#define TEGRA20_SPDIF_USR_STA_RX_A 0x180
52#define TEGRA_SPDIF_USR_DAT_TX_A 0x1C0 52#define TEGRA20_SPDIF_USR_DAT_TX_A 0x1C0
53 53
54/* Fields in TEGRA_SPDIF_CTRL */ 54/* Fields in TEGRA20_SPDIF_CTRL */
55 55
56/* Start capturing from 0=right, 1=left channel */ 56/* Start capturing from 0=right, 1=left channel */
57#define TEGRA_SPDIF_CTRL_CAP_LC (1 << 30) 57#define TEGRA20_SPDIF_CTRL_CAP_LC (1 << 30)
58 58
59/* SPDIF receiver(RX) enable */ 59/* SPDIF receiver(RX) enable */
60#define TEGRA_SPDIF_CTRL_RX_EN (1 << 29) 60#define TEGRA20_SPDIF_CTRL_RX_EN (1 << 29)
61 61
62/* SPDIF Transmitter(TX) enable */ 62/* SPDIF Transmitter(TX) enable */
63#define TEGRA_SPDIF_CTRL_TX_EN (1 << 28) 63#define TEGRA20_SPDIF_CTRL_TX_EN (1 << 28)
64 64
65/* Transmit Channel status */ 65/* Transmit Channel status */
66#define TEGRA_SPDIF_CTRL_TC_EN (1 << 27) 66#define TEGRA20_SPDIF_CTRL_TC_EN (1 << 27)
67 67
68/* Transmit user Data */ 68/* Transmit user Data */
69#define TEGRA_SPDIF_CTRL_TU_EN (1 << 26) 69#define TEGRA20_SPDIF_CTRL_TU_EN (1 << 26)
70 70
71/* Interrupt on transmit error */ 71/* Interrupt on transmit error */
72#define TEGRA_SPDIF_CTRL_IE_TXE (1 << 25) 72#define TEGRA20_SPDIF_CTRL_IE_TXE (1 << 25)
73 73
74/* Interrupt on receive error */ 74/* Interrupt on receive error */
75#define TEGRA_SPDIF_CTRL_IE_RXE (1 << 24) 75#define TEGRA20_SPDIF_CTRL_IE_RXE (1 << 24)
76 76
77/* Interrupt on invalid preamble */ 77/* Interrupt on invalid preamble */
78#define TEGRA_SPDIF_CTRL_IE_P (1 << 23) 78#define TEGRA20_SPDIF_CTRL_IE_P (1 << 23)
79 79
80/* Interrupt on "B" preamble */ 80/* Interrupt on "B" preamble */
81#define TEGRA_SPDIF_CTRL_IE_B (1 << 22) 81#define TEGRA20_SPDIF_CTRL_IE_B (1 << 22)
82 82
83/* Interrupt when block of channel status received */ 83/* Interrupt when block of channel status received */
84#define TEGRA_SPDIF_CTRL_IE_C (1 << 21) 84#define TEGRA20_SPDIF_CTRL_IE_C (1 << 21)
85 85
86/* Interrupt when a valid information unit (IU) is received */ 86/* Interrupt when a valid information unit (IU) is received */
87#define TEGRA_SPDIF_CTRL_IE_U (1 << 20) 87#define TEGRA20_SPDIF_CTRL_IE_U (1 << 20)
88 88
89/* Interrupt when RX user FIFO attention level is reached */ 89/* Interrupt when RX user FIFO attention level is reached */
90#define TEGRA_SPDIF_CTRL_QE_RU (1 << 19) 90#define TEGRA20_SPDIF_CTRL_QE_RU (1 << 19)
91 91
92/* Interrupt when TX user FIFO attention level is reached */ 92/* Interrupt when TX user FIFO attention level is reached */
93#define TEGRA_SPDIF_CTRL_QE_TU (1 << 18) 93#define TEGRA20_SPDIF_CTRL_QE_TU (1 << 18)
94 94
95/* Interrupt when RX data FIFO attention level is reached */ 95/* Interrupt when RX data FIFO attention level is reached */
96#define TEGRA_SPDIF_CTRL_QE_RX (1 << 17) 96#define TEGRA20_SPDIF_CTRL_QE_RX (1 << 17)
97 97
98/* Interrupt when TX data FIFO attention level is reached */ 98/* Interrupt when TX data FIFO attention level is reached */
99#define TEGRA_SPDIF_CTRL_QE_TX (1 << 16) 99#define TEGRA20_SPDIF_CTRL_QE_TX (1 << 16)
100 100
101/* Loopback test mode enable */ 101/* Loopback test mode enable */
102#define TEGRA_SPDIF_CTRL_LBK_EN (1 << 15) 102#define TEGRA20_SPDIF_CTRL_LBK_EN (1 << 15)
103 103
104/* 104/*
105 * Pack data mode: 105 * Pack data mode:
@@ -107,7 +107,7 @@
107 * interface data bit size). 107 * interface data bit size).
108 * 1 = Packeted left/right channel data into a single word. 108 * 1 = Packeted left/right channel data into a single word.
109 */ 109 */
110#define TEGRA_SPDIF_CTRL_PACK (1 << 14) 110#define TEGRA20_SPDIF_CTRL_PACK (1 << 14)
111 111
112/* 112/*
113 * 00 = 16bit data 113 * 00 = 16bit data
@@ -115,19 +115,19 @@
115 * 10 = 24bit data 115 * 10 = 24bit data
116 * 11 = raw data 116 * 11 = raw data
117 */ 117 */
118#define TEGRA_SPDIF_BIT_MODE_16BIT 0 118#define TEGRA20_SPDIF_BIT_MODE_16BIT 0
119#define TEGRA_SPDIF_BIT_MODE_20BIT 1 119#define TEGRA20_SPDIF_BIT_MODE_20BIT 1
120#define TEGRA_SPDIF_BIT_MODE_24BIT 2 120#define TEGRA20_SPDIF_BIT_MODE_24BIT 2
121#define TEGRA_SPDIF_BIT_MODE_RAW 3 121#define TEGRA20_SPDIF_BIT_MODE_RAW 3
122 122
123#define TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT 12 123#define TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT 12
124#define TEGRA_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT) 124#define TEGRA20_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
125#define TEGRA_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA_SPDIF_BIT_MODE_16BIT << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT) 125#define TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA20_SPDIF_BIT_MODE_16BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
126#define TEGRA_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA_SPDIF_BIT_MODE_20BIT << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT) 126#define TEGRA20_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA20_SPDIF_BIT_MODE_20BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
127#define TEGRA_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA_SPDIF_BIT_MODE_24BIT << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT) 127#define TEGRA20_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA20_SPDIF_BIT_MODE_24BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
128#define TEGRA_SPDIF_CTRL_BIT_MODE_RAW (TEGRA_SPDIF_BIT_MODE_RAW << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT) 128#define TEGRA20_SPDIF_CTRL_BIT_MODE_RAW (TEGRA20_SPDIF_BIT_MODE_RAW << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
129 129
130/* Fields in TEGRA_SPDIF_STATUS */ 130/* Fields in TEGRA20_SPDIF_STATUS */
131 131
132/* 132/*
133 * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must 133 * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must
@@ -142,7 +142,7 @@
142 * (a) the end of a frame is reached after RX_EN is deeasserted, or 142 * (a) the end of a frame is reached after RX_EN is deeasserted, or
143 * (b) the SPDIF data stream becomes inactive. 143 * (b) the SPDIF data stream becomes inactive.
144 */ 144 */
145#define TEGRA_SPDIF_STATUS_RX_BSY (1 << 29) 145#define TEGRA20_SPDIF_STATUS_RX_BSY (1 << 29)
146 146
147/* 147/*
148 * Transmitter(TX) shifter is busy transmitting data. 148 * Transmitter(TX) shifter is busy transmitting data.
@@ -150,7 +150,7 @@
150 * This bit is deasserted when the end of a frame is reached after 150 * This bit is deasserted when the end of a frame is reached after
151 * TX_EN is deasserted. 151 * TX_EN is deasserted.
152 */ 152 */
153#define TEGRA_SPDIF_STATUS_TX_BSY (1 << 28) 153#define TEGRA20_SPDIF_STATUS_TX_BSY (1 << 28)
154 154
155/* 155/*
156 * TX is busy shifting out channel status. 156 * TX is busy shifting out channel status.
@@ -160,7 +160,7 @@
160 * (a) the end of a frame is reached after TX_EN is deasserted, or 160 * (a) the end of a frame is reached after TX_EN is deasserted, or
161 * (b) CH_STA_TX_F register is loaded into the internal shifter. 161 * (b) CH_STA_TX_F register is loaded into the internal shifter.
162 */ 162 */
163#define TEGRA_SPDIF_STATUS_TC_BSY (1 << 27) 163#define TEGRA20_SPDIF_STATUS_TC_BSY (1 << 27)
164 164
165/* 165/*
166 * TX User data FIFO busy. 166 * TX User data FIFO busy.
@@ -169,173 +169,173 @@
169 * (a) the end of a frame is reached after TX_EN is deasserted, or 169 * (a) the end of a frame is reached after TX_EN is deasserted, or
170 * (b) there's no data left in the TX user FIFO. 170 * (b) there's no data left in the TX user FIFO.
171 */ 171 */
172#define TEGRA_SPDIF_STATUS_TU_BSY (1 << 26) 172#define TEGRA20_SPDIF_STATUS_TU_BSY (1 << 26)
173 173
174/* TX FIFO Underrun error status */ 174/* TX FIFO Underrun error status */
175#define TEGRA_SPDIF_STATUS_TX_ERR (1 << 25) 175#define TEGRA20_SPDIF_STATUS_TX_ERR (1 << 25)
176 176
177/* RX FIFO Overrun error status */ 177/* RX FIFO Overrun error status */
178#define TEGRA_SPDIF_STATUS_RX_ERR (1 << 24) 178#define TEGRA20_SPDIF_STATUS_RX_ERR (1 << 24)
179 179
180/* Preamble status: 0=Preamble OK, 1=bad/missing preamble */ 180/* Preamble status: 0=Preamble OK, 1=bad/missing preamble */
181#define TEGRA_SPDIF_STATUS_IS_P (1 << 23) 181#define TEGRA20_SPDIF_STATUS_IS_P (1 << 23)
182 182
183/* B-preamble detection status: 0=not detected, 1=B-preamble detected */ 183/* B-preamble detection status: 0=not detected, 1=B-preamble detected */
184#define TEGRA_SPDIF_STATUS_IS_B (1 << 22) 184#define TEGRA20_SPDIF_STATUS_IS_B (1 << 22)
185 185
186/* 186/*
187 * RX channel block data receive status: 187 * RX channel block data receive status:
188 * 0=entire block not recieved yet. 188 * 0=entire block not recieved yet.
189 * 1=received entire block of channel status, 189 * 1=received entire block of channel status,
190 */ 190 */
191#define TEGRA_SPDIF_STATUS_IS_C (1 << 21) 191#define TEGRA20_SPDIF_STATUS_IS_C (1 << 21)
192 192
193/* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */ 193/* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */
194#define TEGRA_SPDIF_STATUS_IS_U (1 << 20) 194#define TEGRA20_SPDIF_STATUS_IS_U (1 << 20)
195 195
196/* 196/*
197 * RX User FIFO Status: 197 * RX User FIFO Status:
198 * 1=attention level reached, 0=attention level not reached. 198 * 1=attention level reached, 0=attention level not reached.
199 */ 199 */
200#define TEGRA_SPDIF_STATUS_QS_RU (1 << 19) 200#define TEGRA20_SPDIF_STATUS_QS_RU (1 << 19)
201 201
202/* 202/*
203 * TX User FIFO Status: 203 * TX User FIFO Status:
204 * 1=attention level reached, 0=attention level not reached. 204 * 1=attention level reached, 0=attention level not reached.
205 */ 205 */
206#define TEGRA_SPDIF_STATUS_QS_TU (1 << 18) 206#define TEGRA20_SPDIF_STATUS_QS_TU (1 << 18)
207 207
208/* 208/*
209 * RX Data FIFO Status: 209 * RX Data FIFO Status:
210 * 1=attention level reached, 0=attention level not reached. 210 * 1=attention level reached, 0=attention level not reached.
211 */ 211 */
212#define TEGRA_SPDIF_STATUS_QS_RX (1 << 17) 212#define TEGRA20_SPDIF_STATUS_QS_RX (1 << 17)
213 213
214/* 214/*
215 * TX Data FIFO Status: 215 * TX Data FIFO Status:
216 * 1=attention level reached, 0=attention level not reached. 216 * 1=attention level reached, 0=attention level not reached.
217 */ 217 */
218#define TEGRA_SPDIF_STATUS_QS_TX (1 << 16) 218#define TEGRA20_SPDIF_STATUS_QS_TX (1 << 16)
219 219
220/* Fields in TEGRA_SPDIF_STROBE_CTRL */ 220/* Fields in TEGRA20_SPDIF_STROBE_CTRL */
221 221
222/* 222/*
223 * Indicates the approximate number of detected SPDIFIN clocks within a 223 * Indicates the approximate number of detected SPDIFIN clocks within a
224 * bi-phase period. 224 * bi-phase period.
225 */ 225 */
226#define TEGRA_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16 226#define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16
227#define TEGRA_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA_SPDIF_STROBE_CTRL_PERIOD_SHIFT) 227#define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
228 228
229/* Data strobe mode: 0=Auto-locked 1=Manual locked */ 229/* Data strobe mode: 0=Auto-locked 1=Manual locked */
230#define TEGRA_SPDIF_STROBE_CTRL_STROBE (1 << 15) 230#define TEGRA20_SPDIF_STROBE_CTRL_STROBE (1 << 15)
231 231
232/* 232/*
233 * Manual data strobe time within the bi-phase clock period (in terms of 233 * Manual data strobe time within the bi-phase clock period (in terms of
234 * the number of over-sampling clocks). 234 * the number of over-sampling clocks).
235 */ 235 */
236#define TEGRA_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8 236#define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8
237#define TEGRA_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT) 237#define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT)
238 238
239/* 239/*
240 * Manual SPDIFIN bi-phase clock period (in terms of the number of 240 * Manual SPDIFIN bi-phase clock period (in terms of the number of
241 * over-sampling clocks). 241 * over-sampling clocks).
242 */ 242 */
243#define TEGRA_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0 243#define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0
244#define TEGRA_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT) 244#define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT)
245 245
246/* Fields in SPDIF_DATA_FIFO_CSR */ 246/* Fields in SPDIF_DATA_FIFO_CSR */
247 247
248/* Clear Receiver User FIFO (RX USR.FIFO) */ 248/* Clear Receiver User FIFO (RX USR.FIFO) */
249#define TEGRA_SPDIF_DATA_FIFO_CSR_RU_CLR (1 << 31) 249#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_CLR (1 << 31)
250 250
251#define TEGRA_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0 251#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0
252#define TEGRA_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS 1 252#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS 1
253#define TEGRA_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS 2 253#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS 2
254#define TEGRA_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS 3 254#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS 3
255 255
256/* RU FIFO attention level */ 256/* RU FIFO attention level */
257#define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT 29 257#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT 29
258#define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK \ 258#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK \
259 (0x3 << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 259 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
260#define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL \ 260#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL \
261 (TEGRA_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 261 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
262#define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL \ 262#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL \
263 (TEGRA_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 263 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
264#define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL \ 264#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL \
265 (TEGRA_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 265 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
266#define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL \ 266#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL \
267 (TEGRA_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) 267 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
268 268
269/* Number of RX USR.FIFO levels with valid data. */ 269/* Number of RX USR.FIFO levels with valid data. */
270#define TEGRA_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT 24 270#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT 24
271#define TEGRA_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT) 271#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT)
272 272
273/* Clear Transmitter User FIFO (TX USR.FIFO) */ 273/* Clear Transmitter User FIFO (TX USR.FIFO) */
274#define TEGRA_SPDIF_DATA_FIFO_CSR_TU_CLR (1 << 23) 274#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_CLR (1 << 23)
275 275
276/* TU FIFO attention level */ 276/* TU FIFO attention level */
277#define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT 21 277#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT 21
278#define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK \ 278#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK \
279 (0x3 << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 279 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
280#define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL \ 280#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL \
281 (TEGRA_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 281 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
282#define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL \ 282#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL \
283 (TEGRA_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 283 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
284#define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL \ 284#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL \
285 (TEGRA_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 285 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
286#define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL \ 286#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL \
287 (TEGRA_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) 287 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
288 288
289/* Number of TX USR.FIFO levels that could be filled. */ 289/* Number of TX USR.FIFO levels that could be filled. */
290#define TEGRA_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT 16 290#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT 16
291#define TEGRA_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT) 291#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT)
292 292
293/* Clear Receiver Data FIFO (RX DATA.FIFO) */ 293/* Clear Receiver Data FIFO (RX DATA.FIFO) */
294#define TEGRA_SPDIF_DATA_FIFO_CSR_RX_CLR (1 << 15) 294#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_CLR (1 << 15)
295 295
296#define TEGRA_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0 296#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0
297#define TEGRA_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS 1 297#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS 1
298#define TEGRA_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS 2 298#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS 2
299#define TEGRA_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS 3 299#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS 3
300 300
301/* RU FIFO attention level */ 301/* RU FIFO attention level */
302#define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT 13 302#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT 13
303#define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK \ 303#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK \
304 (0x3 << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 304 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
305#define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL \ 305#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL \
306 (TEGRA_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 306 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
307#define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL \ 307#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL \
308 (TEGRA_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 308 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
309#define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL \ 309#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL \
310 (TEGRA_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 310 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
311#define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL \ 311#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL \
312 (TEGRA_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) 312 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
313 313
314/* Number of RX DATA.FIFO levels with valid data. */ 314/* Number of RX DATA.FIFO levels with valid data. */
315#define TEGRA_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT 8 315#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT 8
316#define TEGRA_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT) 316#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT)
317 317
318/* Clear Transmitter Data FIFO (TX DATA.FIFO) */ 318/* Clear Transmitter Data FIFO (TX DATA.FIFO) */
319#define TEGRA_SPDIF_DATA_FIFO_CSR_TX_CLR (1 << 7) 319#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_CLR (1 << 7)
320 320
321/* TU FIFO attention level */ 321/* TU FIFO attention level */
322#define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT 5 322#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT 5
323#define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK \ 323#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK \
324 (0x3 << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 324 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
325#define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL \ 325#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL \
326 (TEGRA_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 326 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
327#define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL \ 327#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL \
328 (TEGRA_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 328 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
329#define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL \ 329#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL \
330 (TEGRA_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 330 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
331#define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL \ 331#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL \
332 (TEGRA_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) 332 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
333 333
334/* Number of TX DATA.FIFO levels that could be filled. */ 334/* Number of TX DATA.FIFO levels that could be filled. */
335#define TEGRA_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0 335#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0
336#define TEGRA_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT) 336#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT)
337 337
338/* Fields in TEGRA_SPDIF_DATA_OUT */ 338/* Fields in TEGRA20_SPDIF_DATA_OUT */
339 339
340/* 340/*
341 * This register has 5 different formats: 341 * This register has 5 different formats:
@@ -346,36 +346,36 @@
346 * 16-bit packed (BIT_MODE=00, PACK=1) 346 * 16-bit packed (BIT_MODE=00, PACK=1)
347 */ 347 */
348 348
349#define TEGRA_SPDIF_DATA_OUT_DATA_16_SHIFT 0 349#define TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT 0
350#define TEGRA_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA_SPDIF_DATA_OUT_DATA_16_SHIFT) 350#define TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT)
351 351
352#define TEGRA_SPDIF_DATA_OUT_DATA_20_SHIFT 0 352#define TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT 0
353#define TEGRA_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA_SPDIF_DATA_OUT_DATA_20_SHIFT) 353#define TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT)
354 354
355#define TEGRA_SPDIF_DATA_OUT_DATA_24_SHIFT 0 355#define TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT 0
356#define TEGRA_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA_SPDIF_DATA_OUT_DATA_24_SHIFT) 356#define TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT)
357 357
358#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_P (1 << 31) 358#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_P (1 << 31)
359#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_C (1 << 30) 359#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_C (1 << 30)
360#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_U (1 << 29) 360#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_U (1 << 29)
361#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_V (1 << 28) 361#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_V (1 << 28)
362 362
363#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT 8 363#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT 8
364#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT) 364#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT)
365 365
366#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT 4 366#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT 4
367#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT) 367#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT)
368 368
369#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0 369#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0
370#define TEGRA_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT) 370#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT)
371 371
372#define TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT 16 372#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT 16
373#define TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT) 373#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT)
374 374
375#define TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0 375#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0
376#define TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT) 376#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT)
377 377
378/* Fields in TEGRA_SPDIF_DATA_IN */ 378/* Fields in TEGRA20_SPDIF_DATA_IN */
379 379
380/* 380/*
381 * This register has 5 different formats: 381 * This register has 5 different formats:
@@ -388,44 +388,44 @@
388 * Bits 31:24 are common to all modes except 16-bit packed 388 * Bits 31:24 are common to all modes except 16-bit packed
389 */ 389 */
390 390
391#define TEGRA_SPDIF_DATA_IN_DATA_P (1 << 31) 391#define TEGRA20_SPDIF_DATA_IN_DATA_P (1 << 31)
392#define TEGRA_SPDIF_DATA_IN_DATA_C (1 << 30) 392#define TEGRA20_SPDIF_DATA_IN_DATA_C (1 << 30)
393#define TEGRA_SPDIF_DATA_IN_DATA_U (1 << 29) 393#define TEGRA20_SPDIF_DATA_IN_DATA_U (1 << 29)
394#define TEGRA_SPDIF_DATA_IN_DATA_V (1 << 28) 394#define TEGRA20_SPDIF_DATA_IN_DATA_V (1 << 28)
395 395
396#define TEGRA_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT 24 396#define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT 24
397#define TEGRA_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT) 397#define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT)
398 398
399#define TEGRA_SPDIF_DATA_IN_DATA_16_SHIFT 0 399#define TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT 0
400#define TEGRA_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA_SPDIF_DATA_IN_DATA_16_SHIFT) 400#define TEGRA20_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT)
401 401
402#define TEGRA_SPDIF_DATA_IN_DATA_20_SHIFT 0 402#define TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT 0
403#define TEGRA_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA_SPDIF_DATA_IN_DATA_20_SHIFT) 403#define TEGRA20_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT)
404 404
405#define TEGRA_SPDIF_DATA_IN_DATA_24_SHIFT 0 405#define TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT 0
406#define TEGRA_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA_SPDIF_DATA_IN_DATA_24_SHIFT) 406#define TEGRA20_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT)
407 407
408#define TEGRA_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT 8 408#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT 8
409#define TEGRA_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT) 409#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT)
410 410
411#define TEGRA_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT 4 411#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT 4
412#define TEGRA_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT) 412#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT)
413 413
414#define TEGRA_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0 414#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0
415#define TEGRA_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT) 415#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT)
416 416
417#define TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT 16 417#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT 16
418#define TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT) 418#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT)
419 419
420#define TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0 420#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0
421#define TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT) 421#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT)
422 422
423/* Fields in TEGRA_SPDIF_CH_STA_RX_A */ 423/* Fields in TEGRA20_SPDIF_CH_STA_RX_A */
424/* Fields in TEGRA_SPDIF_CH_STA_RX_B */ 424/* Fields in TEGRA20_SPDIF_CH_STA_RX_B */
425/* Fields in TEGRA_SPDIF_CH_STA_RX_C */ 425/* Fields in TEGRA20_SPDIF_CH_STA_RX_C */
426/* Fields in TEGRA_SPDIF_CH_STA_RX_D */ 426/* Fields in TEGRA20_SPDIF_CH_STA_RX_D */
427/* Fields in TEGRA_SPDIF_CH_STA_RX_E */ 427/* Fields in TEGRA20_SPDIF_CH_STA_RX_E */
428/* Fields in TEGRA_SPDIF_CH_STA_RX_F */ 428/* Fields in TEGRA20_SPDIF_CH_STA_RX_F */
429 429
430/* 430/*
431 * The 6-word receive channel data page buffer holds a block (192 frames) of 431 * The 6-word receive channel data page buffer holds a block (192 frames) of
@@ -433,12 +433,12 @@
433 * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A. 433 * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A.
434 */ 434 */
435 435
436/* Fields in TEGRA_SPDIF_CH_STA_TX_A */ 436/* Fields in TEGRA20_SPDIF_CH_STA_TX_A */
437/* Fields in TEGRA_SPDIF_CH_STA_TX_B */ 437/* Fields in TEGRA20_SPDIF_CH_STA_TX_B */
438/* Fields in TEGRA_SPDIF_CH_STA_TX_C */ 438/* Fields in TEGRA20_SPDIF_CH_STA_TX_C */
439/* Fields in TEGRA_SPDIF_CH_STA_TX_D */ 439/* Fields in TEGRA20_SPDIF_CH_STA_TX_D */
440/* Fields in TEGRA_SPDIF_CH_STA_TX_E */ 440/* Fields in TEGRA20_SPDIF_CH_STA_TX_E */
441/* Fields in TEGRA_SPDIF_CH_STA_TX_F */ 441/* Fields in TEGRA20_SPDIF_CH_STA_TX_F */
442 442
443/* 443/*
444 * The 6-word transmit channel data page buffer holds a block (192 frames) of 444 * The 6-word transmit channel data page buffer holds a block (192 frames) of
@@ -446,21 +446,21 @@
446 * bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A. 446 * bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A.
447 */ 447 */
448 448
449/* Fields in TEGRA_SPDIF_USR_STA_RX_A */ 449/* Fields in TEGRA20_SPDIF_USR_STA_RX_A */
450 450
451/* 451/*
452 * This 4-word deep FIFO receives user FIFO field information. The order of 452 * This 4-word deep FIFO receives user FIFO field information. The order of
453 * receive is from LSB to MSB bit. 453 * receive is from LSB to MSB bit.
454 */ 454 */
455 455
456/* Fields in TEGRA_SPDIF_USR_DAT_TX_A */ 456/* Fields in TEGRA20_SPDIF_USR_DAT_TX_A */
457 457
458/* 458/*
459 * This 4-word deep FIFO transmits user FIFO field information. The order of 459 * This 4-word deep FIFO transmits user FIFO field information. The order of
460 * transmission is from LSB to MSB bit. 460 * transmission is from LSB to MSB bit.
461 */ 461 */
462 462
463struct tegra_spdif { 463struct tegra20_spdif {
464 struct clk *clk_spdif_out; 464 struct clk *clk_spdif_out;
465 struct tegra_pcm_dma_params capture_dma_data; 465 struct tegra_pcm_dma_params capture_dma_data;
466 struct tegra_pcm_dma_params playback_dma_data; 466 struct tegra_pcm_dma_params playback_dma_data;
diff --git a/sound/soc/tegra/tegra_wm8903.c b/sound/soc/tegra/tegra_wm8903.c
index 2f9e9ff771c8..0b0df49d9d33 100644
--- a/sound/soc/tegra/tegra_wm8903.c
+++ b/sound/soc/tegra/tegra_wm8903.c
@@ -350,8 +350,8 @@ static struct snd_soc_dai_link tegra_wm8903_dai = {
350 .name = "WM8903", 350 .name = "WM8903",
351 .stream_name = "WM8903 PCM", 351 .stream_name = "WM8903 PCM",
352 .codec_name = "wm8903.0-001a", 352 .codec_name = "wm8903.0-001a",
353 .platform_name = "tegra-i2s.0", 353 .platform_name = "tegra20-i2s.0",
354 .cpu_dai_name = "tegra-i2s.0", 354 .cpu_dai_name = "tegra20-i2s.0",
355 .codec_dai_name = "wm8903-hifi", 355 .codec_dai_name = "wm8903-hifi",
356 .init = tegra_wm8903_init, 356 .init = tegra_wm8903_init,
357 .ops = &tegra_wm8903_ops, 357 .ops = &tegra_wm8903_ops,
diff --git a/sound/soc/tegra/trimslice.c b/sound/soc/tegra/trimslice.c
index 8884667aff43..0fd115e69a8a 100644
--- a/sound/soc/tegra/trimslice.c
+++ b/sound/soc/tegra/trimslice.c
@@ -116,8 +116,8 @@ static struct snd_soc_dai_link trimslice_tlv320aic23_dai = {
116 .name = "TLV320AIC23", 116 .name = "TLV320AIC23",
117 .stream_name = "AIC23", 117 .stream_name = "AIC23",
118 .codec_name = "tlv320aic23-codec.2-001a", 118 .codec_name = "tlv320aic23-codec.2-001a",
119 .platform_name = "tegra-i2s.0", 119 .platform_name = "tegra20-i2s.0",
120 .cpu_dai_name = "tegra-i2s.0", 120 .cpu_dai_name = "tegra20-i2s.0",
121 .codec_dai_name = "tlv320aic23-hifi", 121 .codec_dai_name = "tlv320aic23-hifi",
122 .ops = &trimslice_asoc_ops, 122 .ops = &trimslice_asoc_ops,
123}; 123};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 11:16:49 -0500