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authorTakashi Iwai <tiwai@suse.de>2005-11-17 04:21:19 -0500
committerJaroslav Kysela <perex@suse.cz>2006-01-03 06:16:37 -0500
commitbdbae7e62837c22c5399df0789a24e9d8a1d675f (patch)
tree4bffa9bf42f5b7541bc432f8b2437e8130278f88 /sound
parentc8eb6ba16a5803fab9cc0d1d0dd04a75bf91b6d5 (diff)
[ALSA] Remove snd_vx_delay() function
Replace snd_vx_delay() with appropriate delay/sleep functions. Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound')
-rw-r--r--sound/drivers/vx/vx_core.c19
-rw-r--r--sound/pci/vx222/vx222_ops.c14
-rw-r--r--sound/pcmcia/vx/vxp_ops.c10
3 files changed, 15 insertions, 28 deletions
diff --git a/sound/drivers/vx/vx_core.c b/sound/drivers/vx/vx_core.c
index 4697b1d75cbb..e6e4cf997419 100644
--- a/sound/drivers/vx/vx_core.c
+++ b/sound/drivers/vx/vx_core.c
@@ -41,18 +41,6 @@ MODULE_LICENSE("GPL");
41 41
42 42
43/* 43/*
44 * snd_vx_delay - delay for the specified time
45 * @xmsec: the time to delay in msec
46 */
47void snd_vx_delay(vx_core_t *chip, int xmsec)
48{
49 if (! in_interrupt() && xmsec >= 1000 / HZ)
50 msleep(xmsec);
51 else
52 mdelay(xmsec);
53}
54
55/*
56 * vx_check_reg_bit - wait for the specified bit is set/reset on a register 44 * vx_check_reg_bit - wait for the specified bit is set/reset on a register
57 * @reg: register to check 45 * @reg: register to check
58 * @mask: bit mask 46 * @mask: bit mask
@@ -76,7 +64,7 @@ int snd_vx_check_reg_bit(vx_core_t *chip, int reg, int mask, int bit, int time)
76 do { 64 do {
77 if ((snd_vx_inb(chip, reg) & mask) == bit) 65 if ((snd_vx_inb(chip, reg) & mask) == bit)
78 return 0; 66 return 0;
79 //snd_vx_delay(chip, 10); 67 //msleep(10);
80 } while (time_after_eq(end_time, jiffies)); 68 } while (time_after_eq(end_time, jiffies));
81 snd_printd(KERN_DEBUG "vx_check_reg_bit: timeout, reg=%s, mask=0x%x, val=0x%x\n", reg_names[reg], mask, snd_vx_inb(chip, reg)); 69 snd_printd(KERN_DEBUG "vx_check_reg_bit: timeout, reg=%s, mask=0x%x, val=0x%x\n", reg_names[reg], mask, snd_vx_inb(chip, reg));
82 return -EIO; 70 return -EIO;
@@ -664,7 +652,7 @@ int snd_vx_dsp_boot(vx_core_t *chip, const struct firmware *boot)
664 652
665 if ((err = snd_vx_load_boot_image(chip, boot)) < 0) 653 if ((err = snd_vx_load_boot_image(chip, boot)) < 0)
666 return err; 654 return err;
667 snd_vx_delay(chip, 10); 655 msleep(10);
668 656
669 return 0; 657 return 0;
670} 658}
@@ -704,7 +692,7 @@ int snd_vx_dsp_load(vx_core_t *chip, const struct firmware *dsp)
704 } 692 }
705 snd_printdd(KERN_DEBUG "checksum = 0x%08x\n", csum); 693 snd_printdd(KERN_DEBUG "checksum = 0x%08x\n", csum);
706 694
707 snd_vx_delay(chip, 200); 695 msleep(200);
708 696
709 if ((err = vx_wait_isr_bit(chip, ISR_CHK)) < 0) 697 if ((err = vx_wait_isr_bit(chip, ISR_CHK)) < 0)
710 return err; 698 return err;
@@ -831,7 +819,6 @@ EXPORT_SYMBOL(snd_vx_create);
831EXPORT_SYMBOL(snd_vx_setup_firmware); 819EXPORT_SYMBOL(snd_vx_setup_firmware);
832EXPORT_SYMBOL(snd_vx_free_firmware); 820EXPORT_SYMBOL(snd_vx_free_firmware);
833EXPORT_SYMBOL(snd_vx_irq_handler); 821EXPORT_SYMBOL(snd_vx_irq_handler);
834EXPORT_SYMBOL(snd_vx_delay);
835EXPORT_SYMBOL(snd_vx_dsp_boot); 822EXPORT_SYMBOL(snd_vx_dsp_boot);
836EXPORT_SYMBOL(snd_vx_dsp_load); 823EXPORT_SYMBOL(snd_vx_dsp_load);
837EXPORT_SYMBOL(snd_vx_load_boot_image); 824EXPORT_SYMBOL(snd_vx_load_boot_image);
diff --git a/sound/pci/vx222/vx222_ops.c b/sound/pci/vx222/vx222_ops.c
index 967bd5e6b23c..2d4d0c29b4c4 100644
--- a/sound/pci/vx222/vx222_ops.c
+++ b/sound/pci/vx222/vx222_ops.c
@@ -154,7 +154,7 @@ static void vx2_reset_dsp(vx_core_t *_chip)
154 /* set the reset dsp bit to 0 */ 154 /* set the reset dsp bit to 0 */
155 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK); 155 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
156 156
157 snd_vx_delay(_chip, XX_DSP_RESET_WAIT_TIME); 157 mdelay(XX_DSP_RESET_WAIT_TIME);
158 158
159 chip->regCDSP |= VX_CDSP_DSP_RESET_MASK; 159 chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
160 /* set the reset dsp bit to 1 */ 160 /* set the reset dsp bit to 1 */
@@ -362,10 +362,10 @@ static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx
362 /* XILINX reset (wait at least 1 milisecond between reset on and off). */ 362 /* XILINX reset (wait at least 1 milisecond between reset on and off). */
363 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK); 363 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
364 vx_inl(chip, CNTRL); 364 vx_inl(chip, CNTRL);
365 snd_vx_delay(chip, 10); 365 msleep(10);
366 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE); 366 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
367 vx_inl(chip, CNTRL); 367 vx_inl(chip, CNTRL);
368 snd_vx_delay(chip, 10); 368 msleep(10);
369 369
370 if (chip->type == VX_TYPE_BOARD) 370 if (chip->type == VX_TYPE_BOARD)
371 port = VX_CNTRL; 371 port = VX_CNTRL;
@@ -381,7 +381,7 @@ static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx
381 } 381 }
382 put_xilinx_data(chip, port, 4, 0xff); /* end signature */ 382 put_xilinx_data(chip, port, 4, 0xff); /* end signature */
383 383
384 snd_vx_delay(chip, 200); 384 msleep(200);
385 385
386 /* test after loading (is buggy with VX222) */ 386 /* test after loading (is buggy with VX222) */
387 if (chip->type != VX_TYPE_BOARD) { 387 if (chip->type != VX_TYPE_BOARD) {
@@ -720,17 +720,17 @@ static void vx2_reset_codec(vx_core_t *_chip)
720 /* Set the reset CODEC bit to 0. */ 720 /* Set the reset CODEC bit to 0. */
721 vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK); 721 vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
722 vx_inl(chip, CDSP); 722 vx_inl(chip, CDSP);
723 snd_vx_delay(_chip, 10); 723 msleep(10);
724 /* Set the reset CODEC bit to 1. */ 724 /* Set the reset CODEC bit to 1. */
725 chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK; 725 chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
726 vx_outl(chip, CDSP, chip->regCDSP); 726 vx_outl(chip, CDSP, chip->regCDSP);
727 vx_inl(chip, CDSP); 727 vx_inl(chip, CDSP);
728 if (_chip->type == VX_TYPE_BOARD) { 728 if (_chip->type == VX_TYPE_BOARD) {
729 snd_vx_delay(_chip, 1); 729 msleep(1);
730 return; 730 return;
731 } 731 }
732 732
733 snd_vx_delay(_chip, 5); /* additionnel wait time for AKM's */ 733 msleep(5); /* additionnel wait time for AKM's */
734 734
735 vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */ 735 vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
736 736
diff --git a/sound/pcmcia/vx/vxp_ops.c b/sound/pcmcia/vx/vxp_ops.c
index 6f15c3d03ab5..2754d657a4d6 100644
--- a/sound/pcmcia/vx/vxp_ops.c
+++ b/sound/pcmcia/vx/vxp_ops.c
@@ -96,7 +96,7 @@ static int vx_check_magic(vx_core_t *chip)
96 c = vx_inb(chip, CDSP); 96 c = vx_inb(chip, CDSP);
97 if (c == CDSP_MAGIC) 97 if (c == CDSP_MAGIC)
98 return 0; 98 return 0;
99 snd_vx_delay(chip, 10); 99 msleep(10);
100 } while (time_after_eq(end_time, jiffies)); 100 } while (time_after_eq(end_time, jiffies));
101 snd_printk(KERN_ERR "cannot find xilinx magic word (%x)\n", c); 101 snd_printk(KERN_ERR "cannot find xilinx magic word (%x)\n", c);
102 return -EIO; 102 return -EIO;
@@ -134,12 +134,12 @@ static void vxp_reset_codec(vx_core_t *_chip)
134 /* Set the reset CODEC bit to 1. */ 134 /* Set the reset CODEC bit to 1. */
135 vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK); 135 vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK);
136 vx_inb(chip, CDSP); 136 vx_inb(chip, CDSP);
137 snd_vx_delay(_chip, 10); 137 msleep(10);
138 /* Set the reset CODEC bit to 0. */ 138 /* Set the reset CODEC bit to 0. */
139 chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK; 139 chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK;
140 vx_outb(chip, CDSP, chip->regCDSP); 140 vx_outb(chip, CDSP, chip->regCDSP);
141 vx_inb(chip, CDSP); 141 vx_inb(chip, CDSP);
142 snd_vx_delay(_chip, 1); 142 msleep(1);
143} 143}
144 144
145/* 145/*
@@ -207,7 +207,7 @@ static int vxp_load_xilinx_binary(vx_core_t *_chip, const struct firmware *fw)
207 vx_outb(chip, ICR, ICR_HF0); 207 vx_outb(chip, ICR, ICR_HF0);
208 208
209 /* TEMPO 250ms : wait until Xilinx is downloaded */ 209 /* TEMPO 250ms : wait until Xilinx is downloaded */
210 snd_vx_delay(_chip, 300); 210 msleep(300);
211 211
212 /* test magical word */ 212 /* test magical word */
213 if (vx_check_magic(_chip) < 0) 213 if (vx_check_magic(_chip) < 0)
@@ -221,7 +221,7 @@ static int vxp_load_xilinx_binary(vx_core_t *_chip, const struct firmware *fw)
221 chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK; 221 chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
222 vx_outb(chip, DIALOG, chip->regDIALOG); 222 vx_outb(chip, DIALOG, chip->regDIALOG);
223 vx_inb(chip, DIALOG); 223 vx_inb(chip, DIALOG);
224 snd_vx_delay(_chip, 10); 224 msleep(10);
225 chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK; 225 chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
226 vx_outb(chip, DIALOG, chip->regDIALOG); 226 vx_outb(chip, DIALOG, chip->regDIALOG);
227 vx_inb(chip, DIALOG); 227 vx_inb(chip, DIALOG);