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authorSudhakar Rajashekhara <sudhakar.raj@ti.com>2009-05-21 07:41:35 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-08-26 03:56:56 -0400
commit60902a2cb12c3c1682ee7a04ad7448ec16dc0c29 (patch)
treeba754bff7fadd7106dc9f8549136a514177d0fd1 /sound
parent4c5adde7943b982d22a7bf711654fbb5cb810667 (diff)
davinci: EDMA: multiple CCs, channel mapping and API changes
- restructure to support multiple channel controllers by using additional struct resources for each CC - interface changes visible to EDMA clients Introduce macros to build IDs from controller and channel number, and to extract them. Modify the edma_alloc_slot function to take an extra argument for the controller. Also update ASoC drivers to use API. ASoC changes Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> - Move queue related mappings to dm<soc>.c EDMA in DM355 and DM644x has two transfer controllers while DM646x has four transfer controllers. Moving the queue to tc mapping and queue priority mapping to dm<soc>.c will be helpful to probe these mappings from platform device so that the machine_is_* testing will be avoided. - add channel mapping logic Channel mapping logic is introduced in dm646x EDMA. This implies that there is no fixed association for a channel number to a parameter entry number. In other words, using the DMA channel mapping registers (DCHMAPn), a PaRAM entry can be mapped to any channel. While in the case of dm644x and dm355 there is a fixed mapping between the EDMA channel and Param entry number. Signed-off-by: Naresh Medisetty <naresh@ti.com> Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Reviewed-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/davinci/davinci-pcm.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
index a05996588489..3ee38b62766d 100644
--- a/sound/soc/davinci/davinci-pcm.c
+++ b/sound/soc/davinci/davinci-pcm.c
@@ -143,7 +143,7 @@ static int davinci_pcm_dma_request(struct snd_pcm_substream *substream)
143 prtd->master_lch = ret; 143 prtd->master_lch = ret;
144 144
145 /* Request parameter RAM reload slot */ 145 /* Request parameter RAM reload slot */
146 ret = edma_alloc_slot(EDMA_SLOT_ANY); 146 ret = edma_alloc_slot(EDMA_CTLR(prtd->master_lch), EDMA_SLOT_ANY);
147 if (ret < 0) { 147 if (ret < 0) {
148 edma_free_channel(prtd->master_lch); 148 edma_free_channel(prtd->master_lch);
149 return ret; 149 return ret;
@@ -160,8 +160,8 @@ static int davinci_pcm_dma_request(struct snd_pcm_substream *substream)
160 * so davinci_pcm_enqueue_dma() takes less time in IRQ. 160 * so davinci_pcm_enqueue_dma() takes less time in IRQ.
161 */ 161 */
162 edma_read_slot(prtd->slave_lch, &p_ram); 162 edma_read_slot(prtd->slave_lch, &p_ram);
163 p_ram.opt |= TCINTEN | EDMA_TCC(prtd->master_lch); 163 p_ram.opt |= TCINTEN | EDMA_TCC(EDMA_CHAN_SLOT(prtd->master_lch));
164 p_ram.link_bcntrld = prtd->slave_lch << 5; 164 p_ram.link_bcntrld = EDMA_CHAN_SLOT(prtd->slave_lch) << 5;
165 edma_write_slot(prtd->slave_lch, &p_ram); 165 edma_write_slot(prtd->slave_lch, &p_ram);
166 166
167 return 0; 167 return 0;