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authorSascha Hauer <s.hauer@pengutronix.de>2009-11-25 10:41:04 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-01-17 06:09:46 -0500
commit8380222ec9458d38a4e0cc3cb688ad7fff311df4 (patch)
treedb2774ff28b93f437bcf217f1b10337a8d4fd9b5 /sound
parent53242c68333570631a15a69842851b458eca3d99 (diff)
ASoC: Add a new imx-ssi sound driver
The old driver has the number of SSI units in the system hardcoded, does not make use of the device model and works only on i.MX21/27. This driver replaces it. It works in DMA mode on i.MX21/27 and using an FIQ handler on other systems. It also supports AC97 mode of the SSI units. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Javier Martin <javier.martin@vista-silicon.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/imx/Kconfig20
-rw-r--r--sound/soc/imx/Makefile12
-rw-r--r--sound/soc/imx/imx-pcm-dma-mx2.c313
-rw-r--r--sound/soc/imx/imx-pcm-fiq.c277
-rw-r--r--sound/soc/imx/imx-ssi.c762
-rw-r--r--sound/soc/imx/imx-ssi.h238
6 files changed, 1602 insertions, 20 deletions
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index a700562e8692..84a25e61bed8 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -1,21 +1,13 @@
1config SND_MX1_MX2_SOC 1config SND_IMX_SOC
2 tristate "SoC Audio for Freecale i.MX1x i.MX2x CPUs" 2 tristate "SoC Audio for Freecale i.MX CPUs"
3 depends on ARCH_MX2 || ARCH_MX1 3 depends on ARCH_MXC
4 select SND_PCM 4 select SND_PCM
5 select FIQ
6 select SND_SOC_AC97_BUS
5 help 7 help
6 Say Y or M if you want to add support for codecs attached to 8 Say Y or M if you want to add support for codecs attached to
7 the MX1 or MX2 SSI interface. 9 the i.MX SSI interface.
8 10
9config SND_MXC_SOC_SSI 11config SND_MXC_SOC_SSI
10 tristate 12 tristate
11 13
12config SND_SOC_MX27VIS_WM8974
13 tristate "SoC Audio support for MX27 - WM8974 Visstrim_sm10 board"
14 depends on SND_MX1_MX2_SOC && MACH_MX27 && MACH_IMX27_VISSTRIM_M10
15 select SND_MXC_SOC_SSI
16 select SND_SOC_WM8974
17 help
18 Say Y if you want to add support for SoC audio on Visstrim SM10
19 board with WM8974.
20
21
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
index c2ffd2c8df5a..4bde34a3a878 100644
--- a/sound/soc/imx/Makefile
+++ b/sound/soc/imx/Makefile
@@ -1,10 +1,10 @@
1# i.MX Platform Support 1# i.MX Platform Support
2snd-soc-mx1_mx2-objs := mx1_mx2-pcm.o 2snd-soc-imx-objs := imx-ssi.o imx-pcm-fiq.o imx-pcm-dma-mx2.o
3snd-soc-mxc-ssi-objs := mxc-ssi.o
4 3
5obj-$(CONFIG_SND_MX1_MX2_SOC) += snd-soc-mx1_mx2.o 4ifdef CONFIG_MACH_MX27
6obj-$(CONFIG_SND_MXC_SOC_SSI) += snd-soc-mxc-ssi.o 5snd-soc-imx-objs += imx-pcm-dma-mx2.o
6endif
7
8obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o
7 9
8# i.MX Machine Support 10# i.MX Machine Support
9snd-soc-mx27vis-wm8974-objs := mx27vis_wm8974.o
10obj-$(CONFIG_SND_SOC_MX27VIS_WM8974) += snd-soc-mx27vis-wm8974.o
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/imx/imx-pcm-dma-mx2.c
new file mode 100644
index 000000000000..19452e44afdc
--- /dev/null
+++ b/sound/soc/imx/imx-pcm-dma-mx2.c
@@ -0,0 +1,313 @@
1/*
2 * imx-pcm-dma-mx2.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This code is based on code copyrighted by Freescale,
7 * Liam Girdwood, Javier Martin and probably others.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/dma-mapping.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22
23#include <sound/core.h>
24#include <sound/initval.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28
29#include <mach/dma-mx1-mx2.h>
30
31#include "imx-ssi.h"
32
33struct imx_pcm_runtime_data {
34 int sg_count;
35 struct scatterlist *sg_list;
36 int period;
37 int periods;
38 unsigned long dma_addr;
39 int dma;
40 struct snd_pcm_substream *substream;
41 unsigned long offset;
42 unsigned long size;
43 unsigned long period_cnt;
44 void *buf;
45 int period_time;
46};
47
48/* Called by the DMA framework when a period has elapsed */
49static void imx_ssi_dma_progression(int channel, void *data,
50 struct scatterlist *sg)
51{
52 struct snd_pcm_substream *substream = data;
53 struct snd_pcm_runtime *runtime = substream->runtime;
54 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
55
56 if (!sg)
57 return;
58
59 runtime = iprtd->substream->runtime;
60
61 iprtd->offset = sg->dma_address - runtime->dma_addr;
62
63 snd_pcm_period_elapsed(iprtd->substream);
64}
65
66static void imx_ssi_dma_callback(int channel, void *data)
67{
68 pr_err("%s shouldn't be called\n", __func__);
69}
70
71static void snd_imx_dma_err_callback(int channel, void *data, int err)
72{
73 pr_err("DMA error callback called\n");
74
75 pr_err("DMA timeout on channel %d -%s%s%s%s\n",
76 channel,
77 err & IMX_DMA_ERR_BURST ? " burst" : "",
78 err & IMX_DMA_ERR_REQUEST ? " request" : "",
79 err & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
80 err & IMX_DMA_ERR_BUFFER ? " buffer" : "");
81}
82
83static int imx_ssi_dma_alloc(struct snd_pcm_substream *substream)
84{
85 struct snd_soc_pcm_runtime *rtd = substream->private_data;
86 struct imx_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
87 struct snd_pcm_runtime *runtime = substream->runtime;
88 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
89 int ret;
90
91 iprtd->dma = imx_dma_request_by_prio(DRV_NAME, DMA_PRIO_HIGH);
92 if (iprtd->dma < 0) {
93 pr_err("Failed to claim the audio DMA\n");
94 return -ENODEV;
95 }
96
97 ret = imx_dma_setup_handlers(iprtd->dma,
98 imx_ssi_dma_callback,
99 snd_imx_dma_err_callback, substream);
100 if (ret)
101 goto out;
102
103 ret = imx_dma_setup_progression_handler(iprtd->dma,
104 imx_ssi_dma_progression);
105 if (ret) {
106 pr_err("Failed to setup the DMA handler\n");
107 goto out;
108 }
109
110 ret = imx_dma_config_channel(iprtd->dma,
111 IMX_DMA_MEMSIZE_16 | IMX_DMA_TYPE_FIFO,
112 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
113 dma_params->dma, 1);
114 if (ret < 0) {
115 pr_err("Cannot configure DMA channel: %d\n", ret);
116 goto out;
117 }
118
119 imx_dma_config_burstlen(iprtd->dma, dma_params->burstsize * 2);
120
121 return 0;
122out:
123 imx_dma_free(iprtd->dma);
124 return ret;
125}
126
127static int snd_imx_pcm_hw_params(struct snd_pcm_substream *substream,
128 struct snd_pcm_hw_params *params)
129{
130 struct snd_pcm_runtime *runtime = substream->runtime;
131 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
132 int i;
133 unsigned long dma_addr;
134
135 imx_ssi_dma_alloc(substream);
136
137 iprtd->size = params_buffer_bytes(params);
138 iprtd->periods = params_periods(params);
139 iprtd->period = params_period_bytes(params);
140 iprtd->offset = 0;
141 iprtd->period_time = HZ / (params_rate(params) /
142 params_period_size(params));
143
144 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
145
146 if (iprtd->sg_count != iprtd->periods) {
147 kfree(iprtd->sg_list);
148
149 iprtd->sg_list = kcalloc(iprtd->periods + 1,
150 sizeof(struct scatterlist), GFP_KERNEL);
151 if (!iprtd->sg_list)
152 return -ENOMEM;
153 iprtd->sg_count = iprtd->periods + 1;
154 }
155
156 sg_init_table(iprtd->sg_list, iprtd->sg_count);
157 dma_addr = runtime->dma_addr;
158
159 for (i = 0; i < iprtd->periods; i++) {
160 iprtd->sg_list[i].page_link = 0;
161 iprtd->sg_list[i].offset = 0;
162 iprtd->sg_list[i].dma_address = dma_addr;
163 iprtd->sg_list[i].length = iprtd->period;
164 dma_addr += iprtd->period;
165 }
166
167 /* close the loop */
168 iprtd->sg_list[iprtd->sg_count - 1].offset = 0;
169 iprtd->sg_list[iprtd->sg_count - 1].length = 0;
170 iprtd->sg_list[iprtd->sg_count - 1].page_link =
171 ((unsigned long) iprtd->sg_list | 0x01) & ~0x02;
172 return 0;
173}
174
175static int snd_imx_pcm_hw_free(struct snd_pcm_substream *substream)
176{
177 struct snd_pcm_runtime *runtime = substream->runtime;
178 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
179
180 if (iprtd->dma >= 0) {
181 imx_dma_free(iprtd->dma);
182 iprtd->dma = -EINVAL;
183 }
184
185 kfree(iprtd->sg_list);
186 iprtd->sg_list = NULL;
187
188 return 0;
189}
190
191static int snd_imx_pcm_prepare(struct snd_pcm_substream *substream)
192{
193 struct snd_pcm_runtime *runtime = substream->runtime;
194 struct snd_soc_pcm_runtime *rtd = substream->private_data;
195 struct imx_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
196 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
197 int err;
198
199 iprtd->substream = substream;
200 iprtd->buf = (unsigned int *)substream->dma_buffer.area;
201 iprtd->period_cnt = 0;
202
203 pr_debug("%s: buf: %p period: %d periods: %d\n",
204 __func__, iprtd->buf, iprtd->period, iprtd->periods);
205
206 err = imx_dma_setup_sg(iprtd->dma, iprtd->sg_list, iprtd->sg_count,
207 IMX_DMA_LENGTH_LOOP, dma_params->dma_addr,
208 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
209 DMA_MODE_WRITE : DMA_MODE_READ);
210 if (err)
211 return err;
212
213 return 0;
214}
215
216static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
217{
218 struct snd_pcm_runtime *runtime = substream->runtime;
219 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
220
221 switch (cmd) {
222 case SNDRV_PCM_TRIGGER_START:
223 case SNDRV_PCM_TRIGGER_RESUME:
224 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
225 imx_dma_enable(iprtd->dma);
226
227 break;
228
229 case SNDRV_PCM_TRIGGER_STOP:
230 case SNDRV_PCM_TRIGGER_SUSPEND:
231 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
232 imx_dma_disable(iprtd->dma);
233
234 break;
235 default:
236 return -EINVAL;
237 }
238
239 return 0;
240}
241
242static snd_pcm_uframes_t snd_imx_pcm_pointer(struct snd_pcm_substream *substream)
243{
244 struct snd_pcm_runtime *runtime = substream->runtime;
245 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
246
247 return bytes_to_frames(substream->runtime, iprtd->offset);
248}
249
250static struct snd_pcm_hardware snd_imx_hardware = {
251 .info = SNDRV_PCM_INFO_INTERLEAVED |
252 SNDRV_PCM_INFO_BLOCK_TRANSFER |
253 SNDRV_PCM_INFO_MMAP |
254 SNDRV_PCM_INFO_MMAP_VALID |
255 SNDRV_PCM_INFO_PAUSE |
256 SNDRV_PCM_INFO_RESUME,
257 .formats = SNDRV_PCM_FMTBIT_S16_LE,
258 .rate_min = 8000,
259 .channels_min = 2,
260 .channels_max = 2,
261 .buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
262 .period_bytes_min = 128,
263 .period_bytes_max = 16 * 1024,
264 .periods_min = 2,
265 .periods_max = 255,
266 .fifo_size = 0,
267};
268
269static int snd_imx_open(struct snd_pcm_substream *substream)
270{
271 struct snd_pcm_runtime *runtime = substream->runtime;
272 struct imx_pcm_runtime_data *iprtd;
273 int ret;
274
275 iprtd = kzalloc(sizeof(*iprtd), GFP_KERNEL);
276 runtime->private_data = iprtd;
277
278 ret = snd_pcm_hw_constraint_integer(substream->runtime,
279 SNDRV_PCM_HW_PARAM_PERIODS);
280 if (ret < 0)
281 return ret;
282
283 snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
284 return 0;
285}
286
287static struct snd_pcm_ops imx_pcm_ops = {
288 .open = snd_imx_open,
289 .ioctl = snd_pcm_lib_ioctl,
290 .hw_params = snd_imx_pcm_hw_params,
291 .hw_free = snd_imx_pcm_hw_free,
292 .prepare = snd_imx_pcm_prepare,
293 .trigger = snd_imx_pcm_trigger,
294 .pointer = snd_imx_pcm_pointer,
295 .mmap = snd_imx_pcm_mmap,
296};
297
298static struct snd_soc_platform imx_soc_platform_dma = {
299 .name = "imx-audio",
300 .pcm_ops = &imx_pcm_ops,
301 .pcm_new = imx_pcm_new,
302 .pcm_free = imx_pcm_free,
303};
304
305struct snd_soc_platform *imx_ssi_dma_mx2_init(struct platform_device *pdev,
306 struct imx_ssi *ssi)
307{
308 ssi->dma_params_tx.burstsize = DMA_TXFIFO_BURST;
309 ssi->dma_params_rx.burstsize = DMA_RXFIFO_BURST;
310
311 return &imx_soc_platform_dma;
312}
313
diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/imx/imx-pcm-fiq.c
new file mode 100644
index 000000000000..5532579ece4d
--- /dev/null
+++ b/sound/soc/imx/imx-pcm-fiq.c
@@ -0,0 +1,277 @@
1/*
2 * imx-pcm-fiq.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This code is based on code copyrighted by Freescale,
7 * Liam Girdwood, Javier Martin and probably others.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/dma-mapping.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22
23#include <sound/core.h>
24#include <sound/initval.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28
29#include <asm/fiq.h>
30
31#include <mach/ssi.h>
32
33#include "imx-ssi.h"
34
35struct imx_pcm_runtime_data {
36 int period;
37 int periods;
38 unsigned long dma_addr;
39 int dma;
40 unsigned long offset;
41 unsigned long size;
42 unsigned long period_cnt;
43 void *buf;
44 struct timer_list timer;
45 int period_time;
46};
47
48static void imx_ssi_timer_callback(unsigned long data)
49{
50 struct snd_pcm_substream *substream = (void *)data;
51 struct snd_pcm_runtime *runtime = substream->runtime;
52 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
53 struct pt_regs regs;
54
55 get_fiq_regs(&regs);
56
57 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
58 iprtd->offset = regs.ARM_r8 & 0xffff;
59 else
60 iprtd->offset = regs.ARM_r9 & 0xffff;
61
62 iprtd->timer.expires = jiffies + iprtd->period_time;
63 add_timer(&iprtd->timer);
64 snd_pcm_period_elapsed(substream);
65}
66
67static struct fiq_handler fh = {
68 .name = DRV_NAME,
69};
70
71static int snd_imx_pcm_hw_params(struct snd_pcm_substream *substream,
72 struct snd_pcm_hw_params *params)
73{
74 struct snd_pcm_runtime *runtime = substream->runtime;
75 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
76
77 iprtd->size = params_buffer_bytes(params);
78 iprtd->periods = params_periods(params);
79 iprtd->period = params_period_bytes(params);
80 iprtd->offset = 0;
81 iprtd->period_time = HZ / (params_rate(params) / params_period_size(params));
82
83 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
84
85 return 0;
86}
87
88static int snd_imx_pcm_prepare(struct snd_pcm_substream *substream)
89{
90 struct snd_pcm_runtime *runtime = substream->runtime;
91 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
92 struct pt_regs regs;
93
94 get_fiq_regs(&regs);
95 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
96 regs.ARM_r8 = (iprtd->period * iprtd->periods - 1) << 16;
97 else
98 regs.ARM_r9 = (iprtd->period * iprtd->periods - 1) << 16;
99
100 set_fiq_regs(&regs);
101
102 return 0;
103}
104
105static int fiq_enable;
106static int imx_pcm_fiq;
107
108static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
109{
110 struct snd_pcm_runtime *runtime = substream->runtime;
111 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
112
113 switch (cmd) {
114 case SNDRV_PCM_TRIGGER_START:
115 case SNDRV_PCM_TRIGGER_RESUME:
116 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
117 iprtd->timer.expires = jiffies + iprtd->period_time;
118 add_timer(&iprtd->timer);
119 if (++fiq_enable == 1)
120 enable_fiq(imx_pcm_fiq);
121
122 break;
123
124 case SNDRV_PCM_TRIGGER_STOP:
125 case SNDRV_PCM_TRIGGER_SUSPEND:
126 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
127 del_timer(&iprtd->timer);
128 if (--fiq_enable == 0)
129 disable_fiq(imx_pcm_fiq);
130
131
132 break;
133 default:
134 return -EINVAL;
135 }
136
137 return 0;
138}
139
140static snd_pcm_uframes_t snd_imx_pcm_pointer(struct snd_pcm_substream *substream)
141{
142 struct snd_pcm_runtime *runtime = substream->runtime;
143 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
144
145 return bytes_to_frames(substream->runtime, iprtd->offset);
146}
147
148static struct snd_pcm_hardware snd_imx_hardware = {
149 .info = SNDRV_PCM_INFO_INTERLEAVED |
150 SNDRV_PCM_INFO_BLOCK_TRANSFER |
151 SNDRV_PCM_INFO_MMAP |
152 SNDRV_PCM_INFO_MMAP_VALID |
153 SNDRV_PCM_INFO_PAUSE |
154 SNDRV_PCM_INFO_RESUME,
155 .formats = SNDRV_PCM_FMTBIT_S16_LE,
156 .rate_min = 8000,
157 .channels_min = 2,
158 .channels_max = 2,
159 .buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
160 .period_bytes_min = 128,
161 .period_bytes_max = 16 * 1024,
162 .periods_min = 2,
163 .periods_max = 255,
164 .fifo_size = 0,
165};
166
167static int snd_imx_open(struct snd_pcm_substream *substream)
168{
169 struct snd_pcm_runtime *runtime = substream->runtime;
170 struct imx_pcm_runtime_data *iprtd;
171 int ret;
172
173 iprtd = kzalloc(sizeof(*iprtd), GFP_KERNEL);
174 runtime->private_data = iprtd;
175
176 init_timer(&iprtd->timer);
177 iprtd->timer.data = (unsigned long)substream;
178 iprtd->timer.function = imx_ssi_timer_callback;
179
180 ret = snd_pcm_hw_constraint_integer(substream->runtime,
181 SNDRV_PCM_HW_PARAM_PERIODS);
182 if (ret < 0)
183 return ret;
184
185 snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
186 return 0;
187}
188
189static int snd_imx_close(struct snd_pcm_substream *substream)
190{
191 struct snd_pcm_runtime *runtime = substream->runtime;
192 struct imx_pcm_runtime_data *iprtd = runtime->private_data;
193
194 del_timer_sync(&iprtd->timer);
195 kfree(iprtd);
196
197 return 0;
198}
199
200static struct snd_pcm_ops imx_pcm_ops = {
201 .open = snd_imx_open,
202 .close = snd_imx_close,
203 .ioctl = snd_pcm_lib_ioctl,
204 .hw_params = snd_imx_pcm_hw_params,
205 .prepare = snd_imx_pcm_prepare,
206 .trigger = snd_imx_pcm_trigger,
207 .pointer = snd_imx_pcm_pointer,
208 .mmap = snd_imx_pcm_mmap,
209};
210
211static int imx_pcm_fiq_new(struct snd_card *card, struct snd_soc_dai *dai,
212 struct snd_pcm *pcm)
213{
214 int ret;
215
216 ret = imx_pcm_new(card, dai, pcm);
217 if (ret)
218 return ret;
219
220 if (dai->playback.channels_min) {
221 struct snd_pcm_substream *substream =
222 pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
223 struct snd_dma_buffer *buf = &substream->dma_buffer;
224
225 imx_ssi_fiq_tx_buffer = (unsigned long)buf->area;
226 }
227
228 if (dai->capture.channels_min) {
229 struct snd_pcm_substream *substream =
230 pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
231 struct snd_dma_buffer *buf = &substream->dma_buffer;
232
233 imx_ssi_fiq_rx_buffer = (unsigned long)buf->area;
234 }
235
236 set_fiq_handler(&imx_ssi_fiq_start,
237 &imx_ssi_fiq_end - &imx_ssi_fiq_start);
238
239 return 0;
240}
241
242static struct snd_soc_platform imx_soc_platform_fiq = {
243 .pcm_ops = &imx_pcm_ops,
244 .pcm_new = imx_pcm_fiq_new,
245 .pcm_free = imx_pcm_free,
246};
247
248struct snd_soc_platform *imx_ssi_fiq_init(struct platform_device *pdev,
249 struct imx_ssi *ssi)
250{
251 int ret = 0;
252
253 ret = claim_fiq(&fh);
254 if (ret) {
255 dev_err(&pdev->dev, "failed to claim fiq: %d", ret);
256 return ERR_PTR(ret);
257 }
258
259 mxc_set_irq_fiq(ssi->irq, 1);
260
261 imx_pcm_fiq = ssi->irq;
262
263 imx_ssi_fiq_base = (unsigned long)ssi->base;
264
265 ssi->dma_params_tx.burstsize = 4;
266 ssi->dma_params_rx.burstsize = 6;
267
268 return &imx_soc_platform_fiq;
269}
270
271void imx_ssi_fiq_exit(struct platform_device *pdev,
272 struct imx_ssi *ssi)
273{
274 mxc_set_irq_fiq(ssi->irq, 0);
275 release_fiq(&fh);
276}
277
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c
new file mode 100644
index 000000000000..c57a11f66954
--- /dev/null
+++ b/sound/soc/imx/imx-ssi.c
@@ -0,0 +1,762 @@
1/*
2 * imx-ssi.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This code is based on code copyrighted by Freescale,
7 * Liam Girdwood, Javier Martin and probably others.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 *
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developped with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
25 * rate.
26 * Reading and writing AC97 registers is another challange. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
31 *
32 */
33
34#include <linux/clk.h>
35#include <linux/delay.h>
36#include <linux/device.h>
37#include <linux/dma-mapping.h>
38#include <linux/init.h>
39#include <linux/interrupt.h>
40#include <linux/module.h>
41#include <linux/platform_device.h>
42
43#include <sound/core.h>
44#include <sound/initval.h>
45#include <sound/pcm.h>
46#include <sound/pcm_params.h>
47#include <sound/soc.h>
48
49#include <mach/ssi.h>
50#include <mach/hardware.h>
51
52#include "imx-ssi.h"
53
54#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
55
56/*
57 * SSI Network Mode or TDM slots configuration.
58 * Should only be called when port is inactive (i.e. SSIEN = 0).
59 */
60static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
61 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
62{
63 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
64 u32 sccr;
65
66 sccr = readl(ssi->base + SSI_STCCR);
67 sccr &= ~SSI_STCCR_DC_MASK;
68 sccr |= SSI_STCCR_DC(slots - 1);
69 writel(sccr, ssi->base + SSI_STCCR);
70
71 sccr = readl(ssi->base + SSI_SRCCR);
72 sccr &= ~SSI_STCCR_DC_MASK;
73 sccr |= SSI_STCCR_DC(slots - 1);
74 writel(sccr, ssi->base + SSI_SRCCR);
75
76 writel(tx_mask, ssi->base + SSI_STMSK);
77 writel(rx_mask, ssi->base + SSI_SRMSK);
78
79 return 0;
80}
81
82/*
83 * SSI DAI format configuration.
84 * Should only be called when port is inactive (i.e. SSIEN = 0).
85 * Note: We don't use the I2S modes but instead manually configure the
86 * SSI for I2S because the I2S mode is only a register preset.
87 */
88static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
89{
90 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
91 u32 strcr = 0, scr;
92
93 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
94
95 /* DAI mode */
96 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
97 case SND_SOC_DAIFMT_I2S:
98 /* data on rising edge of bclk, frame low 1clk before data */
99 strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
100 scr |= SSI_SCR_NET;
101 break;
102 case SND_SOC_DAIFMT_LEFT_J:
103 /* data on rising edge of bclk, frame high with data */
104 strcr |= SSI_STCR_TXBIT0;
105 break;
106 case SND_SOC_DAIFMT_DSP_B:
107 /* data on rising edge of bclk, frame high with data */
108 strcr |= SSI_STCR_TFSL;
109 break;
110 case SND_SOC_DAIFMT_DSP_A:
111 /* data on rising edge of bclk, frame high 1clk before data */
112 strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
113 break;
114 }
115
116 /* DAI clock inversion */
117 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
118 case SND_SOC_DAIFMT_IB_IF:
119 strcr |= SSI_STCR_TFSI;
120 strcr &= ~SSI_STCR_TSCKP;
121 break;
122 case SND_SOC_DAIFMT_IB_NF:
123 strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
124 break;
125 case SND_SOC_DAIFMT_NB_IF:
126 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
127 break;
128 case SND_SOC_DAIFMT_NB_NF:
129 strcr &= ~SSI_STCR_TFSI;
130 strcr |= SSI_STCR_TSCKP;
131 break;
132 }
133
134 /* DAI clock master masks */
135 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
136 case SND_SOC_DAIFMT_CBS_CFS:
137 strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
138 break;
139 case SND_SOC_DAIFMT_CBM_CFS:
140 strcr |= SSI_STCR_TFDIR;
141 break;
142 case SND_SOC_DAIFMT_CBS_CFM:
143 strcr |= SSI_STCR_TXDIR;
144 break;
145 }
146
147 strcr |= SSI_STCR_TFEN0;
148
149 writel(strcr, ssi->base + SSI_STCR);
150 writel(strcr, ssi->base + SSI_SRCR);
151 writel(scr, ssi->base + SSI_SCR);
152
153 return 0;
154}
155
156/*
157 * SSI system clock configuration.
158 * Should only be called when port is inactive (i.e. SSIEN = 0).
159 */
160static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
161 int clk_id, unsigned int freq, int dir)
162{
163 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
164 u32 scr;
165
166 scr = readl(ssi->base + SSI_SCR);
167
168 switch (clk_id) {
169 case IMX_SSP_SYS_CLK:
170 if (dir == SND_SOC_CLOCK_OUT)
171 scr |= SSI_SCR_SYS_CLK_EN;
172 else
173 scr &= ~SSI_SCR_SYS_CLK_EN;
174 break;
175 default:
176 return -EINVAL;
177 }
178
179 writel(scr, ssi->base + SSI_SCR);
180
181 return 0;
182}
183
184/*
185 * SSI Clock dividers
186 * Should only be called when port is inactive (i.e. SSIEN = 0).
187 */
188static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
189 int div_id, int div)
190{
191 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
192 u32 stccr, srccr;
193
194 stccr = readl(ssi->base + SSI_STCCR);
195 srccr = readl(ssi->base + SSI_SRCCR);
196
197 switch (div_id) {
198 case IMX_SSI_TX_DIV_2:
199 stccr &= ~SSI_STCCR_DIV2;
200 stccr |= div;
201 break;
202 case IMX_SSI_TX_DIV_PSR:
203 stccr &= ~SSI_STCCR_PSR;
204 stccr |= div;
205 break;
206 case IMX_SSI_TX_DIV_PM:
207 stccr &= ~0xff;
208 stccr |= SSI_STCCR_PM(div);
209 break;
210 case IMX_SSI_RX_DIV_2:
211 stccr &= ~SSI_STCCR_DIV2;
212 stccr |= div;
213 break;
214 case IMX_SSI_RX_DIV_PSR:
215 stccr &= ~SSI_STCCR_PSR;
216 stccr |= div;
217 break;
218 case IMX_SSI_RX_DIV_PM:
219 stccr &= ~0xff;
220 stccr |= SSI_STCCR_PM(div);
221 break;
222 default:
223 return -EINVAL;
224 }
225
226 writel(stccr, ssi->base + SSI_STCCR);
227 writel(srccr, ssi->base + SSI_SRCCR);
228
229 return 0;
230}
231
232/*
233 * Should only be called when port is inactive (i.e. SSIEN = 0),
234 * although can be called multiple times by upper layers.
235 */
236static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
237 struct snd_pcm_hw_params *params,
238 struct snd_soc_dai *cpu_dai)
239{
240 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
241 u32 reg, sccr;
242
243 /* Tx/Rx config */
244 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
245 reg = SSI_STCCR;
246 cpu_dai->dma_data = &ssi->dma_params_tx;
247 } else {
248 reg = SSI_SRCCR;
249 cpu_dai->dma_data = &ssi->dma_params_rx;
250 }
251
252 sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
253
254 /* DAI data (word) size */
255 switch (params_format(params)) {
256 case SNDRV_PCM_FORMAT_S16_LE:
257 sccr |= SSI_SRCCR_WL(16);
258 break;
259 case SNDRV_PCM_FORMAT_S20_3LE:
260 sccr |= SSI_SRCCR_WL(20);
261 break;
262 case SNDRV_PCM_FORMAT_S24_LE:
263 sccr |= SSI_SRCCR_WL(24);
264 break;
265 }
266
267 writel(sccr, ssi->base + reg);
268
269 return 0;
270}
271
272static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
273 struct snd_soc_dai *dai)
274{
275 struct snd_soc_pcm_runtime *rtd = substream->private_data;
276 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
277 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
278 unsigned int sier_bits, sier;
279 unsigned int scr;
280
281 scr = readl(ssi->base + SSI_SCR);
282 sier = readl(ssi->base + SSI_SIER);
283
284 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
285 if (ssi->flags & IMX_SSI_DMA)
286 sier_bits = SSI_SIER_TDMAE;
287 else
288 sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
289 } else {
290 if (ssi->flags & IMX_SSI_DMA)
291 sier_bits = SSI_SIER_RDMAE;
292 else
293 sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
294 }
295
296 switch (cmd) {
297 case SNDRV_PCM_TRIGGER_START:
298 case SNDRV_PCM_TRIGGER_RESUME:
299 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
300 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
301 scr |= SSI_SCR_TE;
302 else
303 scr |= SSI_SCR_RE;
304 sier |= sier_bits;
305
306 if (++ssi->enabled == 1)
307 scr |= SSI_SCR_SSIEN;
308
309 break;
310
311 case SNDRV_PCM_TRIGGER_STOP:
312 case SNDRV_PCM_TRIGGER_SUSPEND:
313 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
314 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
315 scr &= ~SSI_SCR_TE;
316 else
317 scr &= ~SSI_SCR_RE;
318 sier &= ~sier_bits;
319
320 if (--ssi->enabled == 0)
321 scr &= ~SSI_SCR_SSIEN;
322
323 break;
324 default:
325 return -EINVAL;
326 }
327
328 if (!(ssi->flags & IMX_SSI_USE_AC97))
329 /* rx/tx are always enabled to access ac97 registers */
330 writel(scr, ssi->base + SSI_SCR);
331
332 writel(sier, ssi->base + SSI_SIER);
333
334 return 0;
335}
336
337static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
338 .hw_params = imx_ssi_hw_params,
339 .set_fmt = imx_ssi_set_dai_fmt,
340 .set_clkdiv = imx_ssi_set_dai_clkdiv,
341 .set_sysclk = imx_ssi_set_dai_sysclk,
342 .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
343 .trigger = imx_ssi_trigger,
344};
345
346static struct snd_soc_dai imx_ssi_dai = {
347 .playback = {
348 .channels_min = 2,
349 .channels_max = 2,
350 .rates = SNDRV_PCM_RATE_8000_96000,
351 .formats = SNDRV_PCM_FMTBIT_S16_LE,
352 },
353 .capture = {
354 .channels_min = 2,
355 .channels_max = 2,
356 .rates = SNDRV_PCM_RATE_8000_96000,
357 .formats = SNDRV_PCM_FMTBIT_S16_LE,
358 },
359 .ops = &imx_ssi_pcm_dai_ops,
360};
361
362int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
363 struct vm_area_struct *vma)
364{
365 struct snd_pcm_runtime *runtime = substream->runtime;
366 int ret;
367
368 ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
369 runtime->dma_addr, runtime->dma_bytes);
370
371 pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
372 runtime->dma_area,
373 runtime->dma_addr,
374 runtime->dma_bytes);
375 return ret;
376}
377
378static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
379{
380 struct snd_pcm_substream *substream = pcm->streams[stream].substream;
381 struct snd_dma_buffer *buf = &substream->dma_buffer;
382 size_t size = IMX_SSI_DMABUF_SIZE;
383
384 buf->dev.type = SNDRV_DMA_TYPE_DEV;
385 buf->dev.dev = pcm->card->dev;
386 buf->private_data = NULL;
387 buf->area = dma_alloc_writecombine(pcm->card->dev, size,
388 &buf->addr, GFP_KERNEL);
389 if (!buf->area)
390 return -ENOMEM;
391 buf->bytes = size;
392
393 return 0;
394}
395
396static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
397
398int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
399 struct snd_pcm *pcm)
400{
401
402 int ret = 0;
403
404 if (!card->dev->dma_mask)
405 card->dev->dma_mask = &imx_pcm_dmamask;
406 if (!card->dev->coherent_dma_mask)
407 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
408 if (dai->playback.channels_min) {
409 ret = imx_pcm_preallocate_dma_buffer(pcm,
410 SNDRV_PCM_STREAM_PLAYBACK);
411 if (ret)
412 goto out;
413 }
414
415 if (dai->capture.channels_min) {
416 ret = imx_pcm_preallocate_dma_buffer(pcm,
417 SNDRV_PCM_STREAM_CAPTURE);
418 if (ret)
419 goto out;
420 }
421
422out:
423 return ret;
424}
425
426void imx_pcm_free(struct snd_pcm *pcm)
427{
428 struct snd_pcm_substream *substream;
429 struct snd_dma_buffer *buf;
430 int stream;
431
432 for (stream = 0; stream < 2; stream++) {
433 substream = pcm->streams[stream].substream;
434 if (!substream)
435 continue;
436
437 buf = &substream->dma_buffer;
438 if (!buf->area)
439 continue;
440
441 dma_free_writecombine(pcm->card->dev, buf->bytes,
442 buf->area, buf->addr);
443 buf->area = NULL;
444 }
445}
446
447struct snd_soc_platform imx_soc_platform = {
448 .name = "imx-audio",
449};
450EXPORT_SYMBOL_GPL(imx_soc_platform);
451
452static struct snd_soc_dai imx_ac97_dai = {
453 .name = "AC97",
454 .ac97_control = 1,
455 .playback = {
456 .stream_name = "AC97 Playback",
457 .channels_min = 2,
458 .channels_max = 2,
459 .rates = SNDRV_PCM_RATE_48000,
460 .formats = SNDRV_PCM_FMTBIT_S16_LE,
461 },
462 .capture = {
463 .stream_name = "AC97 Capture",
464 .channels_min = 2,
465 .channels_max = 2,
466 .rates = SNDRV_PCM_RATE_48000,
467 .formats = SNDRV_PCM_FMTBIT_S16_LE,
468 },
469 .ops = &imx_ssi_pcm_dai_ops,
470};
471
472static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
473{
474 void __iomem *base = imx_ssi->base;
475
476 writel(0x0, base + SSI_SCR);
477 writel(0x0, base + SSI_STCR);
478 writel(0x0, base + SSI_SRCR);
479
480 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
481
482 writel(SSI_SFCSR_RFWM0(8) |
483 SSI_SFCSR_TFWM0(8) |
484 SSI_SFCSR_RFWM1(8) |
485 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
486
487 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
488 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
489
490 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
491 writel(SSI_SOR_WAIT(3), base + SSI_SOR);
492
493 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
494 SSI_SCR_TE | SSI_SCR_RE,
495 base + SSI_SCR);
496
497 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
498 writel(0xff, base + SSI_SACCDIS);
499 writel(0x300, base + SSI_SACCEN);
500}
501
502static struct imx_ssi *ac97_ssi;
503
504static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
505 unsigned short val)
506{
507 struct imx_ssi *imx_ssi = ac97_ssi;
508 void __iomem *base = imx_ssi->base;
509 unsigned int lreg;
510 unsigned int lval;
511
512 if (reg > 0x7f)
513 return;
514
515 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
516
517 lreg = reg << 12;
518 writel(lreg, base + SSI_SACADD);
519
520 lval = val << 4;
521 writel(lval , base + SSI_SACDAT);
522
523 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
524 udelay(100);
525}
526
527static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
528 unsigned short reg)
529{
530 struct imx_ssi *imx_ssi = ac97_ssi;
531 void __iomem *base = imx_ssi->base;
532
533 unsigned short val = -1;
534 unsigned int lreg;
535
536 lreg = (reg & 0x7f) << 12 ;
537 writel(lreg, base + SSI_SACADD);
538 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
539
540 udelay(100);
541
542 val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
543
544 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
545
546 return val;
547}
548
549static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
550{
551 struct imx_ssi *imx_ssi = ac97_ssi;
552
553 if (imx_ssi->ac97_reset)
554 imx_ssi->ac97_reset(ac97);
555}
556
557static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
558{
559 struct imx_ssi *imx_ssi = ac97_ssi;
560
561 if (imx_ssi->ac97_warm_reset)
562 imx_ssi->ac97_warm_reset(ac97);
563}
564
565struct snd_ac97_bus_ops soc_ac97_ops = {
566 .read = imx_ssi_ac97_read,
567 .write = imx_ssi_ac97_write,
568 .reset = imx_ssi_ac97_reset,
569 .warm_reset = imx_ssi_ac97_warm_reset
570};
571EXPORT_SYMBOL_GPL(soc_ac97_ops);
572
573struct snd_soc_dai *imx_ssi_pcm_dai[2];
574EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai);
575
576static int imx_ssi_probe(struct platform_device *pdev)
577{
578 struct resource *res;
579 struct imx_ssi *ssi;
580 struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
581 struct snd_soc_platform *platform;
582 int ret = 0;
583 unsigned int val;
584
585 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
586 if (!ssi)
587 return -ENOMEM;
588
589 if (pdata) {
590 ssi->ac97_reset = pdata->ac97_reset;
591 ssi->ac97_warm_reset = pdata->ac97_warm_reset;
592 ssi->flags = pdata->flags;
593 }
594
595 imx_ssi_pcm_dai[pdev->id] = &ssi->dai;
596
597 ssi->irq = platform_get_irq(pdev, 0);
598
599 ssi->clk = clk_get(&pdev->dev, NULL);
600 if (IS_ERR(ssi->clk)) {
601 ret = PTR_ERR(ssi->clk);
602 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
603 ret);
604 goto failed_clk;
605 }
606 clk_enable(ssi->clk);
607
608 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
609 if (!res) {
610 ret = -ENODEV;
611 goto failed_get_resource;
612 }
613
614 if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
615 dev_err(&pdev->dev, "request_mem_region failed\n");
616 ret = -EBUSY;
617 goto failed_get_resource;
618 }
619
620 ssi->base = ioremap(res->start, resource_size(res));
621 if (!ssi->base) {
622 dev_err(&pdev->dev, "ioremap failed\n");
623 ret = -ENODEV;
624 goto failed_ioremap;
625 }
626
627 if (ssi->flags & IMX_SSI_USE_AC97) {
628 if (ac97_ssi) {
629 ret = -EBUSY;
630 goto failed_ac97;
631 }
632 ac97_ssi = ssi;
633 setup_channel_to_ac97(ssi);
634 memcpy(&ssi->dai, &imx_ac97_dai, sizeof(imx_ac97_dai));
635 } else
636 memcpy(&ssi->dai, &imx_ssi_dai, sizeof(imx_ssi_dai));
637
638 ssi->dai.id = pdev->id;
639 ssi->dai.dev = &pdev->dev;
640 ssi->dai.name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
641
642 writel(0x0, ssi->base + SSI_SIER);
643
644 ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
645 ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
646
647 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
648 if (res)
649 ssi->dma_params_tx.dma = res->start;
650
651 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
652 if (res)
653 ssi->dma_params_rx.dma = res->start;
654
655 ssi->dai.id = pdev->id;
656 ssi->dai.dev = &pdev->dev;
657 ssi->dai.name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
658
659 if ((cpu_is_mx27() || cpu_is_mx21()) &&
660 !(ssi->flags & IMX_SSI_USE_AC97)) {
661 ssi->flags |= IMX_SSI_DMA;
662 platform = imx_ssi_dma_mx2_init(pdev, ssi);
663 } else
664 platform = imx_ssi_fiq_init(pdev, ssi);
665
666 imx_soc_platform.pcm_ops = platform->pcm_ops;
667 imx_soc_platform.pcm_new = platform->pcm_new;
668 imx_soc_platform.pcm_free = platform->pcm_free;
669
670 val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
671 SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
672 writel(val, ssi->base + SSI_SFCSR);
673
674 ret = snd_soc_register_dai(&ssi->dai);
675 if (ret) {
676 dev_err(&pdev->dev, "register DAI failed\n");
677 goto failed_register;
678 }
679
680 platform_set_drvdata(pdev, ssi);
681
682 return 0;
683
684failed_register:
685failed_ac97:
686 iounmap(ssi->base);
687failed_ioremap:
688 release_mem_region(res->start, resource_size(res));
689failed_get_resource:
690 clk_disable(ssi->clk);
691 clk_put(ssi->clk);
692failed_clk:
693 kfree(ssi);
694
695 return ret;
696}
697
698static int __devexit imx_ssi_remove(struct platform_device *pdev)
699{
700 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
701 struct imx_ssi *ssi = platform_get_drvdata(pdev);
702
703 snd_soc_unregister_dai(&ssi->dai);
704
705 if (ssi->flags & IMX_SSI_USE_AC97)
706 ac97_ssi = NULL;
707
708 if (!(ssi->flags & IMX_SSI_DMA))
709 imx_ssi_fiq_exit(pdev, ssi);
710
711 iounmap(ssi->base);
712 release_mem_region(res->start, resource_size(res));
713 clk_disable(ssi->clk);
714 clk_put(ssi->clk);
715 kfree(ssi);
716
717 return 0;
718}
719
720static struct platform_driver imx_ssi_driver = {
721 .probe = imx_ssi_probe,
722 .remove = __devexit_p(imx_ssi_remove),
723
724 .driver = {
725 .name = DRV_NAME,
726 .owner = THIS_MODULE,
727 },
728};
729
730static int __init imx_ssi_init(void)
731{
732 int ret;
733
734 ret = snd_soc_register_platform(&imx_soc_platform);
735 if (ret) {
736 pr_err("failed to register soc platform: %d\n", ret);
737 return ret;
738 }
739
740 ret = platform_driver_register(&imx_ssi_driver);
741 if (ret) {
742 snd_soc_unregister_platform(&imx_soc_platform);
743 return ret;
744 }
745
746 return 0;
747}
748
749static void __exit imx_ssi_exit(void)
750{
751 platform_driver_unregister(&imx_ssi_driver);
752 snd_soc_unregister_platform(&imx_soc_platform);
753}
754
755module_init(imx_ssi_init);
756module_exit(imx_ssi_exit);
757
758/* Module information */
759MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
760MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
761MODULE_LICENSE("GPL");
762
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/imx/imx-ssi.h
new file mode 100644
index 000000000000..cb2c81f1a6fc
--- /dev/null
+++ b/sound/soc/imx/imx-ssi.h
@@ -0,0 +1,238 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6
7#ifndef _IMX_SSI_H
8#define _IMX_SSI_H
9
10#define SSI_STX0 0x00
11#define SSI_STX1 0x04
12#define SSI_SRX0 0x08
13#define SSI_SRX1 0x0c
14
15#define SSI_SCR 0x10
16#define SSI_SCR_CLK_IST (1 << 9)
17#define SSI_SCR_CLK_IST_SHIFT 9
18#define SSI_SCR_TCH_EN (1 << 8)
19#define SSI_SCR_SYS_CLK_EN (1 << 7)
20#define SSI_SCR_I2S_MODE_NORM (0 << 5)
21#define SSI_SCR_I2S_MODE_MSTR (1 << 5)
22#define SSI_SCR_I2S_MODE_SLAVE (2 << 5)
23#define SSI_I2S_MODE_MASK (3 << 5)
24#define SSI_SCR_SYN (1 << 4)
25#define SSI_SCR_NET (1 << 3)
26#define SSI_SCR_RE (1 << 2)
27#define SSI_SCR_TE (1 << 1)
28#define SSI_SCR_SSIEN (1 << 0)
29
30#define SSI_SISR 0x14
31#define SSI_SISR_MASK ((1 << 19) - 1)
32#define SSI_SISR_CMDAU (1 << 18)
33#define SSI_SISR_CMDDU (1 << 17)
34#define SSI_SISR_RXT (1 << 16)
35#define SSI_SISR_RDR1 (1 << 15)
36#define SSI_SISR_RDR0 (1 << 14)
37#define SSI_SISR_TDE1 (1 << 13)
38#define SSI_SISR_TDE0 (1 << 12)
39#define SSI_SISR_ROE1 (1 << 11)
40#define SSI_SISR_ROE0 (1 << 10)
41#define SSI_SISR_TUE1 (1 << 9)
42#define SSI_SISR_TUE0 (1 << 8)
43#define SSI_SISR_TFS (1 << 7)
44#define SSI_SISR_RFS (1 << 6)
45#define SSI_SISR_TLS (1 << 5)
46#define SSI_SISR_RLS (1 << 4)
47#define SSI_SISR_RFF1 (1 << 3)
48#define SSI_SISR_RFF0 (1 << 2)
49#define SSI_SISR_TFE1 (1 << 1)
50#define SSI_SISR_TFE0 (1 << 0)
51
52#define SSI_SIER 0x18
53#define SSI_SIER_RDMAE (1 << 22)
54#define SSI_SIER_RIE (1 << 21)
55#define SSI_SIER_TDMAE (1 << 20)
56#define SSI_SIER_TIE (1 << 19)
57#define SSI_SIER_CMDAU_EN (1 << 18)
58#define SSI_SIER_CMDDU_EN (1 << 17)
59#define SSI_SIER_RXT_EN (1 << 16)
60#define SSI_SIER_RDR1_EN (1 << 15)
61#define SSI_SIER_RDR0_EN (1 << 14)
62#define SSI_SIER_TDE1_EN (1 << 13)
63#define SSI_SIER_TDE0_EN (1 << 12)
64#define SSI_SIER_ROE1_EN (1 << 11)
65#define SSI_SIER_ROE0_EN (1 << 10)
66#define SSI_SIER_TUE1_EN (1 << 9)
67#define SSI_SIER_TUE0_EN (1 << 8)
68#define SSI_SIER_TFS_EN (1 << 7)
69#define SSI_SIER_RFS_EN (1 << 6)
70#define SSI_SIER_TLS_EN (1 << 5)
71#define SSI_SIER_RLS_EN (1 << 4)
72#define SSI_SIER_RFF1_EN (1 << 3)
73#define SSI_SIER_RFF0_EN (1 << 2)
74#define SSI_SIER_TFE1_EN (1 << 1)
75#define SSI_SIER_TFE0_EN (1 << 0)
76
77#define SSI_STCR 0x1c
78#define SSI_STCR_TXBIT0 (1 << 9)
79#define SSI_STCR_TFEN1 (1 << 8)
80#define SSI_STCR_TFEN0 (1 << 7)
81#define SSI_FIFO_ENABLE_0_SHIFT 7
82#define SSI_STCR_TFDIR (1 << 6)
83#define SSI_STCR_TXDIR (1 << 5)
84#define SSI_STCR_TSHFD (1 << 4)
85#define SSI_STCR_TSCKP (1 << 3)
86#define SSI_STCR_TFSI (1 << 2)
87#define SSI_STCR_TFSL (1 << 1)
88#define SSI_STCR_TEFS (1 << 0)
89
90#define SSI_SRCR 0x20
91#define SSI_SRCR_RXBIT0 (1 << 9)
92#define SSI_SRCR_RFEN1 (1 << 8)
93#define SSI_SRCR_RFEN0 (1 << 7)
94#define SSI_FIFO_ENABLE_0_SHIFT 7
95#define SSI_SRCR_RFDIR (1 << 6)
96#define SSI_SRCR_RXDIR (1 << 5)
97#define SSI_SRCR_RSHFD (1 << 4)
98#define SSI_SRCR_RSCKP (1 << 3)
99#define SSI_SRCR_RFSI (1 << 2)
100#define SSI_SRCR_RFSL (1 << 1)
101#define SSI_SRCR_REFS (1 << 0)
102
103#define SSI_SRCCR 0x28
104#define SSI_SRCCR_DIV2 (1 << 18)
105#define SSI_SRCCR_PSR (1 << 17)
106#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13)
107#define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8)
108#define SSI_SRCCR_PM(x) (((x) & 0xff) << 0)
109#define SSI_SRCCR_WL_MASK (0xf << 13)
110#define SSI_SRCCR_DC_MASK (0x1f << 8)
111#define SSI_SRCCR_PM_MASK (0xff << 0)
112
113#define SSI_STCCR 0x24
114#define SSI_STCCR_DIV2 (1 << 18)
115#define SSI_STCCR_PSR (1 << 17)
116#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13)
117#define SSI_STCCR_DC(x) (((x) & 0x1f) << 8)
118#define SSI_STCCR_PM(x) (((x) & 0xff) << 0)
119#define SSI_STCCR_WL_MASK (0xf << 13)
120#define SSI_STCCR_DC_MASK (0x1f << 8)
121#define SSI_STCCR_PM_MASK (0xff << 0)
122
123#define SSI_SFCSR 0x2c
124#define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28)
125#define SSI_RX_FIFO_1_COUNT_SHIFT 28
126#define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24)
127#define SSI_TX_FIFO_1_COUNT_SHIFT 24
128#define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20)
129#define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16)
130#define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12)
131#define SSI_RX_FIFO_0_COUNT_SHIFT 12
132#define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8)
133#define SSI_TX_FIFO_0_COUNT_SHIFT 8
134#define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4)
135#define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0)
136#define SSI_SFCSR_RFWM0_MASK (0xf << 4)
137#define SSI_SFCSR_TFWM0_MASK (0xf << 0)
138
139#define SSI_STR 0x30
140#define SSI_STR_TEST (1 << 15)
141#define SSI_STR_RCK2TCK (1 << 14)
142#define SSI_STR_RFS2TFS (1 << 13)
143#define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8)
144#define SSI_STR_TXD2RXD (1 << 7)
145#define SSI_STR_TCK2RCK (1 << 6)
146#define SSI_STR_TFS2RFS (1 << 5)
147#define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0)
148
149#define SSI_SOR 0x34
150#define SSI_SOR_CLKOFF (1 << 6)
151#define SSI_SOR_RX_CLR (1 << 5)
152#define SSI_SOR_TX_CLR (1 << 4)
153#define SSI_SOR_INIT (1 << 3)
154#define SSI_SOR_WAIT(x) (((x) & 0x3) << 1)
155#define SSI_SOR_WAIT_MASK (0x3 << 1)
156#define SSI_SOR_SYNRST (1 << 0)
157
158#define SSI_SACNT 0x38
159#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
160#define SSI_SACNT_WR (1 << 4)
161#define SSI_SACNT_RD (1 << 3)
162#define SSI_SACNT_TIF (1 << 2)
163#define SSI_SACNT_FV (1 << 1)
164#define SSI_SACNT_AC97EN (1 << 0)
165
166#define SSI_SACADD 0x3c
167#define SSI_SACDAT 0x40
168#define SSI_SATAG 0x44
169#define SSI_STMSK 0x48
170#define SSI_SRMSK 0x4c
171#define SSI_SACCST 0x50
172#define SSI_SACCEN 0x54
173#define SSI_SACCDIS 0x58
174
175/* SSI clock sources */
176#define IMX_SSP_SYS_CLK 0
177
178/* SSI audio dividers */
179#define IMX_SSI_TX_DIV_2 0
180#define IMX_SSI_TX_DIV_PSR 1
181#define IMX_SSI_TX_DIV_PM 2
182#define IMX_SSI_RX_DIV_2 3
183#define IMX_SSI_RX_DIV_PSR 4
184#define IMX_SSI_RX_DIV_PM 5
185
186extern struct snd_soc_dai *imx_ssi_pcm_dai[2];
187extern struct snd_soc_platform imx_soc_platform;
188
189#define DRV_NAME "imx-ssi"
190
191struct imx_pcm_dma_params {
192 int dma;
193 unsigned long dma_addr;
194 int burstsize;
195};
196
197struct imx_ssi {
198 struct snd_soc_dai dai;
199 struct platform_device *ac97_dev;
200
201 struct snd_soc_device imx_ac97;
202 struct clk *clk;
203 void __iomem *base;
204 int irq;
205 int fiq_enable;
206 unsigned int offset;
207
208 unsigned int flags;
209
210 void (*ac97_reset) (struct snd_ac97 *ac97);
211 void (*ac97_warm_reset)(struct snd_ac97 *ac97);
212
213 struct imx_pcm_dma_params dma_params_rx;
214 struct imx_pcm_dma_params dma_params_tx;
215
216 int enabled;
217};
218
219struct snd_soc_platform *imx_ssi_fiq_init(struct platform_device *pdev,
220 struct imx_ssi *ssi);
221void imx_ssi_fiq_exit(struct platform_device *pdev, struct imx_ssi *ssi);
222struct snd_soc_platform *imx_ssi_dma_mx2_init(struct platform_device *pdev,
223 struct imx_ssi *ssi);
224
225int snd_imx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma);
226int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
227 struct snd_pcm *pcm);
228void imx_pcm_free(struct snd_pcm *pcm);
229
230/*
231 * Do not change this as the FIQ handler depends on this size
232 */
233#define IMX_SSI_DMABUF_SIZE (64 * 1024)
234
235#define DMA_RXFIFO_BURST 0x4
236#define DMA_TXFIFO_BURST 0x6
237
238#endif /* _IMX_SSI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 01:59:06 -0500