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authorRemy Bruno <remy.bruno@trinnov.com>2007-03-07 13:08:46 -0500
committerJaroslav Kysela <perex@suse.cz>2007-05-11 10:55:45 -0400
commitffb2c3c07f6ffd61923de736139248b31dc6f642 (patch)
tree9b2ec46341db8090916407a552c95956ca07ef53 /sound
parent59ae9d05918aca6790fece86b6b3f7daef66d6a8 (diff)
[ALSA] hdspm - Support for Master mode of AES32 and recent MADI
The current MADI driver was found not to completely work, at least on recent MADI cards (rev 204), in particular at 96kHz. This patch solves this: * Add support of DDS feature * Channel map fixed * Channel/rate rules fixed * DMA allocation fixed (need to alloc for all channels and not only for the used ones) Full support for AES32 master mode was added: * Add support of DDS feature * Channel map fixed * Channel/rate rules fixed Signed-off-by: Remy Bruno <remy.bruno@trinnov.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
Diffstat (limited to 'sound')
-rw-r--r--sound/pci/rme9652/hdspm.c177
1 files changed, 115 insertions, 62 deletions
diff --git a/sound/pci/rme9652/hdspm.c b/sound/pci/rme9652/hdspm.c
index d2ae6380943e..143185e7e4dc 100644
--- a/sound/pci/rme9652/hdspm.c
+++ b/sound/pci/rme9652/hdspm.c
@@ -91,8 +91,10 @@ MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
91#define HDSPM_controlRegister 64 91#define HDSPM_controlRegister 64
92#define HDSPM_interruptConfirmation 96 92#define HDSPM_interruptConfirmation 96
93#define HDSPM_control2Reg 256 /* not in specs ???????? */ 93#define HDSPM_control2Reg 256 /* not in specs ???????? */
94#define HDSPM_freqReg 256 /* for AES32 */
94#define HDSPM_midiDataOut0 352 /* just believe in old code */ 95#define HDSPM_midiDataOut0 352 /* just believe in old code */
95#define HDSPM_midiDataOut1 356 96#define HDSPM_midiDataOut1 356
97#define HDSPM_eeprom_wr 384 /* for AES32 */
96 98
97/* DMA enable for 64 channels, only Bit 0 is relevant */ 99/* DMA enable for 64 channels, only Bit 0 is relevant */
98#define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 100#define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
@@ -389,9 +391,8 @@ MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
389 size is the same regardless of the number of channels, and 391 size is the same regardless of the number of channels, and
390 also the latency to use. 392 also the latency to use.
391 for one direction !!! 393 for one direction !!!
392 => need to mupltiply by 2!!
393*/ 394*/
394#define HDSPM_DMA_AREA_BYTES (2 * HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 395#define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
395#define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 396#define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
396 397
397/* revisions >= 230 indicate AES32 card */ 398/* revisions >= 230 indicate AES32 card */
@@ -484,28 +485,6 @@ static char channel_map_madi_ss[HDSPM_MAX_CHANNELS] = {
484 56, 57, 58, 59, 60, 61, 62, 63 485 56, 57, 58, 59, 60, 61, 62, 63
485}; 486};
486 487
487static char channel_map_madi_ds[HDSPM_MAX_CHANNELS] = {
488 0, 2, 4, 6, 8, 10, 12, 14,
489 16, 18, 20, 22, 24, 26, 28, 30,
490 32, 34, 36, 38, 40, 42, 44, 46,
491 48, 50, 52, 54, 56, 58, 60, 62,
492 -1, -1, -1, -1, -1, -1, -1, -1,
493 -1, -1, -1, -1, -1, -1, -1, -1,
494 -1, -1, -1, -1, -1, -1, -1, -1,
495 -1, -1, -1, -1, -1, -1, -1, -1
496};
497
498static char channel_map_madi_qs[HDSPM_MAX_CHANNELS] = {
499 0, 4, 8, 12, 16, 20, 24, 28,
500 32, 36, 40, 44, 48, 52, 56, 60
501 -1, -1, -1, -1, -1, -1, -1, -1,
502 -1, -1, -1, -1, -1, -1, -1, -1,
503 -1, -1, -1, -1, -1, -1, -1, -1,
504 -1, -1, -1, -1, -1, -1, -1, -1,
505 -1, -1, -1, -1, -1, -1, -1, -1,
506 -1, -1, -1, -1, -1, -1, -1, -1
507};
508
509 488
510static struct pci_device_id snd_hdspm_ids[] __devinitdata = { 489static struct pci_device_id snd_hdspm_ids[] __devinitdata = {
511 { 490 {
@@ -818,6 +797,27 @@ static int hdspm_set_interrupt_interval(struct hdspm * s, unsigned int frames)
818 return 0; 797 return 0;
819} 798}
820 799
800static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
801{
802 u64 n;
803 u32 r;
804
805 if (rate >= 112000)
806 rate /= 4;
807 else if (rate >= 56000)
808 rate /= 2;
809
810 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
811// return 104857600000000 / rate; // 100 MHz
812 return 110100480000000 / rate; // 105 MHz
813 */
814 //n = 104857600000000ULL; /* = 2^20 * 10^8 */
815 n = 110100480000000ULL; /* Value checked for AES32 and MADI */
816 div64_32(&n, rate, &r);
817 /* n should be less than 2^32 for being written to FREQ register */
818 snd_assert((n >> 32) == 0);
819 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
820}
821 821
822/* dummy set rate lets see what happens */ 822/* dummy set rate lets see what happens */
823static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 823static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
@@ -943,12 +943,16 @@ static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
943 hdspm->control_register |= rate_bits; 943 hdspm->control_register |= rate_bits;
944 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 944 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
945 945
946 if (rate > 96000 /* 64000*/) 946 /* For AES32, need to set DDS value in FREQ register
947 hdspm->channel_map = channel_map_madi_qs; 947 For MADI, also apparently */
948 else if (rate > 48000) 948 hdspm_set_dds_value(hdspm, rate);
949 hdspm->channel_map = channel_map_madi_ds; 949
950 else 950 if (hdspm->is_aes32 && rate != current_rate)
951 hdspm->channel_map = channel_map_madi_ss; 951 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
952
953 /* For AES32 and for MADI (at least rev 204), channel_map needs to
954 * always be channel_map_madi_ss, whatever the sample rate */
955 hdspm->channel_map = channel_map_madi_ss;
952 956
953 hdspm->system_sample_rate = rate; 957 hdspm->system_sample_rate = rate;
954 958
@@ -3184,8 +3188,8 @@ snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
3184 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 3188 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
3185 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 3189 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
3186 snd_iprintf(buffer, 3190 snd_iprintf(buffer,
3187 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, status2=0x%x, timecode=0x%x\n", 3191 "Register: ctrl1=0x%x, status1=0x%x, status2=0x%x, timecode=0x%x\n",
3188 hdspm->control_register, hdspm->control2_register, 3192 hdspm->control_register,
3189 status, status2, timecode); 3193 status, status2, timecode);
3190 3194
3191 snd_iprintf(buffer, "--- Settings ---\n"); 3195 snd_iprintf(buffer, "--- Settings ---\n");
@@ -3377,13 +3381,16 @@ static int snd_hdspm_set_defaults(struct hdspm * hdspm)
3377 3381
3378 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3382 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3379 3383
3384 if (!hdspm->is_aes32) {
3385 /* No control2 register for AES32 */
3380#ifdef SNDRV_BIG_ENDIAN 3386#ifdef SNDRV_BIG_ENDIAN
3381 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 3387 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
3382#else 3388#else
3383 hdspm->control2_register = 0; 3389 hdspm->control2_register = 0;
3384#endif 3390#endif
3385 3391
3386 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 3392 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
3393 }
3387 hdspm_compute_period_size(hdspm); 3394 hdspm_compute_period_size(hdspm);
3388 3395
3389 /* silence everything */ 3396 /* silence everything */
@@ -3656,11 +3663,10 @@ static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
3656 3663
3657 /* Memory allocation, takashi's method, dont know if we should spinlock */ 3664 /* Memory allocation, takashi's method, dont know if we should spinlock */
3658 /* malloc all buffer even if not enabled to get sure */ 3665 /* malloc all buffer even if not enabled to get sure */
3659 /* malloc only needed bytes */ 3666 /* Update for MADI rev 204: we need to allocate for all channels,
3667 * otherwise it doesn't work at 96kHz */
3660 err = 3668 err =
3661 snd_pcm_lib_malloc_pages(substream, 3669 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
3662 HDSPM_CHANNEL_BUFFER_BYTES *
3663 params_channels(params));
3664 if (err < 0) 3670 if (err < 0)
3665 return err; 3671 return err;
3666 3672
@@ -3696,6 +3702,13 @@ static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
3696 "playback" : "capture", 3702 "playback" : "capture",
3697 snd_pcm_sgbuf_get_addr(sgbuf, 0)); 3703 snd_pcm_sgbuf_get_addr(sgbuf, 0));
3698 */ 3704 */
3705 /*
3706 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
3707 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
3708 "playback" : "capture",
3709 params_rate(params), params_channels(params),
3710 params_buffer_size(params));
3711 */
3699 return 0; 3712 return 0;
3700} 3713}
3701 3714
@@ -3900,16 +3913,16 @@ static int snd_hdspm_hw_rule_channels_rate(struct snd_pcm_hw_params *params,
3900 struct snd_interval *r = 3913 struct snd_interval *r =
3901 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 3914 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
3902 3915
3903 if (r->min > 48000) { 3916 if (r->min > 48000 && r->max <= 96000) {
3904 struct snd_interval t = { 3917 struct snd_interval t = {
3905 .min = 1, 3918 .min = hdspm->ds_channels,
3906 .max = hdspm->ds_channels, 3919 .max = hdspm->ds_channels,
3907 .integer = 1, 3920 .integer = 1,
3908 }; 3921 };
3909 return snd_interval_refine(c, &t); 3922 return snd_interval_refine(c, &t);
3910 } else if (r->max < 64000) { 3923 } else if (r->max < 64000) {
3911 struct snd_interval t = { 3924 struct snd_interval t = {
3912 .min = 1, 3925 .min = hdspm->ss_channels,
3913 .max = hdspm->ss_channels, 3926 .max = hdspm->ss_channels,
3914 .integer = 1, 3927 .integer = 1,
3915 }; 3928 };
@@ -3927,14 +3940,14 @@ static int snd_hdspm_hw_rule_rate_channels(struct snd_pcm_hw_params *params,
3927 struct snd_interval *r = 3940 struct snd_interval *r =
3928 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 3941 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
3929 3942
3930 if (c->min <= hdspm->ss_channels) { 3943 if (c->min >= hdspm->ss_channels) {
3931 struct snd_interval t = { 3944 struct snd_interval t = {
3932 .min = 32000, 3945 .min = 32000,
3933 .max = 48000, 3946 .max = 48000,
3934 .integer = 1, 3947 .integer = 1,
3935 }; 3948 };
3936 return snd_interval_refine(r, &t); 3949 return snd_interval_refine(r, &t);
3937 } else if (c->max > hdspm->ss_channels) { 3950 } else if (c->max <= hdspm->ds_channels) {
3938 struct snd_interval t = { 3951 struct snd_interval t = {
3939 .min = 64000, 3952 .min = 64000,
3940 .max = 96000, 3953 .max = 96000,
@@ -3946,13 +3959,39 @@ static int snd_hdspm_hw_rule_rate_channels(struct snd_pcm_hw_params *params,
3946 return 0; 3959 return 0;
3947} 3960}
3948 3961
3962static int snd_hdspm_hw_rule_channels(struct snd_pcm_hw_params *params,
3963 struct snd_pcm_hw_rule *rule)
3964{
3965 unsigned int list[3];
3966 struct hdspm *hdspm = rule->private;
3967 struct snd_interval *c = hw_param_interval(params,
3968 SNDRV_PCM_HW_PARAM_CHANNELS);
3969 if (hdspm->is_aes32) {
3970 list[0] = hdspm->qs_channels;
3971 list[1] = hdspm->ds_channels;
3972 list[2] = hdspm->ss_channels;
3973 return snd_interval_list(c, 3, list, 0);
3974 } else {
3975 list[0] = hdspm->ds_channels;
3976 list[1] = hdspm->ss_channels;
3977 return snd_interval_list(c, 2, list, 0);
3978 }
3979}
3980
3981
3982static unsigned int hdspm_aes32_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
3983
3984static struct snd_pcm_hw_constraint_list hdspm_hw_constraints_aes32_sample_rates = {
3985 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
3986 .list = hdspm_aes32_sample_rates,
3987 .mask = 0
3988};
3989
3949static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 3990static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
3950{ 3991{
3951 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 3992 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3952 struct snd_pcm_runtime *runtime = substream->runtime; 3993 struct snd_pcm_runtime *runtime = substream->runtime;
3953 3994
3954 snd_printdd("Open device substream %d\n", substream->stream);
3955
3956 spin_lock_irq(&hdspm->lock); 3995 spin_lock_irq(&hdspm->lock);
3957 3996
3958 snd_pcm_set_sync(substream); 3997 snd_pcm_set_sync(substream);
@@ -3973,14 +4012,21 @@ static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
3973 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 4012 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
3974 &hw_constraints_period_sizes); 4013 &hw_constraints_period_sizes);
3975 4014
3976 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4015 if (hdspm->is_aes32) {
3977 snd_hdspm_hw_rule_channels_rate, hdspm, 4016 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
3978 SNDRV_PCM_HW_PARAM_RATE, -1); 4017 &hdspm_hw_constraints_aes32_sample_rates);
3979 4018 } else {
3980 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4019 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
3981 snd_hdspm_hw_rule_rate_channels, hdspm, 4020 snd_hdspm_hw_rule_channels, hdspm,
3982 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4021 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
3983 4022 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4023 snd_hdspm_hw_rule_channels_rate, hdspm,
4024 SNDRV_PCM_HW_PARAM_RATE, -1);
4025
4026 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4027 snd_hdspm_hw_rule_rate_channels, hdspm,
4028 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4029 }
3984 return 0; 4030 return 0;
3985} 4031}
3986 4032
@@ -4020,14 +4066,21 @@ static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
4020 snd_pcm_hw_constraint_list(runtime, 0, 4066 snd_pcm_hw_constraint_list(runtime, 0,
4021 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 4067 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
4022 &hw_constraints_period_sizes); 4068 &hw_constraints_period_sizes);
4023 4069 if (hdspm->is_aes32) {
4024 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4070 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4025 snd_hdspm_hw_rule_channels_rate, hdspm, 4071 &hdspm_hw_constraints_aes32_sample_rates);
4026 SNDRV_PCM_HW_PARAM_RATE, -1); 4072 } else {
4027 4073 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4028 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4074 snd_hdspm_hw_rule_channels, hdspm,
4029 snd_hdspm_hw_rule_rate_channels, hdspm, 4075 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4030 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4076 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4077 snd_hdspm_hw_rule_channels_rate, hdspm,
4078 SNDRV_PCM_HW_PARAM_RATE, -1);
4079
4080 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4081 snd_hdspm_hw_rule_rate_channels, hdspm,
4082 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4083 }
4031 return 0; 4084 return 0;
4032} 4085}
4033 4086