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authorTakashi Iwai <tiwai@suse.de>2012-06-18 02:36:00 -0400
committerTakashi Iwai <tiwai@suse.de>2012-06-18 02:36:00 -0400
commitef890ae9b34cd99411bc72829944c74d2223ef70 (patch)
tree414850284836df5a7180b43618df279653f9c294 /sound
parent2e8b2b29d1f904353c3e54b342ccb8c66390dab8 (diff)
parent3419ae781f1592b3d367107db6500090495490cd (diff)
Merge tag 'asoc-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ASoC: Updates for 3.5 All driver specific and fairly small. The pxa-ssp changes are larger than I'd like but they're build failures and are pretty clear to inspection.
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/codecs/wm8904.c26
-rw-r--r--sound/soc/codecs/wm8996.c8
-rw-r--r--sound/soc/pxa/pxa-ssp.c38
-rw-r--r--sound/soc/tegra/tegra_wm8903.c13
4 files changed, 39 insertions, 46 deletions
diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c
index 65d525d74c54..812acd83fb48 100644
--- a/sound/soc/codecs/wm8904.c
+++ b/sound/soc/codecs/wm8904.c
@@ -1863,6 +1863,7 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec,
1863 return ret; 1863 return ret;
1864 } 1864 }
1865 1865
1866 regcache_cache_only(wm8904->regmap, false);
1866 regcache_sync(wm8904->regmap); 1867 regcache_sync(wm8904->regmap);
1867 1868
1868 /* Enable bias */ 1869 /* Enable bias */
@@ -1899,14 +1900,8 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec,
1899 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 1900 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1900 WM8904_BIAS_ENA, 0); 1901 WM8904_BIAS_ENA, 0);
1901 1902
1902#ifdef CONFIG_REGULATOR 1903 regcache_cache_only(wm8904->regmap, true);
1903 /* Post 2.6.34 we will be able to get a callback when 1904 regcache_mark_dirty(wm8904->regmap);
1904 * the regulators are disabled which we can use but
1905 * for now just assume that the power will be cut if
1906 * the regulator API is in use.
1907 */
1908 codec->cache_sync = 1;
1909#endif
1910 1905
1911 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 1906 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1912 wm8904->supplies); 1907 wm8904->supplies);
@@ -2084,10 +2079,8 @@ static int wm8904_probe(struct snd_soc_codec *codec)
2084{ 2079{
2085 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2080 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2086 struct wm8904_pdata *pdata = wm8904->pdata; 2081 struct wm8904_pdata *pdata = wm8904->pdata;
2087 u16 *reg_cache = codec->reg_cache;
2088 int ret, i; 2082 int ret, i;
2089 2083
2090 codec->cache_sync = 1;
2091 codec->control_data = wm8904->regmap; 2084 codec->control_data = wm8904->regmap;
2092 2085
2093 switch (wm8904->devtype) { 2086 switch (wm8904->devtype) {
@@ -2150,6 +2143,7 @@ static int wm8904_probe(struct snd_soc_codec *codec)
2150 goto err_enable; 2143 goto err_enable;
2151 } 2144 }
2152 2145
2146 regcache_cache_only(wm8904->regmap, true);
2153 /* Change some default settings - latch VU and enable ZC */ 2147 /* Change some default settings - latch VU and enable ZC */
2154 snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_LEFT, 2148 snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2155 WM8904_ADC_VU, WM8904_ADC_VU); 2149 WM8904_ADC_VU, WM8904_ADC_VU);
@@ -2180,14 +2174,18 @@ static int wm8904_probe(struct snd_soc_codec *codec)
2180 if (!pdata->gpio_cfg[i]) 2174 if (!pdata->gpio_cfg[i])
2181 continue; 2175 continue;
2182 2176
2183 reg_cache[WM8904_GPIO_CONTROL_1 + i] 2177 regmap_update_bits(wm8904->regmap,
2184 = pdata->gpio_cfg[i] & 0xffff; 2178 WM8904_GPIO_CONTROL_1 + i,
2179 0xffff,
2180 pdata->gpio_cfg[i]);
2185 } 2181 }
2186 2182
2187 /* Zero is the default value for these anyway */ 2183 /* Zero is the default value for these anyway */
2188 for (i = 0; i < WM8904_MIC_REGS; i++) 2184 for (i = 0; i < WM8904_MIC_REGS; i++)
2189 reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] 2185 regmap_update_bits(wm8904->regmap,
2190 = pdata->mic_cfg[i]; 2186 WM8904_MIC_BIAS_CONTROL_0 + i,
2187 0xffff,
2188 pdata->mic_cfg[i]);
2191 } 2189 }
2192 2190
2193 /* Set Class W by default - this will be managed by the Class 2191 /* Set Class W by default - this will be managed by the Class
diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
index 8af422e38fd0..dc9b42b7fc4d 100644
--- a/sound/soc/codecs/wm8996.c
+++ b/sound/soc/codecs/wm8996.c
@@ -2837,8 +2837,6 @@ static int wm8996_probe(struct snd_soc_codec *codec)
2837 } 2837 }
2838 } 2838 }
2839 2839
2840 regcache_cache_only(codec->control_data, true);
2841
2842 /* Apply platform data settings */ 2840 /* Apply platform data settings */
2843 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL, 2841 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2844 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK, 2842 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
@@ -3051,7 +3049,6 @@ static int wm8996_remove(struct snd_soc_codec *codec)
3051 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 3049 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3052 regulator_unregister_notifier(wm8996->supplies[i].consumer, 3050 regulator_unregister_notifier(wm8996->supplies[i].consumer,
3053 &wm8996->disable_nb[i]); 3051 &wm8996->disable_nb[i]);
3054 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3055 3052
3056 return 0; 3053 return 0;
3057} 3054}
@@ -3206,14 +3203,15 @@ static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
3206 dev_info(&i2c->dev, "revision %c\n", 3203 dev_info(&i2c->dev, "revision %c\n",
3207 (reg & WM8996_CHIP_REV_MASK) + 'A'); 3204 (reg & WM8996_CHIP_REV_MASK) + 'A');
3208 3205
3209 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3210
3211 ret = wm8996_reset(wm8996); 3206 ret = wm8996_reset(wm8996);
3212 if (ret < 0) { 3207 if (ret < 0) {
3213 dev_err(&i2c->dev, "Failed to issue reset\n"); 3208 dev_err(&i2c->dev, "Failed to issue reset\n");
3214 goto err_regmap; 3209 goto err_regmap;
3215 } 3210 }
3216 3211
3212 regcache_cache_only(wm8996->regmap, true);
3213 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3214
3217 wm8996_init_gpio(wm8996); 3215 wm8996_init_gpio(wm8996);
3218 3216
3219 ret = snd_soc_register_codec(&i2c->dev, 3217 ret = snd_soc_register_codec(&i2c->dev,
diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c
index 1c2aa7fab3fd..4da5fc55c7ee 100644
--- a/sound/soc/pxa/pxa-ssp.c
+++ b/sound/soc/pxa/pxa-ssp.c
@@ -33,7 +33,6 @@
33 33
34#include <mach/hardware.h> 34#include <mach/hardware.h>
35#include <mach/dma.h> 35#include <mach/dma.h>
36#include <mach/audio.h>
37 36
38#include "../../arm/pxa2xx-pcm.h" 37#include "../../arm/pxa2xx-pcm.h"
39#include "pxa-ssp.h" 38#include "pxa-ssp.h"
@@ -194,7 +193,7 @@ static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
194{ 193{
195 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); 194 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
196 195
197 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) { 196 if (ssp->type == PXA25x_SSP) {
198 sscr0 &= ~0x0000ff00; 197 sscr0 &= ~0x0000ff00;
199 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */ 198 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
200 } else { 199 } else {
@@ -212,7 +211,7 @@ static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
212 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); 211 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
213 u32 div; 212 u32 div;
214 213
215 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) 214 if (ssp->type == PXA25x_SSP)
216 div = ((sscr0 >> 8) & 0xff) * 2 + 2; 215 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
217 else 216 else
218 div = ((sscr0 >> 8) & 0xfff) + 1; 217 div = ((sscr0 >> 8) & 0xfff) + 1;
@@ -242,7 +241,7 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
242 break; 241 break;
243 case PXA_SSP_CLK_PLL: 242 case PXA_SSP_CLK_PLL:
244 /* Internal PLL is fixed */ 243 /* Internal PLL is fixed */
245 if (cpu_is_pxa25x()) 244 if (ssp->type == PXA25x_SSP)
246 priv->sysclk = 1843200; 245 priv->sysclk = 1843200;
247 else 246 else
248 priv->sysclk = 13000000; 247 priv->sysclk = 13000000;
@@ -266,11 +265,11 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
266 265
267 /* The SSP clock must be disabled when changing SSP clock mode 266 /* The SSP clock must be disabled when changing SSP clock mode
268 * on PXA2xx. On PXA3xx it must be enabled when doing so. */ 267 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
269 if (!cpu_is_pxa3xx()) 268 if (ssp->type != PXA3xx_SSP)
270 clk_disable(ssp->clk); 269 clk_disable(ssp->clk);
271 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0; 270 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
272 pxa_ssp_write_reg(ssp, SSCR0, val); 271 pxa_ssp_write_reg(ssp, SSCR0, val);
273 if (!cpu_is_pxa3xx()) 272 if (ssp->type != PXA3xx_SSP)
274 clk_enable(ssp->clk); 273 clk_enable(ssp->clk);
275 274
276 return 0; 275 return 0;
@@ -294,24 +293,20 @@ static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
294 case PXA_SSP_AUDIO_DIV_SCDB: 293 case PXA_SSP_AUDIO_DIV_SCDB:
295 val = pxa_ssp_read_reg(ssp, SSACD); 294 val = pxa_ssp_read_reg(ssp, SSACD);
296 val &= ~SSACD_SCDB; 295 val &= ~SSACD_SCDB;
297#if defined(CONFIG_PXA3xx) 296 if (ssp->type == PXA3xx_SSP)
298 if (cpu_is_pxa3xx())
299 val &= ~SSACD_SCDX8; 297 val &= ~SSACD_SCDX8;
300#endif
301 switch (div) { 298 switch (div) {
302 case PXA_SSP_CLK_SCDB_1: 299 case PXA_SSP_CLK_SCDB_1:
303 val |= SSACD_SCDB; 300 val |= SSACD_SCDB;
304 break; 301 break;
305 case PXA_SSP_CLK_SCDB_4: 302 case PXA_SSP_CLK_SCDB_4:
306 break; 303 break;
307#if defined(CONFIG_PXA3xx)
308 case PXA_SSP_CLK_SCDB_8: 304 case PXA_SSP_CLK_SCDB_8:
309 if (cpu_is_pxa3xx()) 305 if (ssp->type == PXA3xx_SSP)
310 val |= SSACD_SCDX8; 306 val |= SSACD_SCDX8;
311 else 307 else
312 return -EINVAL; 308 return -EINVAL;
313 break; 309 break;
314#endif
315 default: 310 default:
316 return -EINVAL; 311 return -EINVAL;
317 } 312 }
@@ -337,10 +332,8 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
337 struct ssp_device *ssp = priv->ssp; 332 struct ssp_device *ssp = priv->ssp;
338 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70; 333 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
339 334
340#if defined(CONFIG_PXA3xx) 335 if (ssp->type == PXA3xx_SSP)
341 if (cpu_is_pxa3xx())
342 pxa_ssp_write_reg(ssp, SSACDD, 0); 336 pxa_ssp_write_reg(ssp, SSACDD, 0);
343#endif
344 337
345 switch (freq_out) { 338 switch (freq_out) {
346 case 5622000: 339 case 5622000:
@@ -365,11 +358,10 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
365 break; 358 break;
366 359
367 default: 360 default:
368#ifdef CONFIG_PXA3xx
369 /* PXA3xx has a clock ditherer which can be used to generate 361 /* PXA3xx has a clock ditherer which can be used to generate
370 * a wider range of frequencies - calculate a value for it. 362 * a wider range of frequencies - calculate a value for it.
371 */ 363 */
372 if (cpu_is_pxa3xx()) { 364 if (ssp->type == PXA3xx_SSP) {
373 u32 val; 365 u32 val;
374 u64 tmp = 19968; 366 u64 tmp = 19968;
375 tmp *= 1000000; 367 tmp *= 1000000;
@@ -386,7 +378,6 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
386 val, freq_out); 378 val, freq_out);
387 break; 379 break;
388 } 380 }
389#endif
390 381
391 return -EINVAL; 382 return -EINVAL;
392 } 383 }
@@ -590,10 +581,8 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
590 /* bit size */ 581 /* bit size */
591 switch (params_format(params)) { 582 switch (params_format(params)) {
592 case SNDRV_PCM_FORMAT_S16_LE: 583 case SNDRV_PCM_FORMAT_S16_LE:
593#ifdef CONFIG_PXA3xx 584 if (ssp->type == PXA3xx_SSP)
594 if (cpu_is_pxa3xx())
595 sscr0 |= SSCR0_FPCKE; 585 sscr0 |= SSCR0_FPCKE;
596#endif
597 sscr0 |= SSCR0_DataSize(16); 586 sscr0 |= SSCR0_DataSize(16);
598 break; 587 break;
599 case SNDRV_PCM_FORMAT_S24_LE: 588 case SNDRV_PCM_FORMAT_S24_LE:
@@ -618,9 +607,7 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
618 * trying and failing a lot; some of the registers 607 * trying and failing a lot; some of the registers
619 * needed for that mode are only available on PXA3xx. 608 * needed for that mode are only available on PXA3xx.
620 */ 609 */
621 610 if (ssp->type != PXA3xx_SSP)
622#ifdef CONFIG_PXA3xx
623 if (!cpu_is_pxa3xx())
624 return -EINVAL; 611 return -EINVAL;
625 612
626 sspsp |= SSPSP_SFRMWDTH(width * 2); 613 sspsp |= SSPSP_SFRMWDTH(width * 2);
@@ -628,9 +615,6 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
628 sspsp |= SSPSP_EDMYSTOP(3); 615 sspsp |= SSPSP_EDMYSTOP(3);
629 sspsp |= SSPSP_DMYSTOP(3); 616 sspsp |= SSPSP_DMYSTOP(3);
630 sspsp |= SSPSP_DMYSTRT(1); 617 sspsp |= SSPSP_DMYSTRT(1);
631#else
632 return -EINVAL;
633#endif
634 } else { 618 } else {
635 /* The frame width is the width the LRCLK is 619 /* The frame width is the width the LRCLK is
636 * asserted for; the delay is expressed in 620 * asserted for; the delay is expressed in
diff --git a/sound/soc/tegra/tegra_wm8903.c b/sound/soc/tegra/tegra_wm8903.c
index 0b0df49d9d33..3b6da91188a9 100644
--- a/sound/soc/tegra/tegra_wm8903.c
+++ b/sound/soc/tegra/tegra_wm8903.c
@@ -346,6 +346,17 @@ static int tegra_wm8903_init(struct snd_soc_pcm_runtime *rtd)
346 return 0; 346 return 0;
347} 347}
348 348
349static int tegra_wm8903_remove(struct snd_soc_card *card)
350{
351 struct snd_soc_pcm_runtime *rtd = &(card->rtd[0]);
352 struct snd_soc_dai *codec_dai = rtd->codec_dai;
353 struct snd_soc_codec *codec = codec_dai->codec;
354
355 wm8903_mic_detect(codec, NULL, 0, 0);
356
357 return 0;
358}
359
349static struct snd_soc_dai_link tegra_wm8903_dai = { 360static struct snd_soc_dai_link tegra_wm8903_dai = {
350 .name = "WM8903", 361 .name = "WM8903",
351 .stream_name = "WM8903 PCM", 362 .stream_name = "WM8903 PCM",
@@ -363,6 +374,8 @@ static struct snd_soc_card snd_soc_tegra_wm8903 = {
363 .dai_link = &tegra_wm8903_dai, 374 .dai_link = &tegra_wm8903_dai,
364 .num_links = 1, 375 .num_links = 1,
365 376
377 .remove = tegra_wm8903_remove,
378
366 .controls = tegra_wm8903_controls, 379 .controls = tegra_wm8903_controls,
367 .num_controls = ARRAY_SIZE(tegra_wm8903_controls), 380 .num_controls = ARRAY_SIZE(tegra_wm8903_controls),
368 .dapm_widgets = tegra_wm8903_dapm_widgets, 381 .dapm_widgets = tegra_wm8903_dapm_widgets,