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authorEero Nurkkala <ext-eero.nurkkala@nokia.com>2009-08-20 09:18:24 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-08-20 15:10:29 -0400
commitca6e2ce08679c094878d7f39a0349a7db1d13675 (patch)
tree2b2bac37dad9a8c888503deb2bd51e18bba9b02a /sound/soc
parentc721bbdad71d2928e8b5015e9b462fbeb35427c6 (diff)
ASoC: Always syncronize audio transfers on frames
All these steps are required for ASoC to behave correctly. rccr and xccr are format dependent, for example TDM audio has different values than I2S or DSP_A. Also the omap_mcbsp_xmit_enable and/or omap_mcbsp_recv_enable must be called right after the DMA has started. This provides no longer L and R channels switching at random. Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc')
-rw-r--r--sound/soc/omap/omap-mcbsp.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index a7b09614734d..6e855080e6ea 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -191,6 +191,11 @@ static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
191 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 191 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
192 mcbsp_data->active++; 192 mcbsp_data->active++;
193 omap_mcbsp_start(mcbsp_data->bus_id, play, !play); 193 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
194 /* Make sure data transfer is frame synchronized */
195 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
196 omap_mcbsp_xmit_enable(mcbsp_data->bus_id, 1);
197 else
198 omap_mcbsp_recv_enable(mcbsp_data->bus_id, 1);
194 break; 199 break;
195 200
196 case SNDRV_PCM_TRIGGER_STOP: 201 case SNDRV_PCM_TRIGGER_STOP:
@@ -336,11 +341,15 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
336 /* 1-bit data delay */ 341 /* 1-bit data delay */
337 regs->rcr2 |= RDATDLY(1); 342 regs->rcr2 |= RDATDLY(1);
338 regs->xcr2 |= XDATDLY(1); 343 regs->xcr2 |= XDATDLY(1);
344 regs->rccr |= RFULL_CYCLE | RDMAEN | RDISABLE;
345 regs->xccr |= (DXENDLY(1) | XDMAEN | XDISABLE);
339 break; 346 break;
340 case SND_SOC_DAIFMT_DSP_A: 347 case SND_SOC_DAIFMT_DSP_A:
341 /* 1-bit data delay */ 348 /* 1-bit data delay */
342 regs->rcr2 |= RDATDLY(1); 349 regs->rcr2 |= RDATDLY(1);
343 regs->xcr2 |= XDATDLY(1); 350 regs->xcr2 |= XDATDLY(1);
351 regs->rccr |= RFULL_CYCLE | RDMAEN | RDISABLE;
352 regs->xccr |= (DXENDLY(1) | XDMAEN | XDISABLE);
344 /* Invert FS polarity configuration */ 353 /* Invert FS polarity configuration */
345 temp_fmt ^= SND_SOC_DAIFMT_NB_IF; 354 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
346 break; 355 break;