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authorLars-Peter Clausen <lars@metafoo.de>2010-12-28 15:38:00 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-12-28 18:20:00 -0500
commit715920d04c787ed718327da53cf51689e51ef3ce (patch)
tree48f445e0c21341f1456d5ccc85e7e6ab1fc30f37 /sound/soc
parentf578a188e8b21be623b48bb0eb3a92174c2e5b82 (diff)
ASoC: codecs: wm8955: Fix register cache incoherency
The multi-component patch(commit f0fba2ad1) moved the allocation of the register cache from the driver to the ASoC core. Most drivers where adjusted to this, but the wm8955 driver still uses its own register cache for its private functions, while functions from the ASoC core use the generic cache. Thus we end up with two from each other incoherent caches, which can lead to undefined behaviour. This patch fixes the issue by changing the wm8955 driver to use the generic register cache in its private functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: stable@kernel.org (for 2.6.37 only)
Diffstat (limited to 'sound/soc')
-rw-r--r--sound/soc/codecs/wm8955.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/sound/soc/codecs/wm8955.c b/sound/soc/codecs/wm8955.c
index a2ad91d6078a..2ac35b0be86a 100644
--- a/sound/soc/codecs/wm8955.c
+++ b/sound/soc/codecs/wm8955.c
@@ -42,8 +42,6 @@ static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
42struct wm8955_priv { 42struct wm8955_priv {
43 enum snd_soc_control_type control_type; 43 enum snd_soc_control_type control_type;
44 44
45 u16 reg_cache[WM8955_MAX_REGISTER + 1];
46
47 unsigned int mclk_rate; 45 unsigned int mclk_rate;
48 46
49 int deemph; 47 int deemph;
@@ -768,6 +766,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
768 enum snd_soc_bias_level level) 766 enum snd_soc_bias_level level)
769{ 767{
770 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); 768 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
769 u16 *reg_cache = codec->reg_cache;
771 int ret, i; 770 int ret, i;
772 771
773 switch (level) { 772 switch (level) {
@@ -800,14 +799,14 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
800 /* Sync back cached values if they're 799 /* Sync back cached values if they're
801 * different from the hardware default. 800 * different from the hardware default.
802 */ 801 */
803 for (i = 0; i < ARRAY_SIZE(wm8955->reg_cache); i++) { 802 for (i = 0; i < codec->driver->reg_cache_size; i++) {
804 if (i == WM8955_RESET) 803 if (i == WM8955_RESET)
805 continue; 804 continue;
806 805
807 if (wm8955->reg_cache[i] == wm8955_reg[i]) 806 if (reg_cache[i] == wm8955_reg[i])
808 continue; 807 continue;
809 808
810 snd_soc_write(codec, i, wm8955->reg_cache[i]); 809 snd_soc_write(codec, i, reg_cache[i]);
811 } 810 }
812 811
813 /* Enable VREF and VMID */ 812 /* Enable VREF and VMID */
@@ -902,6 +901,7 @@ static int wm8955_probe(struct snd_soc_codec *codec)
902{ 901{
903 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); 902 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
904 struct wm8955_pdata *pdata = dev_get_platdata(codec->dev); 903 struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
904 u16 *reg_cache = codec->reg_cache;
905 int ret, i; 905 int ret, i;
906 906
907 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type); 907 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type);
@@ -934,25 +934,25 @@ static int wm8955_probe(struct snd_soc_codec *codec)
934 } 934 }
935 935
936 /* Change some default settings - latch VU and enable ZC */ 936 /* Change some default settings - latch VU and enable ZC */
937 wm8955->reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU; 937 reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU;
938 wm8955->reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU; 938 reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU;
939 wm8955->reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC; 939 reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC;
940 wm8955->reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC; 940 reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC;
941 wm8955->reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC; 941 reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC;
942 wm8955->reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC; 942 reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC;
943 wm8955->reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC; 943 reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC;
944 944
945 /* Also enable adaptive bass boost by default */ 945 /* Also enable adaptive bass boost by default */
946 wm8955->reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB; 946 reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB;
947 947
948 /* Set platform data values */ 948 /* Set platform data values */
949 if (pdata) { 949 if (pdata) {
950 if (pdata->out2_speaker) 950 if (pdata->out2_speaker)
951 wm8955->reg_cache[WM8955_ADDITIONAL_CONTROL_2] 951 reg_cache[WM8955_ADDITIONAL_CONTROL_2]
952 |= WM8955_ROUT2INV; 952 |= WM8955_ROUT2INV;
953 953
954 if (pdata->monoin_diff) 954 if (pdata->monoin_diff)
955 wm8955->reg_cache[WM8955_MONO_OUT_MIX_1] 955 reg_cache[WM8955_MONO_OUT_MIX_1]
956 |= WM8955_DMEN; 956 |= WM8955_DMEN;
957 } 957 }
958 958