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authorPeter Ujfalusi <peter.ujfalusi@nokia.com>2009-12-31 03:30:21 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-12-31 06:54:27 -0500
commitaec242dc3719e19bd7c1561f8a56a4eb37bb3987 (patch)
treee216c735e20f0c9905fb50567d1047b543e6654a /sound/soc
parentd4f102d437c069a64f3a4c7a6cd50360e034541f (diff)
ASoC: tlv320dac33: Clean up the hardware configuration code
Use switch instead of if statements to configure FIFO bypass and mode1. With this change adding new FIFO mode is going to be easier, and cleaner. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc')
-rw-r--r--sound/soc/codecs/tlv320dac33.c61
1 files changed, 45 insertions, 16 deletions
diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index f7c7bbceb3db..c684aa23bd51 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -707,7 +707,7 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
707 struct snd_soc_codec *codec = socdev->card->codec; 707 struct snd_soc_codec *codec = socdev->card->codec;
708 struct tlv320dac33_priv *dac33 = codec->private_data; 708 struct tlv320dac33_priv *dac33 = codec->private_data;
709 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; 709 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
710 u8 aictrl_a, fifoctrl_a; 710 u8 aictrl_a, aictrl_b, fifoctrl_a;
711 711
712 switch (substream->runtime->rate) { 712 switch (substream->runtime->rate) {
713 case 44100: 713 case 44100:
@@ -764,6 +764,7 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
764 dac33_oscwait(codec); 764 dac33_oscwait(codec);
765 765
766 if (dac33->fifo_mode) { 766 if (dac33->fifo_mode) {
767 /* Generic for all FIFO modes */
767 /* 50-51 : ASRC Control registers */ 768 /* 50-51 : ASRC Control registers */
768 dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */ 769 dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
769 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */ 770 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
@@ -773,38 +774,66 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
773 774
774 /* Set interrupts to high active */ 775 /* Set interrupts to high active */
775 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); 776 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
776
777 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
778 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
779 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
780 } else { 777 } else {
778 /* FIFO bypass mode */
781 /* 50-51 : ASRC Control registers */ 779 /* 50-51 : ASRC Control registers */
782 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); 780 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
783 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */ 781 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
784 } 782 }
785 783
786 if (dac33->fifo_mode) 784 /* Interrupt behaviour configuration */
785 switch (dac33->fifo_mode) {
786 case DAC33_FIFO_MODE1:
787 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
788 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
789 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
790 break;
791 default:
792 /* in FIFO bypass mode, the interrupts are not used */
793 break;
794 }
795
796 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
797
798 switch (dac33->fifo_mode) {
799 case DAC33_FIFO_MODE1:
800 /*
801 * For mode1:
802 * Disable the FIFO bypass (Enable the use of FIFO)
803 * Select nSample mode
804 * BCLK is only running when data is needed by DAC33
805 */
787 fifoctrl_a &= ~DAC33_FBYPAS; 806 fifoctrl_a &= ~DAC33_FBYPAS;
788 else 807 fifoctrl_a &= ~DAC33_FAUTO;
808 aictrl_b &= ~DAC33_BCLKON;
809 break;
810 default:
811 /*
812 * For FIFO bypass mode:
813 * Enable the FIFO bypass (Disable the FIFO use)
814 * Set the BCLK as continous
815 */
789 fifoctrl_a |= DAC33_FBYPAS; 816 fifoctrl_a |= DAC33_FBYPAS;
790 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a); 817 aictrl_b |= DAC33_BCLKON;
818 break;
819 }
791 820
821 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
792 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 822 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
793 reg_tmp = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 823 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
794 if (dac33->fifo_mode)
795 reg_tmp &= ~DAC33_BCLKON;
796 else
797 reg_tmp |= DAC33_BCLKON;
798 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg_tmp);
799 824
800 if (dac33->fifo_mode) { 825 switch (dac33->fifo_mode) {
826 case DAC33_FIFO_MODE1:
801 /* 20: BCLK divide ratio */ 827 /* 20: BCLK divide ratio */
802 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 3); 828 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 3);
803 829
804 dac33_write16(codec, DAC33_ATHR_MSB, 830 dac33_write16(codec, DAC33_ATHR_MSB,
805 DAC33_THRREG(dac33->alarm_threshold)); 831 DAC33_THRREG(dac33->alarm_threshold));
806 } else { 832 break;
833 default:
834 /* BYPASS mode */
807 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); 835 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
836 break;
808 } 837 }
809 838
810 mutex_unlock(&dac33->mutex); 839 mutex_unlock(&dac33->mutex);