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authorManuel Lauss <mano@roarinelk.homelinux.net>2007-05-14 12:40:07 -0400
committerJaroslav Kysela <perex@suse.cz>2007-07-20 05:11:17 -0400
commitaef3b06ac69783d6a6d1e4357c62bab46dd16141 (patch)
tree7c4e86d880a08ee5639d87a3702f7318203710d5 /sound/soc/sh
parent80ab1c0e9ea90467e34dd3187b1d8162e8be314b (diff)
[ALSA] SH7760 ASoC support
ALSA ASoC support for SH7760 This patch adds ALSA ASoC drivers for the Audio interfaces of the SH7760 SoC: Add driver for the SH7760 DMA engine (dmabrg) Add AC97 driver for HAC unit(s) found on SH7760/SH7780 Add I2S driver for SSI unit(s) found on SH7760/SH7780 Add a generic SH7760-AC97 machine driver. Hook it all up with the build system. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
Diffstat (limited to 'sound/soc/sh')
-rw-r--r--sound/soc/sh/Kconfig39
-rw-r--r--sound/soc/sh/Makefile14
-rw-r--r--sound/soc/sh/dma-sh7760.c354
-rw-r--r--sound/soc/sh/hac.c322
-rw-r--r--sound/soc/sh/sh7760-ac97.c92
-rw-r--r--sound/soc/sh/ssi.c400
6 files changed, 1221 insertions, 0 deletions
diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
new file mode 100644
index 000000000000..a332e51d6887
--- /dev/null
+++ b/sound/soc/sh/Kconfig
@@ -0,0 +1,39 @@
1menu "SoC Audio support for SuperH"
2
3config SND_SOC_PCM_SH7760
4 tristate "SoC Audio support for Renesas SH7760"
5 depends on CPU_SUBTYPE_SH7760 && SND_SOC
6 select SH_DMABRG
7 help
8 Enable this option for SH7760 AC97/I2S audio support.
9
10
11##
12## Audio unit modules
13##
14
15config SND_SOC_SH4_HAC
16 select AC97_BUS
17 select SND_SOC_AC97_BUS
18 select SND_AC97_CODEC
19 tristate
20
21config SND_SOC_SH4_SSI
22 tristate
23
24
25
26##
27## Boards
28##
29
30config SND_SH7760_AC97
31 tristate "SH7760 AC97 sound support"
32 depends on CPU_SUBTYPE_SH7760 && SND_SOC_PCM_SH7760
33 select SND_SOC_SH4_HAC
34 select SND_SOC_AC97_CODEC
35 help
36 This option enables generic sound support for the first
37 AC97 unit of the SH7760.
38
39endmenu
diff --git a/sound/soc/sh/Makefile b/sound/soc/sh/Makefile
new file mode 100644
index 000000000000..a8e8ab81cc6a
--- /dev/null
+++ b/sound/soc/sh/Makefile
@@ -0,0 +1,14 @@
1## DMA engines
2snd-soc-dma-sh7760-objs := dma-sh7760.o
3obj-$(CONFIG_SND_SOC_PCM_SH7760) += snd-soc-dma-sh7760.o
4
5## audio units found on some SH-4
6snd-soc-hac-objs := hac.o
7snd-soc-ssi-objs := ssi.o
8obj-$(CONFIG_SND_SOC_SH4_HAC) += snd-soc-hac.o
9obj-$(CONFIG_SND_SOC_SH4_SSI) += snd-soc-ssi.o
10
11## boards
12snd-soc-sh7760-ac97-objs := sh7760-ac97.o
13
14obj-$(CONFIG_SND_SH7760_AC97) += snd-soc-sh7760-ac97.o
diff --git a/sound/soc/sh/dma-sh7760.c b/sound/soc/sh/dma-sh7760.c
new file mode 100644
index 000000000000..cdee374b843e
--- /dev/null
+++ b/sound/soc/sh/dma-sh7760.c
@@ -0,0 +1,354 @@
1/*
2 * SH7760 ("camelot") DMABRG audio DMA unit support
3 *
4 * Copyright (C) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
5 * licensed under the terms outlined in the file COPYING at the root
6 * of the linux kernel sources.
7 *
8 * The SH7760 DMABRG provides 4 dma channels (2x rec, 2x play), which
9 * trigger an interrupt when one half of the programmed transfer size
10 * has been xmitted.
11 *
12 * FIXME: little-endian only for now
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <sound/driver.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/soc.h>
24#include <asm/dmabrg.h>
25
26
27/* registers and bits */
28#define BRGATXSAR 0x00
29#define BRGARXDAR 0x04
30#define BRGATXTCR 0x08
31#define BRGARXTCR 0x0C
32#define BRGACR 0x10
33#define BRGATXTCNT 0x14
34#define BRGARXTCNT 0x18
35
36#define ACR_RAR (1 << 18)
37#define ACR_RDS (1 << 17)
38#define ACR_RDE (1 << 16)
39#define ACR_TAR (1 << 2)
40#define ACR_TDS (1 << 1)
41#define ACR_TDE (1 << 0)
42
43/* receiver/transmitter data alignment */
44#define ACR_RAM_NONE (0 << 24)
45#define ACR_RAM_4BYTE (1 << 24)
46#define ACR_RAM_2WORD (2 << 24)
47#define ACR_TAM_NONE (0 << 8)
48#define ACR_TAM_4BYTE (1 << 8)
49#define ACR_TAM_2WORD (2 << 8)
50
51
52struct camelot_pcm {
53 unsigned long mmio; /* DMABRG audio channel control reg MMIO */
54 unsigned int txid; /* ID of first DMABRG IRQ for this unit */
55
56 struct snd_pcm_substream *tx_ss;
57 unsigned long tx_period_size;
58 unsigned int tx_period;
59
60 struct snd_pcm_substream *rx_ss;
61 unsigned long rx_period_size;
62 unsigned int rx_period;
63
64} cam_pcm_data[2] = {
65 {
66 .mmio = 0xFE3C0040,
67 .txid = DMABRGIRQ_A0TXF,
68 },
69 {
70 .mmio = 0xFE3C0060,
71 .txid = DMABRGIRQ_A1TXF,
72 },
73};
74
75#define BRGREG(x) (*(unsigned long *)(cam->mmio + (x)))
76
77/*
78 * set a minimum of 16kb per period, to avoid interrupt-"storm" and
79 * resulting skipping. In general, the bigger the minimum size, the
80 * better for overall system performance. (The SH7760 is a puny CPU
81 * with a slow SDRAM interface and poor internal bus bandwidth,
82 * *especially* when the LCDC is active). The minimum for the DMAC
83 * is 8 bytes; 16kbytes are enough to get skip-free playback of a
84 * 44kHz/16bit/stereo MP3 on a lightly loaded system, and maintain
85 * reasonable responsiveness in MPlayer.
86 */
87#define DMABRG_PERIOD_MIN 16 * 1024
88#define DMABRG_PERIOD_MAX 0x03fffffc
89#define DMABRG_PREALLOC_BUFFER 32 * 1024
90#define DMABRG_PREALLOC_BUFFER_MAX 32 * 1024
91
92/* support everything the SSI supports */
93#define DMABRG_RATES \
94 SNDRV_PCM_RATE_8000_192000
95
96#define DMABRG_FMTS \
97 (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \
98 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
99 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
100 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_U24_3LE | \
101 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
102
103static struct snd_pcm_hardware camelot_pcm_hardware = {
104 .info = (SNDRV_PCM_INFO_MMAP |
105 SNDRV_PCM_INFO_INTERLEAVED |
106 SNDRV_PCM_INFO_BLOCK_TRANSFER |
107 SNDRV_PCM_INFO_MMAP_VALID),
108 .formats = DMABRG_FMTS,
109 .rates = DMABRG_RATES,
110 .rate_min = 8000,
111 .rate_max = 192000,
112 .channels_min = 2,
113 .channels_max = 8, /* max of the SSI */
114 .buffer_bytes_max = DMABRG_PERIOD_MAX,
115 .period_bytes_min = DMABRG_PERIOD_MIN,
116 .period_bytes_max = DMABRG_PERIOD_MAX / 2,
117 .periods_min = 2,
118 .periods_max = 2,
119 .fifo_size = 128,
120};
121
122static void camelot_txdma(void *data)
123{
124 struct camelot_pcm *cam = data;
125 cam->tx_period ^= 1;
126 snd_pcm_period_elapsed(cam->tx_ss);
127}
128
129static void camelot_rxdma(void *data)
130{
131 struct camelot_pcm *cam = data;
132 cam->rx_period ^= 1;
133 snd_pcm_period_elapsed(cam->rx_ss);
134}
135
136static int camelot_pcm_open(struct snd_pcm_substream *substream)
137{
138 struct snd_soc_pcm_runtime *rtd = substream->private_data;
139 struct camelot_pcm *cam = &cam_pcm_data[rtd->dai->cpu_dai->id];
140 int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
141 int ret, dmairq;
142
143 snd_soc_set_runtime_hwparams(substream, &camelot_pcm_hardware);
144
145 /* DMABRG buffer half/full events */
146 dmairq = (recv) ? cam->txid + 2 : cam->txid;
147 if (recv) {
148 cam->rx_ss = substream;
149 ret = dmabrg_request_irq(dmairq, camelot_rxdma, cam);
150 if (unlikely(ret)) {
151 pr_debug("audio unit %d irqs already taken!\n",
152 rtd->dai->cpu_dai->id);
153 return -EBUSY;
154 }
155 (void)dmabrg_request_irq(dmairq + 1,camelot_rxdma, cam);
156 } else {
157 cam->tx_ss = substream;
158 ret = dmabrg_request_irq(dmairq, camelot_txdma, cam);
159 if (unlikely(ret)) {
160 pr_debug("audio unit %d irqs already taken!\n",
161 rtd->dai->cpu_dai->id);
162 return -EBUSY;
163 }
164 (void)dmabrg_request_irq(dmairq + 1, camelot_txdma, cam);
165 }
166 return 0;
167}
168
169static int camelot_pcm_close(struct snd_pcm_substream *substream)
170{
171 struct snd_soc_pcm_runtime *rtd = substream->private_data;
172 struct camelot_pcm *cam = &cam_pcm_data[rtd->dai->cpu_dai->id];
173 int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
174 int dmairq;
175
176 dmairq = (recv) ? cam->txid + 2 : cam->txid;
177
178 if (recv)
179 cam->rx_ss = NULL;
180 else
181 cam->tx_ss = NULL;
182
183 dmabrg_free_irq(dmairq + 1);
184 dmabrg_free_irq(dmairq);
185
186 return 0;
187}
188
189static int camelot_hw_params(struct snd_pcm_substream *substream,
190 struct snd_pcm_hw_params *hw_params)
191{
192 struct snd_soc_pcm_runtime *rtd = substream->private_data;
193 struct camelot_pcm *cam = &cam_pcm_data[rtd->dai->cpu_dai->id];
194 int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
195 int ret;
196
197 ret = snd_pcm_lib_malloc_pages(substream,
198 params_buffer_bytes(hw_params));
199 if (ret < 0)
200 return ret;
201
202 if (recv) {
203 cam->rx_period_size = params_period_bytes(hw_params);
204 cam->rx_period = 0;
205 } else {
206 cam->tx_period_size = params_period_bytes(hw_params);
207 cam->tx_period = 0;
208 }
209 return 0;
210}
211
212static int camelot_hw_free(struct snd_pcm_substream *substream)
213{
214 return snd_pcm_lib_free_pages(substream);
215}
216
217static int camelot_prepare(struct snd_pcm_substream *substream)
218{
219 struct snd_pcm_runtime *runtime = substream->runtime;
220 struct snd_soc_pcm_runtime *rtd = substream->private_data;
221 struct camelot_pcm *cam = &cam_pcm_data[rtd->dai->cpu_dai->id];
222
223 pr_debug("PCM data: addr 0x%08ulx len %d\n",
224 (u32)runtime->dma_addr, runtime->dma_bytes);
225
226 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
227 BRGREG(BRGATXSAR) = (unsigned long)runtime->dma_area;
228 BRGREG(BRGATXTCR) = runtime->dma_bytes;
229 } else {
230 BRGREG(BRGARXDAR) = (unsigned long)runtime->dma_area;
231 BRGREG(BRGARXTCR) = runtime->dma_bytes;
232 }
233
234 return 0;
235}
236
237static inline void dmabrg_play_dma_start(struct camelot_pcm *cam)
238{
239 unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
240 /* start DMABRG engine: XFER start, auto-addr-reload */
241 BRGREG(BRGACR) = acr | ACR_TDE | ACR_TAR | ACR_TAM_2WORD;
242}
243
244static inline void dmabrg_play_dma_stop(struct camelot_pcm *cam)
245{
246 unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
247 /* forcibly terminate data transmission */
248 BRGREG(BRGACR) = acr | ACR_TDS;
249}
250
251static inline void dmabrg_rec_dma_start(struct camelot_pcm *cam)
252{
253 unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
254 /* start DMABRG engine: recv start, auto-reload */
255 BRGREG(BRGACR) = acr | ACR_RDE | ACR_RAR | ACR_RAM_2WORD;
256}
257
258static inline void dmabrg_rec_dma_stop(struct camelot_pcm *cam)
259{
260 unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
261 /* forcibly terminate data receiver */
262 BRGREG(BRGACR) = acr | ACR_RDS;
263}
264
265static int camelot_trigger(struct snd_pcm_substream *substream, int cmd)
266{
267 struct snd_soc_pcm_runtime *rtd = substream->private_data;
268 struct camelot_pcm *cam = &cam_pcm_data[rtd->dai->cpu_dai->id];
269 int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
270
271 switch (cmd) {
272 case SNDRV_PCM_TRIGGER_START:
273 if (recv)
274 dmabrg_rec_dma_start(cam);
275 else
276 dmabrg_play_dma_start(cam);
277 break;
278 case SNDRV_PCM_TRIGGER_STOP:
279 if (recv)
280 dmabrg_rec_dma_stop(cam);
281 else
282 dmabrg_play_dma_stop(cam);
283 break;
284 default:
285 return -EINVAL;
286 }
287
288 return 0;
289}
290
291static snd_pcm_uframes_t camelot_pos(struct snd_pcm_substream *substream)
292{
293 struct snd_pcm_runtime *runtime = substream->runtime;
294 struct snd_soc_pcm_runtime *rtd = substream->private_data;
295 struct camelot_pcm *cam = &cam_pcm_data[rtd->dai->cpu_dai->id];
296 int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
297 unsigned long pos;
298
299 /* cannot use the DMABRG pointer register: under load, by the
300 * time ALSA comes around to read the register, it is already
301 * far ahead (or worse, already done with the fragment) of the
302 * position at the time the IRQ was triggered, which results in
303 * fast-playback sound in my test application (ScummVM)
304 */
305 if (recv)
306 pos = cam->rx_period ? cam->rx_period_size : 0;
307 else
308 pos = cam->tx_period ? cam->tx_period_size : 0;
309
310 return bytes_to_frames(runtime, pos);
311}
312
313static struct snd_pcm_ops camelot_pcm_ops = {
314 .open = camelot_pcm_open,
315 .close = camelot_pcm_close,
316 .ioctl = snd_pcm_lib_ioctl,
317 .hw_params = camelot_hw_params,
318 .hw_free = camelot_hw_free,
319 .prepare = camelot_prepare,
320 .trigger = camelot_trigger,
321 .pointer = camelot_pos,
322};
323
324static void camelot_pcm_free(struct snd_pcm *pcm)
325{
326 snd_pcm_lib_preallocate_free_for_all(pcm);
327}
328
329static int camelot_pcm_new(struct snd_card *card,
330 struct snd_soc_codec_dai *dai,
331 struct snd_pcm *pcm)
332{
333 /* dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
334 * in MMAP mode (i.e. aplay -M)
335 */
336 snd_pcm_lib_preallocate_pages_for_all(pcm,
337 SNDRV_DMA_TYPE_CONTINUOUS,
338 snd_dma_continuous_data(GFP_KERNEL),
339 DMABRG_PREALLOC_BUFFER, DMABRG_PREALLOC_BUFFER_MAX);
340
341 return 0;
342}
343
344struct snd_soc_platform sh7760_soc_platform = {
345 .name = "sh7760-pcm",
346 .pcm_ops = &camelot_pcm_ops,
347 .pcm_new = camelot_pcm_new,
348 .pcm_free = camelot_pcm_free,
349};
350EXPORT_SYMBOL_GPL(sh7760_soc_platform);
351
352MODULE_LICENSE("GPL");
353MODULE_DESCRIPTION("SH7760 Audio DMA (DMABRG) driver");
354MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
diff --git a/sound/soc/sh/hac.c b/sound/soc/sh/hac.c
new file mode 100644
index 000000000000..8e3f03908cdb
--- /dev/null
+++ b/sound/soc/sh/hac.c
@@ -0,0 +1,322 @@
1/*
2 * Hitachi Audio Controller (AC97) support for SH7760/SH7780
3 *
4 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
5 * licensed under the terms outlined in the file COPYING at the root
6 * of the linux kernel sources.
7 *
8 * dont forget to set IPSEL/OMSEL register bits (in your board code) to
9 * enable HAC output pins!
10 */
11
12/* BIG FAT FIXME: although the SH7760 has 2 independent AC97 units, only
13 * the FIRST can be used since ASoC does not pass any information to the
14 * ac97_read/write() functions regarding WHICH unit to use. You'll have
15 * to edit the code a bit to use the other AC97 unit. --mlau
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/interrupt.h>
22#include <linux/wait.h>
23#include <linux/delay.h>
24#include <sound/driver.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/ac97_codec.h>
28#include <sound/initval.h>
29#include <sound/soc.h>
30
31/* regs and bits */
32#define HACCR 0x08
33#define HACCSAR 0x20
34#define HACCSDR 0x24
35#define HACPCML 0x28
36#define HACPCMR 0x2C
37#define HACTIER 0x50
38#define HACTSR 0x54
39#define HACRIER 0x58
40#define HACRSR 0x5C
41#define HACACR 0x60
42
43#define CR_CR (1 << 15) /* "codec-ready" indicator */
44#define CR_CDRT (1 << 11) /* cold reset */
45#define CR_WMRT (1 << 10) /* warm reset */
46#define CR_B9 (1 << 9) /* the mysterious "bit 9" */
47#define CR_ST (1 << 5) /* AC97 link start bit */
48
49#define CSAR_RD (1 << 19) /* AC97 data read bit */
50#define CSAR_WR (0)
51
52#define TSR_CMDAMT (1 << 31)
53#define TSR_CMDDMT (1 << 30)
54
55#define RSR_STARY (1 << 22)
56#define RSR_STDRY (1 << 21)
57
58#define ACR_DMARX16 (1 << 30)
59#define ACR_DMATX16 (1 << 29)
60#define ACR_TX12ATOM (1 << 26)
61#define ACR_DMARX20 ((1 << 24) | (1 << 22))
62#define ACR_DMATX20 ((1 << 23) | (1 << 21))
63
64#define CSDR_SHIFT 4
65#define CSDR_MASK (0xffff << CSDR_SHIFT)
66#define CSAR_SHIFT 12
67#define CSAR_MASK (0x7f << CSAR_SHIFT)
68
69#define AC97_WRITE_RETRY 1
70#define AC97_READ_RETRY 5
71
72/* manual-suggested AC97 codec access timeouts (us) */
73#define TMO_E1 500 /* 21 < E1 < 1000 */
74#define TMO_E2 13 /* 13 < E2 */
75#define TMO_E3 21 /* 21 < E3 */
76#define TMO_E4 500 /* 21 < E4 < 1000 */
77
78struct hac_priv {
79 unsigned long mmio; /* HAC base address */
80} hac_cpu_data[] = {
81#if defined(CONFIG_CPU_SUBTYPE_SH7760)
82 {
83 .mmio = 0xFE240000,
84 },
85 {
86 .mmio = 0xFE250000,
87 },
88#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
89 {
90 .mmio = 0xFFE40000,
91 },
92#else
93#error "Unsupported SuperH SoC"
94#endif
95};
96
97#define HACREG(reg) (*(unsigned long *)(hac->mmio + (reg)))
98
99/*
100 * AC97 read/write flow as outlined in the SH7760 manual (pages 903-906)
101 */
102static int hac_get_codec_data(struct hac_priv *hac, unsigned short r,
103 unsigned short *v)
104{
105 unsigned int to1, to2, i;
106 unsigned short adr;
107
108 for (i = 0; i < AC97_READ_RETRY; ++i) {
109 *v = 0;
110 /* wait for HAC to receive something from the codec */
111 for (to1 = TMO_E4;
112 to1 && !(HACREG(HACRSR) & RSR_STARY);
113 --to1)
114 udelay(1);
115 for (to2 = TMO_E4;
116 to2 && !(HACREG(HACRSR) & RSR_STDRY);
117 --to2)
118 udelay(1);
119
120 if (!to1 && !to2)
121 return 0; /* codec comm is down */
122
123 adr = ((HACREG(HACCSAR) & CSAR_MASK) >> CSAR_SHIFT);
124 *v = ((HACREG(HACCSDR) & CSDR_MASK) >> CSDR_SHIFT);
125
126 HACREG(HACRSR) &= ~(RSR_STDRY | RSR_STARY);
127
128 if (r == adr)
129 break;
130
131 /* manual says: wait at least 21 usec before retrying */
132 udelay(21);
133 }
134 HACREG(HACRSR) &= ~(RSR_STDRY | RSR_STARY);
135 return (i < AC97_READ_RETRY);
136}
137
138static unsigned short hac_read_codec_aux(struct hac_priv *hac,
139 unsigned short reg)
140{
141 unsigned short val;
142 unsigned int i, to;
143
144 for (i = 0; i < AC97_READ_RETRY; i++) {
145 /* send_read_request */
146 local_irq_disable();
147 HACREG(HACTSR) &= ~(TSR_CMDAMT);
148 HACREG(HACCSAR) = (reg << CSAR_SHIFT) | CSAR_RD;
149 local_irq_enable();
150
151 for (to = TMO_E3;
152 to && !(HACREG(HACTSR) & TSR_CMDAMT);
153 --to)
154 udelay(1);
155
156 HACREG(HACTSR) &= ~TSR_CMDAMT;
157 val = 0;
158 if (hac_get_codec_data(hac, reg, &val) != 0)
159 break;
160 }
161
162 if (i == AC97_READ_RETRY)
163 return ~0;
164
165 return val;
166}
167
168static void hac_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
169 unsigned short val)
170{
171 int unit_id = 0 /* ac97->private_data */;
172 struct hac_priv *hac = &hac_cpu_data[unit_id];
173 unsigned int i, to;
174 /* write_codec_aux */
175 for (i = 0; i < AC97_WRITE_RETRY; i++) {
176 /* send_write_request */
177 local_irq_disable();
178 HACREG(HACTSR) &= ~(TSR_CMDDMT | TSR_CMDAMT);
179 HACREG(HACCSDR) = (val << CSDR_SHIFT);
180 HACREG(HACCSAR) = (reg << CSAR_SHIFT) & (~CSAR_RD);
181 local_irq_enable();
182
183 /* poll-wait for CMDAMT and CMDDMT */
184 for (to = TMO_E1;
185 to && !(HACREG(HACTSR) & (TSR_CMDAMT|TSR_CMDDMT));
186 --to)
187 udelay(1);
188
189 HACREG(HACTSR) &= ~(TSR_CMDAMT | TSR_CMDDMT);
190 if (to)
191 break;
192 /* timeout, try again */
193 }
194}
195
196static unsigned short hac_ac97_read(struct snd_ac97 *ac97,
197 unsigned short reg)
198{
199 int unit_id = 0 /* ac97->private_data */;
200 struct hac_priv *hac = &hac_cpu_data[unit_id];
201 return hac_read_codec_aux(hac, reg);
202}
203
204static void hac_ac97_warmrst(struct snd_ac97 *ac97)
205{
206 int unit_id = 0 /* ac97->private_data */;
207 struct hac_priv *hac = &hac_cpu_data[unit_id];
208 unsigned int tmo;
209
210 HACREG(HACCR) = CR_WMRT | CR_ST | CR_B9;
211 msleep(10);
212 HACREG(HACCR) = CR_ST | CR_B9;
213 for (tmo = 1000; (tmo > 0) && !(HACREG(HACCR) & CR_CR); tmo--)
214 udelay(1);
215
216 if (!tmo)
217 printk(KERN_INFO "hac: reset: AC97 link down!\n");
218 /* settings this bit lets us have a conversation with codec */
219 HACREG(HACACR) |= ACR_TX12ATOM;
220}
221
222static void hac_ac97_coldrst(struct snd_ac97 *ac97)
223{
224 int unit_id = 0 /* ac97->private_data */;
225 struct hac_priv *hac;
226 hac = &hac_cpu_data[unit_id];
227
228 HACREG(HACCR) = 0;
229 HACREG(HACCR) = CR_CDRT | CR_ST | CR_B9;
230 msleep(10);
231 hac_ac97_warmrst(ac97);
232}
233
234struct snd_ac97_bus_ops soc_ac97_ops = {
235 .read = hac_ac97_read,
236 .write = hac_ac97_write,
237 .reset = hac_ac97_coldrst,
238 .warm_reset = hac_ac97_warmrst,
239};
240EXPORT_SYMBOL_GPL(soc_ac97_ops);
241
242static int hac_hw_params(struct snd_pcm_substream *substream,
243 struct snd_pcm_hw_params *params)
244{
245 struct snd_soc_pcm_runtime *rtd = substream->private_data;
246 struct hac_priv *hac = &hac_cpu_data[rtd->dai->cpu_dai->id];
247 int d = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
248
249 switch (params->msbits) {
250 case 16:
251 HACREG(HACACR) |= d ? ACR_DMARX16 : ACR_DMATX16;
252 HACREG(HACACR) &= d ? ~ACR_DMARX20 : ~ACR_DMATX20;
253 break;
254 case 20:
255 HACREG(HACACR) &= d ? ~ACR_DMARX16 : ~ACR_DMATX16;
256 HACREG(HACACR) |= d ? ACR_DMARX20 : ACR_DMATX20;
257 break;
258 default:
259 pr_debug("hac: invalid depth %d bit\n", params->msbits);
260 return -EINVAL;
261 break;
262 }
263
264 return 0;
265}
266
267#define AC97_RATES \
268 SNDRV_PCM_RATE_8000_192000
269
270#define AC97_FMTS \
271 SNDRV_PCM_FMTBIT_S16_LE
272
273struct snd_soc_cpu_dai sh4_hac_dai[] = {
274{
275 .name = "HAC0",
276 .id = 0,
277 .type = SND_SOC_DAI_AC97,
278 .playback = {
279 .rates = AC97_RATES,
280 .formats = AC97_FMTS,
281 .channels_min = 2,
282 .channels_max = 2,
283 },
284 .capture = {
285 .rates = AC97_RATES,
286 .formats = AC97_FMTS,
287 .channels_min = 2,
288 .channels_max = 2,
289 },
290 .ops = {
291 .hw_params = hac_hw_params,
292 },
293},
294#ifdef CONFIG_CPU_SUBTYPE_SH7760
295{
296 .name = "HAC1",
297 .id = 1,
298 .type = SND_SOC_DAI_AC97,
299 .playback = {
300 .rates = AC97_RATES,
301 .formats = AC97_FMTS,
302 .channels_min = 2,
303 .channels_max = 2,
304 },
305 .capture = {
306 .rates = AC97_RATES,
307 .formats = AC97_FMTS,
308 .channels_min = 2,
309 .channels_max = 2,
310 },
311 .ops = {
312 .hw_params = hac_hw_params,
313 },
314
315},
316#endif
317};
318EXPORT_SYMBOL_GPL(sh4_hac_dai);
319
320MODULE_LICENSE("GPL");
321MODULE_DESCRIPTION("SuperH onchip HAC (AC97) audio driver");
322MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
diff --git a/sound/soc/sh/sh7760-ac97.c b/sound/soc/sh/sh7760-ac97.c
new file mode 100644
index 000000000000..5563f14511fa
--- /dev/null
+++ b/sound/soc/sh/sh7760-ac97.c
@@ -0,0 +1,92 @@
1/*
2 * Generic AC97 sound support for SH7760
3 *
4 * (c) 2007 Manuel Lauss
5 *
6 * Licensed under the GPLv2.
7 */
8
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/platform_device.h>
12#include <sound/driver.h>
13#include <sound/core.h>
14#include <sound/pcm.h>
15#include <sound/soc.h>
16#include <sound/soc-dapm.h>
17#include <asm/io.h>
18
19#include "../codecs/ac97.h"
20
21#define IPSEL 0xFE400034
22
23/* platform specific structs can be declared here */
24extern struct snd_soc_cpu_dai sh4_hac_dai[2];
25extern struct snd_soc_platform sh7760_soc_platform;
26
27static int machine_init(struct snd_soc_codec *codec)
28{
29 snd_soc_dapm_sync_endpoints(codec);
30 return 0;
31}
32
33static struct snd_soc_dai_link sh7760_ac97_dai = {
34 .name = "AC97",
35 .stream_name = "AC97 HiFi",
36 .cpu_dai = &sh4_hac_dai[0], /* HAC0 */
37 .codec_dai = &ac97_dai,
38 .init = machine_init,
39 .ops = NULL,
40};
41
42static struct snd_soc_machine sh7760_ac97_soc_machine = {
43 .name = "SH7760 AC97",
44 .dai_link = &sh7760_ac97_dai,
45 .num_links = 1,
46};
47
48static struct snd_soc_device sh7760_ac97_snd_devdata = {
49 .machine = &sh7760_ac97_soc_machine,
50 .platform = &sh7760_soc_platform,
51 .codec_dev = &soc_codec_dev_ac97,
52};
53
54static struct platform_device *sh7760_ac97_snd_device;
55
56static int __init sh7760_ac97_init(void)
57{
58 int ret;
59 unsigned short ipsel;
60
61 /* enable both AC97 controllers in pinmux reg */
62 ipsel = ctrl_inw(IPSEL);
63 ctrl_outw(ipsel | (3 << 10), IPSEL);
64
65 ret = -ENOMEM;
66 sh7760_ac97_snd_device = platform_device_alloc("soc-audio", -1);
67 if (!sh7760_ac97_snd_device)
68 goto out;
69
70 platform_set_drvdata(sh7760_ac97_snd_device,
71 &sh7760_ac97_snd_devdata);
72 sh7760_ac97_snd_devdata.dev = &sh7760_ac97_snd_device->dev;
73 ret = platform_device_add(sh7760_ac97_snd_device);
74
75 if (ret)
76 platform_device_put(sh7760_ac97_snd_device);
77
78out:
79 return ret;
80}
81
82static void __exit sh7760_ac97_exit(void)
83{
84 platform_device_unregister(sh7760_ac97_snd_device);
85}
86
87module_init(sh7760_ac97_init);
88module_exit(sh7760_ac97_exit);
89
90MODULE_LICENSE("GPL");
91MODULE_DESCRIPTION("Generic SH7760 AC97 sound machine");
92MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
diff --git a/sound/soc/sh/ssi.c b/sound/soc/sh/ssi.c
new file mode 100644
index 000000000000..b72bc316cb8e
--- /dev/null
+++ b/sound/soc/sh/ssi.c
@@ -0,0 +1,400 @@
1/*
2 * Serial Sound Interface (I2S) support for SH7760/SH7780
3 *
4 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
5 *
6 * licensed under the terms outlined in the file COPYING at the root
7 * of the linux kernel sources.
8 *
9 * dont forget to set IPSEL/OMSEL register bits (in your board code) to
10 * enable SSI output pins!
11 */
12
13/*
14 * LIMITATIONS:
15 * The SSI unit has only one physical data line, so full duplex is
16 * impossible. This can be remedied on the SH7760 by using the
17 * other SSI unit for recording; however the SH7780 has only 1 SSI
18 * unit, and its pins are shared with the AC97 unit, among others.
19 *
20 * FEATURES:
21 * The SSI features "compressed mode": in this mode it continuously
22 * streams PCM data over the I2S lines and uses LRCK as a handshake
23 * signal. Can be used to send compressed data (AC3/DTS) to a DSP.
24 * The number of bits sent over the wire in a frame can be adjusted
25 * and can be independent from the actual sample bit depth. This is
26 * useful to support TDM mode codecs like the AD1939 which have a
27 * fixed TDM slot size, regardless of sample resolution.
28 */
29
30#include <linux/init.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
33#include <sound/driver.h>
34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/initval.h>
37#include <sound/soc.h>
38#include <asm/io.h>
39
40#define SSICR 0x00
41#define SSISR 0x04
42
43#define CR_DMAEN (1 << 28)
44#define CR_CHNL_SHIFT 22
45#define CR_CHNL_MASK (3 << CR_CHNL_SHIFT)
46#define CR_DWL_SHIFT 19
47#define CR_DWL_MASK (7 << CR_DWL_SHIFT)
48#define CR_SWL_SHIFT 16
49#define CR_SWL_MASK (7 << CR_SWL_SHIFT)
50#define CR_SCK_MASTER (1 << 15) /* bitclock master bit */
51#define CR_SWS_MASTER (1 << 14) /* wordselect master bit */
52#define CR_SCKP (1 << 13) /* I2Sclock polarity */
53#define CR_SWSP (1 << 12) /* LRCK polarity */
54#define CR_SPDP (1 << 11)
55#define CR_SDTA (1 << 10) /* i2s alignment (msb/lsb) */
56#define CR_PDTA (1 << 9) /* fifo data alignment */
57#define CR_DEL (1 << 8) /* delay data by 1 i2sclk */
58#define CR_BREN (1 << 7) /* clock gating in burst mode */
59#define CR_CKDIV_SHIFT 4
60#define CR_CKDIV_MASK (7 << CR_CKDIV_SHIFT) /* bitclock divider */
61#define CR_MUTE (1 << 3) /* SSI mute */
62#define CR_CPEN (1 << 2) /* compressed mode */
63#define CR_TRMD (1 << 1) /* transmit/receive select */
64#define CR_EN (1 << 0) /* enable SSI */
65
66#define SSIREG(reg) (*(unsigned long *)(ssi->mmio + (reg)))
67
68struct ssi_priv {
69 unsigned long mmio;
70 unsigned long sysclk;
71 int inuse;
72} ssi_cpu_data[] = {
73#if defined(CONFIG_CPU_SUBTYPE_SH7760)
74 {
75 .mmio = 0xFE680000,
76 },
77 {
78 .mmio = 0xFE690000,
79 },
80#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
81 {
82 .mmio = 0xFFE70000,
83 },
84#else
85#error "Unsupported SuperH SoC"
86#endif
87};
88
89/*
90 * track usage of the SSI; it is simplex-only so prevent attempts of
91 * concurrent playback + capture. FIXME: any locking required?
92 */
93static int ssi_startup(struct snd_pcm_substream *substream)
94{
95 struct snd_soc_pcm_runtime *rtd = substream->private_data;
96 struct ssi_priv *ssi = &ssi_cpu_data[rtd->dai->cpu_dai->id];
97 if (ssi->inuse) {
98 pr_debug("ssi: already in use!\n");
99 return -EBUSY;
100 } else
101 ssi->inuse = 1;
102 return 0;
103}
104
105static void ssi_shutdown(struct snd_pcm_substream *substream)
106{
107 struct snd_soc_pcm_runtime *rtd = substream->private_data;
108 struct ssi_priv *ssi = &ssi_cpu_data[rtd->dai->cpu_dai->id];
109
110 ssi->inuse = 0;
111}
112
113static int ssi_trigger(struct snd_pcm_substream *substream, int cmd)
114{
115 struct snd_soc_pcm_runtime *rtd = substream->private_data;
116 struct ssi_priv *ssi = &ssi_cpu_data[rtd->dai->cpu_dai->id];
117
118 switch (cmd) {
119 case SNDRV_PCM_TRIGGER_START:
120 SSIREG(SSICR) |= CR_DMAEN | CR_EN;
121 break;
122 case SNDRV_PCM_TRIGGER_STOP:
123 SSIREG(SSICR) &= ~(CR_DMAEN | CR_EN);
124 break;
125 default:
126 return -EINVAL;
127 }
128
129 return 0;
130}
131
132static int ssi_hw_params(struct snd_pcm_substream *substream,
133 struct snd_pcm_hw_params *params)
134{
135 struct snd_soc_pcm_runtime *rtd = substream->private_data;
136 struct ssi_priv *ssi = &ssi_cpu_data[rtd->dai->cpu_dai->id];
137 unsigned long ssicr = SSIREG(SSICR);
138 unsigned int bits, channels, swl, recv, i;
139
140 channels = params_channels(params);
141 bits = params->msbits;
142 recv = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 0 : 1;
143
144 pr_debug("ssi_hw_params() enter\nssicr was %08lx\n", ssicr);
145 pr_debug("bits: %d channels: %d\n", bits, channels);
146
147 ssicr &= ~(CR_TRMD | CR_CHNL_MASK | CR_DWL_MASK | CR_PDTA |
148 CR_SWL_MASK);
149
150 /* direction (send/receive) */
151 if (!recv)
152 ssicr |= CR_TRMD; /* transmit */
153
154 /* channels */
155 if ((channels < 2) || (channels > 8) || (channels & 1)) {
156 pr_debug("ssi: invalid number of channels\n");
157 return -EINVAL;
158 }
159 ssicr |= ((channels >> 1) - 1) << CR_CHNL_SHIFT;
160
161 /* DATA WORD LENGTH (DWL): databits in audio sample */
162 i = 0;
163 switch (bits) {
164 case 32: ++i;
165 case 24: ++i;
166 case 22: ++i;
167 case 20: ++i;
168 case 18: ++i;
169 case 16: ++i;
170 ssicr |= i << CR_DWL_SHIFT;
171 case 8: break;
172 default:
173 pr_debug("ssi: invalid sample width\n");
174 return -EINVAL;
175 }
176
177 /*
178 * SYSTEM WORD LENGTH: size in bits of half a frame over the I2S
179 * wires. This is usually bits_per_sample x channels/2; i.e. in
180 * Stereo mode the SWL equals DWL. SWL can be bigger than the
181 * product of (channels_per_slot x samplebits), e.g. for codecs
182 * like the AD1939 which only accept 32bit wide TDM slots. For
183 * "standard" I2S operation we set SWL = chans / 2 * DWL here.
184 * Waiting for ASoC to get TDM support ;-)
185 */
186 if ((bits > 16) && (bits <= 24)) {
187 bits = 24; /* these are padded by the SSI */
188 /*ssicr |= CR_PDTA;*/ /* cpu/data endianness ? */
189 }
190 i = 0;
191 swl = (bits * channels) / 2;
192 switch (swl) {
193 case 256: ++i;
194 case 128: ++i;
195 case 64: ++i;
196 case 48: ++i;
197 case 32: ++i;
198 case 16: ++i;
199 ssicr |= i << CR_SWL_SHIFT;
200 case 8: break;
201 default:
202 pr_debug("ssi: invalid system word length computed\n");
203 return -EINVAL;
204 }
205
206 SSIREG(SSICR) = ssicr;
207
208 pr_debug("ssi_hw_params() leave\nssicr is now %08lx\n", ssicr);
209 return 0;
210}
211
212static int ssi_set_sysclk(struct snd_soc_cpu_dai *cpu_dai, int clk_id,
213 unsigned int freq, int dir)
214{
215 struct ssi_priv *ssi = &ssi_cpu_data[cpu_dai->id];
216
217 ssi->sysclk = freq;
218
219 return 0;
220}
221
222/*
223 * This divider is used to generate the SSI_SCK (I2S bitclock) from the
224 * clock at the HAC_BIT_CLK ("oversampling clock") pin.
225 */
226static int ssi_set_clkdiv(struct snd_soc_cpu_dai *dai, int did, int div)
227{
228 struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
229 unsigned long ssicr;
230 int i;
231
232 i = 0;
233 ssicr = SSIREG(SSICR) & ~CR_CKDIV_MASK;
234 switch (div) {
235 case 16: ++i;
236 case 8: ++i;
237 case 4: ++i;
238 case 2: ++i;
239 SSIREG(SSICR) = ssicr | (i << CR_CKDIV_SHIFT);
240 case 1: break;
241 default:
242 pr_debug("ssi: invalid sck divider %d\n", div);
243 return -EINVAL;
244 }
245
246 return 0;
247}
248
249static int ssi_set_fmt(struct snd_soc_cpu_dai *dai, unsigned int fmt)
250{
251 struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
252 unsigned long ssicr = SSIREG(SSICR);
253
254 pr_debug("ssi_set_fmt()\nssicr was 0x%08lx\n", ssicr);
255
256 ssicr &= ~(CR_DEL | CR_PDTA | CR_BREN | CR_SWSP | CR_SCKP |
257 CR_SWS_MASTER | CR_SCK_MASTER);
258
259 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
260 case SND_SOC_DAIFMT_I2S:
261 break;
262 case SND_SOC_DAIFMT_RIGHT_J:
263 ssicr |= CR_DEL | CR_PDTA;
264 break;
265 case SND_SOC_DAIFMT_LEFT_J:
266 ssicr |= CR_DEL;
267 break;
268 default:
269 pr_debug("ssi: unsupported format\n");
270 return -EINVAL;
271 }
272
273 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
274 case SND_SOC_DAIFMT_CONT:
275 break;
276 case SND_SOC_DAIFMT_GATED:
277 ssicr |= CR_BREN;
278 break;
279 }
280
281 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
282 case SND_SOC_DAIFMT_NB_NF:
283 ssicr |= CR_SCKP; /* sample data at low clkedge */
284 break;
285 case SND_SOC_DAIFMT_NB_IF:
286 ssicr |= CR_SCKP | CR_SWSP;
287 break;
288 case SND_SOC_DAIFMT_IB_NF:
289 break;
290 case SND_SOC_DAIFMT_IB_IF:
291 ssicr |= CR_SWSP; /* word select starts low */
292 break;
293 default:
294 pr_debug("ssi: invalid inversion\n");
295 return -EINVAL;
296 }
297
298 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
299 case SND_SOC_DAIFMT_CBM_CFM:
300 break;
301 case SND_SOC_DAIFMT_CBS_CFM:
302 ssicr |= CR_SCK_MASTER;
303 break;
304 case SND_SOC_DAIFMT_CBM_CFS:
305 ssicr |= CR_SWS_MASTER;
306 break;
307 case SND_SOC_DAIFMT_CBS_CFS:
308 ssicr |= CR_SWS_MASTER | CR_SCK_MASTER;
309 break;
310 default:
311 pr_debug("ssi: invalid master/slave configuration\n");
312 return -EINVAL;
313 }
314
315 SSIREG(SSICR) = ssicr;
316 pr_debug("ssi_set_fmt() leave\nssicr is now 0x%08lx\n", ssicr);
317
318 return 0;
319}
320
321/* the SSI depends on an external clocksource (at HAC_BIT_CLK) even in
322 * Master mode, so really this is board specific; the SSI can do any
323 * rate with the right bitclk and divider settings.
324 */
325#define SSI_RATES \
326 SNDRV_PCM_RATE_8000_192000
327
328/* the SSI can do 8-32 bit samples, with 8 possible channels */
329#define SSI_FMTS \
330 (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \
331 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
332 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
333 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_U24_3LE | \
334 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
335
336struct snd_soc_cpu_dai sh4_ssi_dai[] = {
337{
338 .name = "SSI0",
339 .id = 0,
340 .type = SND_SOC_DAI_I2S,
341 .playback = {
342 .rates = SSI_RATES,
343 .formats = SSI_FMTS,
344 .channels_min = 2,
345 .channels_max = 8,
346 },
347 .capture = {
348 .rates = SSI_RATES,
349 .formats = SSI_FMTS,
350 .channels_min = 2,
351 .channels_max = 8,
352 },
353 .ops = {
354 .startup = ssi_startup,
355 .shutdown = ssi_shutdown,
356 .trigger = ssi_trigger,
357 .hw_params = ssi_hw_params,
358 },
359 .dai_ops = {
360 .set_sysclk = ssi_set_sysclk,
361 .set_clkdiv = ssi_set_clkdiv,
362 .set_fmt = ssi_set_fmt,
363 },
364},
365#ifdef CONFIG_CPU_SUBTYPE_SH7760
366{
367 .name = "SSI1",
368 .id = 1,
369 .type = SND_SOC_DAI_I2S,
370 .playback = {
371 .rates = SSI_RATES,
372 .formats = SSI_FMTS,
373 .channels_min = 2,
374 .channels_max = 8,
375 },
376 .capture = {
377 .rates = SSI_RATES,
378 .formats = SSI_FMTS,
379 .channels_min = 2,
380 .channels_max = 8,
381 },
382 .ops = {
383 .startup = ssi_startup,
384 .shutdown = ssi_shutdown,
385 .trigger = ssi_trigger,
386 .hw_params = ssi_hw_params,
387 },
388 .dai_ops = {
389 .set_sysclk = ssi_set_sysclk,
390 .set_clkdiv = ssi_set_clkdiv,
391 .set_fmt = ssi_set_fmt,
392 },
393},
394#endif
395};
396EXPORT_SYMBOL_GPL(sh4_ssi_dai);
397
398MODULE_LICENSE("GPL");
399MODULE_DESCRIPTION("SuperH onchip SSI (I2S) audio driver");
400MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 14:35:19 -0500