diff options
| author | Sangbeom Kim <sbkim73@samsung.com> | 2011-06-20 03:36:18 -0400 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-06-26 07:05:17 -0400 |
| commit | 172a453dcfe7de2f50c5e2d00107a734cf1dccc8 (patch) | |
| tree | 1fac3ef3dcd3840051367f1be8039c1f35882d19 /sound/soc/samsung/i2s.c | |
| parent | d2ec3ababa675ffdd4c8e7272d7dbd4cbdbd12ff (diff) | |
ASoC: SAMSUNG: Move I2S common register definition
I2S registers can be used for control idma.
Previously, register is defined in i2s.c.
For sharing the registers, It is moved to i2s-regs.h
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/samsung/i2s.c')
| -rw-r--r-- | sound/soc/samsung/i2s.c | 104 |
1 files changed, 1 insertions, 103 deletions
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c index 992a732b5211..1568eea31f41 100644 --- a/sound/soc/samsung/i2s.c +++ b/sound/soc/samsung/i2s.c | |||
| @@ -22,109 +22,7 @@ | |||
| 22 | 22 | ||
| 23 | #include "dma.h" | 23 | #include "dma.h" |
| 24 | #include "i2s.h" | 24 | #include "i2s.h" |
| 25 | 25 | #include "i2s-regs.h" | |
| 26 | #define I2SCON 0x0 | ||
| 27 | #define I2SMOD 0x4 | ||
| 28 | #define I2SFIC 0x8 | ||
| 29 | #define I2SPSR 0xc | ||
| 30 | #define I2STXD 0x10 | ||
| 31 | #define I2SRXD 0x14 | ||
| 32 | #define I2SFICS 0x18 | ||
| 33 | #define I2STXDS 0x1c | ||
| 34 | |||
| 35 | #define CON_RSTCLR (1 << 31) | ||
| 36 | #define CON_FRXOFSTATUS (1 << 26) | ||
| 37 | #define CON_FRXORINTEN (1 << 25) | ||
| 38 | #define CON_FTXSURSTAT (1 << 24) | ||
| 39 | #define CON_FTXSURINTEN (1 << 23) | ||
| 40 | #define CON_TXSDMA_PAUSE (1 << 20) | ||
| 41 | #define CON_TXSDMA_ACTIVE (1 << 18) | ||
| 42 | |||
| 43 | #define CON_FTXURSTATUS (1 << 17) | ||
| 44 | #define CON_FTXURINTEN (1 << 16) | ||
| 45 | #define CON_TXFIFO2_EMPTY (1 << 15) | ||
| 46 | #define CON_TXFIFO1_EMPTY (1 << 14) | ||
| 47 | #define CON_TXFIFO2_FULL (1 << 13) | ||
| 48 | #define CON_TXFIFO1_FULL (1 << 12) | ||
| 49 | |||
| 50 | #define CON_LRINDEX (1 << 11) | ||
| 51 | #define CON_TXFIFO_EMPTY (1 << 10) | ||
| 52 | #define CON_RXFIFO_EMPTY (1 << 9) | ||
| 53 | #define CON_TXFIFO_FULL (1 << 8) | ||
| 54 | #define CON_RXFIFO_FULL (1 << 7) | ||
| 55 | #define CON_TXDMA_PAUSE (1 << 6) | ||
| 56 | #define CON_RXDMA_PAUSE (1 << 5) | ||
| 57 | #define CON_TXCH_PAUSE (1 << 4) | ||
| 58 | #define CON_RXCH_PAUSE (1 << 3) | ||
| 59 | #define CON_TXDMA_ACTIVE (1 << 2) | ||
| 60 | #define CON_RXDMA_ACTIVE (1 << 1) | ||
| 61 | #define CON_ACTIVE (1 << 0) | ||
| 62 | |||
| 63 | #define MOD_OPCLK_CDCLK_OUT (0 << 30) | ||
| 64 | #define MOD_OPCLK_CDCLK_IN (1 << 30) | ||
| 65 | #define MOD_OPCLK_BCLK_OUT (2 << 30) | ||
| 66 | #define MOD_OPCLK_PCLK (3 << 30) | ||
| 67 | #define MOD_OPCLK_MASK (3 << 30) | ||
| 68 | #define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */ | ||
| 69 | |||
| 70 | #define MOD_BLCS_SHIFT 26 | ||
| 71 | #define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT) | ||
| 72 | #define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT) | ||
| 73 | #define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT) | ||
| 74 | #define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT) | ||
| 75 | #define MOD_BLCP_SHIFT 24 | ||
| 76 | #define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) | ||
| 77 | #define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) | ||
| 78 | #define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) | ||
| 79 | #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) | ||
| 80 | |||
| 81 | #define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */ | ||
| 82 | #define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */ | ||
| 83 | #define MOD_C1DD_HHALF (1 << 19) | ||
| 84 | #define MOD_C1DD_LHALF (1 << 18) | ||
| 85 | #define MOD_DC2_EN (1 << 17) | ||
| 86 | #define MOD_DC1_EN (1 << 16) | ||
| 87 | #define MOD_BLC_16BIT (0 << 13) | ||
| 88 | #define MOD_BLC_8BIT (1 << 13) | ||
| 89 | #define MOD_BLC_24BIT (2 << 13) | ||
| 90 | #define MOD_BLC_MASK (3 << 13) | ||
| 91 | |||
| 92 | #define MOD_IMS_SYSMUX (1 << 10) | ||
| 93 | #define MOD_SLAVE (1 << 11) | ||
| 94 | #define MOD_TXONLY (0 << 8) | ||
| 95 | #define MOD_RXONLY (1 << 8) | ||
| 96 | #define MOD_TXRX (2 << 8) | ||
| 97 | #define MOD_MASK (3 << 8) | ||
| 98 | #define MOD_LR_LLOW (0 << 7) | ||
| 99 | #define MOD_LR_RLOW (1 << 7) | ||
| 100 | #define MOD_SDF_IIS (0 << 5) | ||
| 101 | #define MOD_SDF_MSB (1 << 5) | ||
| 102 | #define MOD_SDF_LSB (2 << 5) | ||
| 103 | #define MOD_SDF_MASK (3 << 5) | ||
| 104 | #define MOD_RCLK_256FS (0 << 3) | ||
| 105 | #define MOD_RCLK_512FS (1 << 3) | ||
| 106 | #define MOD_RCLK_384FS (2 << 3) | ||
| 107 | #define MOD_RCLK_768FS (3 << 3) | ||
| 108 | #define MOD_RCLK_MASK (3 << 3) | ||
| 109 | #define MOD_BCLK_32FS (0 << 1) | ||
| 110 | #define MOD_BCLK_48FS (1 << 1) | ||
| 111 | #define MOD_BCLK_16FS (2 << 1) | ||
| 112 | #define MOD_BCLK_24FS (3 << 1) | ||
| 113 | #define MOD_BCLK_MASK (3 << 1) | ||
| 114 | #define MOD_8BIT (1 << 0) | ||
| 115 | |||
| 116 | #define MOD_CDCLKCON (1 << 12) | ||
| 117 | |||
| 118 | #define PSR_PSREN (1 << 15) | ||
| 119 | |||
| 120 | #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf) | ||
| 121 | #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf) | ||
| 122 | |||
| 123 | #define FIC_TXFLUSH (1 << 15) | ||
| 124 | #define FIC_RXFLUSH (1 << 7) | ||
| 125 | #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf) | ||
| 126 | #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf) | ||
| 127 | #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f) | ||
| 128 | 26 | ||
| 129 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | 27 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
| 130 | 28 | ||