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authorMark Brown <broonie@opensource.wolfsonmicro.com>2009-04-30 08:21:52 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-04-30 08:30:43 -0400
commitabbc82466967064e4eaafa367fc225a8c803569c (patch)
treef16e399c5df584f615d4733ba0ac7dd07ab0c112 /sound/soc/s3c24xx/s3c-i2s-v2.c
parent38e43c81a07de8ee8a757a9c93dd3a4937dd35e0 (diff)
ASoC: Staticise txctrl and rxctrl for S3C IISv2
They aren't used by anything external and aren't prototyped; if any users appear they can be exported again for them. Also report what modes we have a problem with when we encounter invalid mode configurations. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/s3c24xx/s3c-i2s-v2.c')
-rw-r--r--sound/soc/s3c24xx/s3c-i2s-v2.c20
1 files changed, 12 insertions, 8 deletions
diff --git a/sound/soc/s3c24xx/s3c-i2s-v2.c b/sound/soc/s3c24xx/s3c-i2s-v2.c
index bc4e5044e6ca..972c27684198 100644
--- a/sound/soc/s3c24xx/s3c-i2s-v2.c
+++ b/sound/soc/s3c24xx/s3c-i2s-v2.c
@@ -89,7 +89,7 @@ static inline void dbg_showcon(const char *fn, u32 con)
89 89
90 90
91/* Turn on or off the transmission path. */ 91/* Turn on or off the transmission path. */
92void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on) 92static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
93{ 93{
94 void __iomem *regs = i2s->regs; 94 void __iomem *regs = i2s->regs;
95 u32 fic, con, mod; 95 u32 fic, con, mod;
@@ -119,7 +119,9 @@ void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
119 break; 119 break;
120 120
121 default: 121 default:
122 dev_err(i2s->dev, "TXEN: Invalid MODE in IISMOD\n"); 122 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
123 mod & S3C2412_IISMOD_MODE_MASK);
124 break;
123 } 125 }
124 126
125 writel(con, regs + S3C2412_IISCON); 127 writel(con, regs + S3C2412_IISCON);
@@ -146,7 +148,9 @@ void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
146 break; 148 break;
147 149
148 default: 150 default:
149 dev_err(i2s->dev, "TXDIS: Invalid MODE in IISMOD\n"); 151 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
152 mod & S3C2412_IISMOD_MODE_MASK);
153 break;
150 } 154 }
151 155
152 writel(mod, regs + S3C2412_IISMOD); 156 writel(mod, regs + S3C2412_IISMOD);
@@ -157,9 +161,8 @@ void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
157 dbg_showcon(__func__, con); 161 dbg_showcon(__func__, con);
158 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); 162 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
159} 163}
160EXPORT_SYMBOL_GPL(s3c2412_snd_txctrl);
161 164
162void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on) 165static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
163{ 166{
164 void __iomem *regs = i2s->regs; 167 void __iomem *regs = i2s->regs;
165 u32 fic, con, mod; 168 u32 fic, con, mod;
@@ -189,7 +192,8 @@ void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
189 break; 192 break;
190 193
191 default: 194 default:
192 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n"); 195 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
196 mod & S3C2412_IISMOD_MODE_MASK);
193 } 197 }
194 198
195 writel(mod, regs + S3C2412_IISMOD); 199 writel(mod, regs + S3C2412_IISMOD);
@@ -213,7 +217,8 @@ void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
213 break; 217 break;
214 218
215 default: 219 default:
216 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n"); 220 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
221 mod & S3C2412_IISMOD_MODE_MASK);
217 } 222 }
218 223
219 writel(con, regs + S3C2412_IISCON); 224 writel(con, regs + S3C2412_IISCON);
@@ -223,7 +228,6 @@ void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
223 fic = readl(regs + S3C2412_IISFIC); 228 fic = readl(regs + S3C2412_IISFIC);
224 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); 229 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
225} 230}
226EXPORT_SYMBOL_GPL(s3c2412_snd_rxctrl);
227 231
228/* 232/*
229 * Wait for the LR signal to allow synchronisation to the L/R clock 233 * Wait for the LR signal to allow synchronisation to the L/R clock