diff options
author | Jassi Brar <jassi.brar@samsung.com> | 2010-04-27 02:56:27 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-05-05 10:11:29 -0400 |
commit | ce76f9fd34d4d39fbda330f14b327273551e2f54 (patch) | |
tree | 659dcd028e1ee8cef947fcc2ad82dc8ff0e604bb /sound/soc/s3c24xx/regs-i2s-v2.h | |
parent | b720d56294187ea4167a20e59c4ea0bb4f064132 (diff) |
ASoC: S3C2412: I2S: Debug IMS field
The IMS field of s3c2412/13 is essentially the same as that of s3c64xx.
That is, the IISMOD[11] bit decides Master/Slave mode and IISMOD[10] bit
selects source clock for signal generation.
For that reason, remove improper defines for IISMOD[11:10] field mask
and define two 1bit fields that can be set independent of each other.
As a consequence, corresponding fields for PLAT_S3C64XX too get to use
these new defines.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/s3c24xx/regs-i2s-v2.h')
-rw-r--r-- | sound/soc/s3c24xx/regs-i2s-v2.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/sound/soc/s3c24xx/regs-i2s-v2.h b/sound/soc/s3c24xx/regs-i2s-v2.h index f3d90289e7be..484858a5f33b 100644 --- a/sound/soc/s3c24xx/regs-i2s-v2.h +++ b/sound/soc/s3c24xx/regs-i2s-v2.h | |||
@@ -76,10 +76,8 @@ | |||
76 | #define S3C64XX_IISMOD_IMS_PCLK (0 << 10) | 76 | #define S3C64XX_IISMOD_IMS_PCLK (0 << 10) |
77 | #define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10) | 77 | #define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10) |
78 | 78 | ||
79 | #define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10) | 79 | #define S3C2412_IISMOD_IMS_SYSMUX (1 << 10) |
80 | #define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10) | 80 | #define S3C2412_IISMOD_SLAVE (1 << 11) |
81 | #define S3C2412_IISMOD_SLAVE (2 << 10) | ||
82 | #define S3C2412_IISMOD_MASTER_MASK (3 << 10) | ||
83 | #define S3C2412_IISMOD_MODE_TXONLY (0 << 8) | 81 | #define S3C2412_IISMOD_MODE_TXONLY (0 << 8) |
84 | #define S3C2412_IISMOD_MODE_RXONLY (1 << 8) | 82 | #define S3C2412_IISMOD_MODE_RXONLY (1 << 8) |
85 | #define S3C2412_IISMOD_MODE_TXRX (2 << 8) | 83 | #define S3C2412_IISMOD_MODE_TXRX (2 << 8) |