diff options
author | Peter Ujfalusi <peter.ujfalusi@nokia.com> | 2009-04-15 08:38:56 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-04-16 09:04:10 -0400 |
commit | 3ba191ce051a32b20757f063120496e860ea8f9d (patch) | |
tree | d80b632ae8027d26ed336805e21e96c8759e6550 /sound/soc/omap/omap-mcbsp.c | |
parent | c29b206ffd0700acb2dc1fdb70856cc4b907216c (diff) |
ASoC: OMAP: Add DSP_A mode support for mcbsp
DSP_A mode is similar to the DSP_B, but the MSB is delayed with
one bclk (appears after the FS pulse and not under it).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Jarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/omap/omap-mcbsp.c')
-rw-r--r-- | sound/soc/omap/omap-mcbsp.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index 402a1eb7bd3f..2b4a8da09918 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c | |||
@@ -287,6 +287,7 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, | |||
287 | regs->srgr2 |= FPER(wlen * channels - 1); | 287 | regs->srgr2 |= FPER(wlen * channels - 1); |
288 | regs->srgr1 |= FWID(wlen - 1); | 288 | regs->srgr1 |= FWID(wlen - 1); |
289 | break; | 289 | break; |
290 | case SND_SOC_DAIFMT_DSP_A: | ||
290 | case SND_SOC_DAIFMT_DSP_B: | 291 | case SND_SOC_DAIFMT_DSP_B: |
291 | regs->srgr2 |= FPER(wlen * channels - 1); | 292 | regs->srgr2 |= FPER(wlen * channels - 1); |
292 | regs->srgr1 |= FWID(wlen * channels - 2); | 293 | regs->srgr1 |= FWID(wlen * channels - 2); |
@@ -330,6 +331,13 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
330 | regs->rcr2 |= RDATDLY(1); | 331 | regs->rcr2 |= RDATDLY(1); |
331 | regs->xcr2 |= XDATDLY(1); | 332 | regs->xcr2 |= XDATDLY(1); |
332 | break; | 333 | break; |
334 | case SND_SOC_DAIFMT_DSP_A: | ||
335 | /* 1-bit data delay */ | ||
336 | regs->rcr2 |= RDATDLY(1); | ||
337 | regs->xcr2 |= XDATDLY(1); | ||
338 | /* Invert FS polarity configuration */ | ||
339 | temp_fmt ^= SND_SOC_DAIFMT_NB_IF; | ||
340 | break; | ||
333 | case SND_SOC_DAIFMT_DSP_B: | 341 | case SND_SOC_DAIFMT_DSP_B: |
334 | /* 0-bit data delay */ | 342 | /* 0-bit data delay */ |
335 | regs->rcr2 |= RDATDLY(0); | 343 | regs->rcr2 |= RDATDLY(0); |