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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2012-01-26 05:47:22 -0500
committerLiam Girdwood <lrg@ti.com>2012-03-12 09:34:19 -0400
commit71e822e9dcd80923813705e5843eb39e065e8250 (patch)
tree5ed8f20874100f5495441fd2808139e1f67700c1 /sound/soc/omap/mcbsp.c
parent0210dc4eafcfd1b38ac178ebf63627f359d6371d (diff)
OMAP: mcbsp: Move core driver under sound/soc/omap
In order to consolidate the McBSP driver move it out from arch/arm/plat-omap directory under sound/soc/omap/ Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Grazvydas Ignotas <notasas@gmail.com> Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Acked-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: Liam Girdwood <lrg@ti.com>
Diffstat (limited to 'sound/soc/omap/mcbsp.c')
-rw-r--r--sound/soc/omap/mcbsp.c1364
1 files changed, 1364 insertions, 0 deletions
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
new file mode 100644
index 000000000000..36d83b0c9f02
--- /dev/null
+++ b/sound/soc/omap/mcbsp.c
@@ -0,0 +1,1364 @@
1/*
2 * sound/soc/omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Multichannel mode not supported.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/io.h>
26#include <linux/slab.h>
27
28#include <plat/mcbsp.h>
29#include <linux/pm_runtime.h>
30
31struct omap_mcbsp **mcbsp_ptr;
32int omap_mcbsp_count;
33
34#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
35#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
36
37static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
38{
39 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
40
41 if (mcbsp->pdata->reg_size == 2) {
42 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
43 __raw_writew((u16)val, addr);
44 } else {
45 ((u32 *)mcbsp->reg_cache)[reg] = val;
46 __raw_writel(val, addr);
47 }
48}
49
50static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
51{
52 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
53
54 if (mcbsp->pdata->reg_size == 2) {
55 return !from_cache ? __raw_readw(addr) :
56 ((u16 *)mcbsp->reg_cache)[reg];
57 } else {
58 return !from_cache ? __raw_readl(addr) :
59 ((u32 *)mcbsp->reg_cache)[reg];
60 }
61}
62
63static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
64{
65 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
66}
67
68static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
69{
70 return __raw_readl(mcbsp->st_data->io_base_st + reg);
71}
72
73#define MCBSP_READ(mcbsp, reg) \
74 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
75#define MCBSP_WRITE(mcbsp, reg, val) \
76 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
77#define MCBSP_READ_CACHE(mcbsp, reg) \
78 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
79
80#define MCBSP_ST_READ(mcbsp, reg) \
81 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
82#define MCBSP_ST_WRITE(mcbsp, reg, val) \
83 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
84
85static void omap_mcbsp_dump_reg(u8 id)
86{
87 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
88
89 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
90 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
91 MCBSP_READ(mcbsp, DRR2));
92 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
93 MCBSP_READ(mcbsp, DRR1));
94 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
95 MCBSP_READ(mcbsp, DXR2));
96 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
97 MCBSP_READ(mcbsp, DXR1));
98 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
99 MCBSP_READ(mcbsp, SPCR2));
100 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
101 MCBSP_READ(mcbsp, SPCR1));
102 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
103 MCBSP_READ(mcbsp, RCR2));
104 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
105 MCBSP_READ(mcbsp, RCR1));
106 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
107 MCBSP_READ(mcbsp, XCR2));
108 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
109 MCBSP_READ(mcbsp, XCR1));
110 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
111 MCBSP_READ(mcbsp, SRGR2));
112 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
113 MCBSP_READ(mcbsp, SRGR1));
114 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
115 MCBSP_READ(mcbsp, PCR0));
116 dev_dbg(mcbsp->dev, "***********************\n");
117}
118
119static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
120{
121 struct omap_mcbsp *mcbsp_tx = dev_id;
122 u16 irqst_spcr2;
123
124 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
125 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
126
127 if (irqst_spcr2 & XSYNC_ERR) {
128 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
129 irqst_spcr2);
130 /* Writing zero to XSYNC_ERR clears the IRQ */
131 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
132 }
133
134 return IRQ_HANDLED;
135}
136
137static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
138{
139 struct omap_mcbsp *mcbsp_rx = dev_id;
140 u16 irqst_spcr1;
141
142 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
143 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
144
145 if (irqst_spcr1 & RSYNC_ERR) {
146 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
147 irqst_spcr1);
148 /* Writing zero to RSYNC_ERR clears the IRQ */
149 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
150 }
151
152 return IRQ_HANDLED;
153}
154
155/*
156 * omap_mcbsp_config simply write a config to the
157 * appropriate McBSP.
158 * You either call this function or set the McBSP registers
159 * by yourself before calling omap_mcbsp_start().
160 */
161void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
162{
163 struct omap_mcbsp *mcbsp;
164
165 if (!omap_mcbsp_check_valid_id(id)) {
166 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
167 return;
168 }
169 mcbsp = id_to_mcbsp_ptr(id);
170
171 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
172 mcbsp->id, mcbsp->phys_base);
173
174 /* We write the given config */
175 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
176 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
177 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
178 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
179 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
180 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
181 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
182 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
183 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
184 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
185 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
186 if (mcbsp->pdata->has_ccr) {
187 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
188 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
189 }
190}
191EXPORT_SYMBOL(omap_mcbsp_config);
192
193/**
194 * omap_mcbsp_dma_params - returns the dma channel number
195 * @id - mcbsp id
196 * @stream - indicates the direction of data flow (rx or tx)
197 *
198 * Returns the dma channel number for the rx channel or tx channel
199 * based on the value of @stream for the requested mcbsp given by @id
200 */
201int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
202{
203 struct omap_mcbsp *mcbsp;
204
205 if (!omap_mcbsp_check_valid_id(id)) {
206 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
207 return -ENODEV;
208 }
209 mcbsp = id_to_mcbsp_ptr(id);
210
211 if (stream)
212 return mcbsp->dma_rx_sync;
213 else
214 return mcbsp->dma_tx_sync;
215}
216EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
217
218/**
219 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
220 * @id - mcbsp id
221 * @stream - indicates the direction of data flow (rx or tx)
222 *
223 * Returns the address of mcbsp data transmit register or data receive register
224 * to be used by DMA for transferring/receiving data based on the value of
225 * @stream for the requested mcbsp given by @id
226 */
227int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
228{
229 struct omap_mcbsp *mcbsp;
230 int data_reg;
231
232 if (!omap_mcbsp_check_valid_id(id)) {
233 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
234 return -ENODEV;
235 }
236 mcbsp = id_to_mcbsp_ptr(id);
237
238 if (mcbsp->pdata->reg_size == 2) {
239 if (stream)
240 data_reg = OMAP_MCBSP_REG_DRR1;
241 else
242 data_reg = OMAP_MCBSP_REG_DXR1;
243 } else {
244 if (stream)
245 data_reg = OMAP_MCBSP_REG_DRR;
246 else
247 data_reg = OMAP_MCBSP_REG_DXR;
248 }
249
250 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
251}
252EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
253
254static void omap_st_on(struct omap_mcbsp *mcbsp)
255{
256 unsigned int w;
257
258 if (mcbsp->pdata->enable_st_clock)
259 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
260
261 /* Enable McBSP Sidetone */
262 w = MCBSP_READ(mcbsp, SSELCR);
263 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
264
265 /* Enable Sidetone from Sidetone Core */
266 w = MCBSP_ST_READ(mcbsp, SSELCR);
267 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
268}
269
270static void omap_st_off(struct omap_mcbsp *mcbsp)
271{
272 unsigned int w;
273
274 w = MCBSP_ST_READ(mcbsp, SSELCR);
275 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
276
277 w = MCBSP_READ(mcbsp, SSELCR);
278 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
279
280 if (mcbsp->pdata->enable_st_clock)
281 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
282}
283
284static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
285{
286 u16 val, i;
287
288 val = MCBSP_ST_READ(mcbsp, SSELCR);
289
290 if (val & ST_COEFFWREN)
291 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
292
293 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
294
295 for (i = 0; i < 128; i++)
296 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
297
298 i = 0;
299
300 val = MCBSP_ST_READ(mcbsp, SSELCR);
301 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
302 val = MCBSP_ST_READ(mcbsp, SSELCR);
303
304 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
305
306 if (i == 1000)
307 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
308}
309
310static void omap_st_chgain(struct omap_mcbsp *mcbsp)
311{
312 u16 w;
313 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
314
315 w = MCBSP_ST_READ(mcbsp, SSELCR);
316
317 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
318 ST_CH1GAIN(st_data->ch1gain));
319}
320
321int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
322{
323 struct omap_mcbsp *mcbsp;
324 struct omap_mcbsp_st_data *st_data;
325 int ret = 0;
326
327 if (!omap_mcbsp_check_valid_id(id)) {
328 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
329 return -ENODEV;
330 }
331
332 mcbsp = id_to_mcbsp_ptr(id);
333 st_data = mcbsp->st_data;
334
335 if (!st_data)
336 return -ENOENT;
337
338 spin_lock_irq(&mcbsp->lock);
339 if (channel == 0)
340 st_data->ch0gain = chgain;
341 else if (channel == 1)
342 st_data->ch1gain = chgain;
343 else
344 ret = -EINVAL;
345
346 if (st_data->enabled)
347 omap_st_chgain(mcbsp);
348 spin_unlock_irq(&mcbsp->lock);
349
350 return ret;
351}
352EXPORT_SYMBOL(omap_st_set_chgain);
353
354int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
355{
356 struct omap_mcbsp *mcbsp;
357 struct omap_mcbsp_st_data *st_data;
358 int ret = 0;
359
360 if (!omap_mcbsp_check_valid_id(id)) {
361 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
362 return -ENODEV;
363 }
364
365 mcbsp = id_to_mcbsp_ptr(id);
366 st_data = mcbsp->st_data;
367
368 if (!st_data)
369 return -ENOENT;
370
371 spin_lock_irq(&mcbsp->lock);
372 if (channel == 0)
373 *chgain = st_data->ch0gain;
374 else if (channel == 1)
375 *chgain = st_data->ch1gain;
376 else
377 ret = -EINVAL;
378 spin_unlock_irq(&mcbsp->lock);
379
380 return ret;
381}
382EXPORT_SYMBOL(omap_st_get_chgain);
383
384static int omap_st_start(struct omap_mcbsp *mcbsp)
385{
386 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
387
388 if (st_data && st_data->enabled && !st_data->running) {
389 omap_st_fir_write(mcbsp, st_data->taps);
390 omap_st_chgain(mcbsp);
391
392 if (!mcbsp->free) {
393 omap_st_on(mcbsp);
394 st_data->running = 1;
395 }
396 }
397
398 return 0;
399}
400
401int omap_st_enable(unsigned int id)
402{
403 struct omap_mcbsp *mcbsp;
404 struct omap_mcbsp_st_data *st_data;
405
406 if (!omap_mcbsp_check_valid_id(id)) {
407 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
408 return -ENODEV;
409 }
410
411 mcbsp = id_to_mcbsp_ptr(id);
412 st_data = mcbsp->st_data;
413
414 if (!st_data)
415 return -ENODEV;
416
417 spin_lock_irq(&mcbsp->lock);
418 st_data->enabled = 1;
419 omap_st_start(mcbsp);
420 spin_unlock_irq(&mcbsp->lock);
421
422 return 0;
423}
424EXPORT_SYMBOL(omap_st_enable);
425
426static int omap_st_stop(struct omap_mcbsp *mcbsp)
427{
428 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
429
430 if (st_data && st_data->running) {
431 if (!mcbsp->free) {
432 omap_st_off(mcbsp);
433 st_data->running = 0;
434 }
435 }
436
437 return 0;
438}
439
440int omap_st_disable(unsigned int id)
441{
442 struct omap_mcbsp *mcbsp;
443 struct omap_mcbsp_st_data *st_data;
444 int ret = 0;
445
446 if (!omap_mcbsp_check_valid_id(id)) {
447 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
448 return -ENODEV;
449 }
450
451 mcbsp = id_to_mcbsp_ptr(id);
452 st_data = mcbsp->st_data;
453
454 if (!st_data)
455 return -ENODEV;
456
457 spin_lock_irq(&mcbsp->lock);
458 omap_st_stop(mcbsp);
459 st_data->enabled = 0;
460 spin_unlock_irq(&mcbsp->lock);
461
462 return ret;
463}
464EXPORT_SYMBOL(omap_st_disable);
465
466int omap_st_is_enabled(unsigned int id)
467{
468 struct omap_mcbsp *mcbsp;
469 struct omap_mcbsp_st_data *st_data;
470
471 if (!omap_mcbsp_check_valid_id(id)) {
472 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
473 return -ENODEV;
474 }
475
476 mcbsp = id_to_mcbsp_ptr(id);
477 st_data = mcbsp->st_data;
478
479 if (!st_data)
480 return -ENODEV;
481
482
483 return st_data->enabled;
484}
485EXPORT_SYMBOL(omap_st_is_enabled);
486
487/*
488 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
489 * The threshold parameter is 1 based, and it is converted (threshold - 1)
490 * for the THRSH2 register.
491 */
492void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
493{
494 struct omap_mcbsp *mcbsp;
495
496 if (!omap_mcbsp_check_valid_id(id)) {
497 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
498 return;
499 }
500 mcbsp = id_to_mcbsp_ptr(id);
501 if (mcbsp->pdata->buffer_size == 0)
502 return;
503
504 if (threshold && threshold <= mcbsp->max_tx_thres)
505 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
506}
507EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
508
509/*
510 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
511 * The threshold parameter is 1 based, and it is converted (threshold - 1)
512 * for the THRSH1 register.
513 */
514void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
515{
516 struct omap_mcbsp *mcbsp;
517
518 if (!omap_mcbsp_check_valid_id(id)) {
519 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
520 return;
521 }
522 mcbsp = id_to_mcbsp_ptr(id);
523 if (mcbsp->pdata->buffer_size == 0)
524 return;
525
526 if (threshold && threshold <= mcbsp->max_rx_thres)
527 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
528}
529EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
530
531/*
532 * omap_mcbsp_get_max_tx_thres just return the current configured
533 * maximum threshold for transmission
534 */
535u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
536{
537 struct omap_mcbsp *mcbsp;
538
539 if (!omap_mcbsp_check_valid_id(id)) {
540 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
541 return -ENODEV;
542 }
543 mcbsp = id_to_mcbsp_ptr(id);
544
545 return mcbsp->max_tx_thres;
546}
547EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
548
549/*
550 * omap_mcbsp_get_max_rx_thres just return the current configured
551 * maximum threshold for reception
552 */
553u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
554{
555 struct omap_mcbsp *mcbsp;
556
557 if (!omap_mcbsp_check_valid_id(id)) {
558 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
559 return -ENODEV;
560 }
561 mcbsp = id_to_mcbsp_ptr(id);
562
563 return mcbsp->max_rx_thres;
564}
565EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
566
567u16 omap_mcbsp_get_fifo_size(unsigned int id)
568{
569 struct omap_mcbsp *mcbsp;
570
571 if (!omap_mcbsp_check_valid_id(id)) {
572 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
573 return -ENODEV;
574 }
575 mcbsp = id_to_mcbsp_ptr(id);
576
577 return mcbsp->pdata->buffer_size;
578}
579EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
580
581/*
582 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
583 */
584u16 omap_mcbsp_get_tx_delay(unsigned int id)
585{
586 struct omap_mcbsp *mcbsp;
587 u16 buffstat;
588
589 if (!omap_mcbsp_check_valid_id(id)) {
590 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
591 return -ENODEV;
592 }
593 mcbsp = id_to_mcbsp_ptr(id);
594 if (mcbsp->pdata->buffer_size == 0)
595 return 0;
596
597 /* Returns the number of free locations in the buffer */
598 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
599
600 /* Number of slots are different in McBSP ports */
601 return mcbsp->pdata->buffer_size - buffstat;
602}
603EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
604
605/*
606 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
607 * to reach the threshold value (when the DMA will be triggered to read it)
608 */
609u16 omap_mcbsp_get_rx_delay(unsigned int id)
610{
611 struct omap_mcbsp *mcbsp;
612 u16 buffstat, threshold;
613
614 if (!omap_mcbsp_check_valid_id(id)) {
615 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
616 return -ENODEV;
617 }
618 mcbsp = id_to_mcbsp_ptr(id);
619 if (mcbsp->pdata->buffer_size == 0)
620 return 0;
621
622 /* Returns the number of used locations in the buffer */
623 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
624 /* RX threshold */
625 threshold = MCBSP_READ(mcbsp, THRSH1);
626
627 /* Return the number of location till we reach the threshold limit */
628 if (threshold <= buffstat)
629 return 0;
630 else
631 return threshold - buffstat;
632}
633EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
634
635/*
636 * omap_mcbsp_get_dma_op_mode just return the current configured
637 * operating mode for the mcbsp channel
638 */
639int omap_mcbsp_get_dma_op_mode(unsigned int id)
640{
641 struct omap_mcbsp *mcbsp;
642 int dma_op_mode;
643
644 if (!omap_mcbsp_check_valid_id(id)) {
645 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
646 return -ENODEV;
647 }
648 mcbsp = id_to_mcbsp_ptr(id);
649
650 dma_op_mode = mcbsp->dma_op_mode;
651
652 return dma_op_mode;
653}
654EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
655
656int omap_mcbsp_request(unsigned int id)
657{
658 struct omap_mcbsp *mcbsp;
659 void *reg_cache;
660 int err;
661
662 if (!omap_mcbsp_check_valid_id(id)) {
663 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
664 return -ENODEV;
665 }
666 mcbsp = id_to_mcbsp_ptr(id);
667
668 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
669 if (!reg_cache) {
670 return -ENOMEM;
671 }
672
673 spin_lock(&mcbsp->lock);
674 if (!mcbsp->free) {
675 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
676 mcbsp->id);
677 err = -EBUSY;
678 goto err_kfree;
679 }
680
681 mcbsp->free = false;
682 mcbsp->reg_cache = reg_cache;
683 spin_unlock(&mcbsp->lock);
684
685 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
686 mcbsp->pdata->ops->request(id);
687
688 pm_runtime_get_sync(mcbsp->dev);
689
690 /* Enable wakeup behavior */
691 if (mcbsp->pdata->has_wakeup)
692 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
693
694 /*
695 * Make sure that transmitter, receiver and sample-rate generator are
696 * not running before activating IRQs.
697 */
698 MCBSP_WRITE(mcbsp, SPCR1, 0);
699 MCBSP_WRITE(mcbsp, SPCR2, 0);
700
701 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
702 0, "McBSP", (void *)mcbsp);
703 if (err != 0) {
704 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
705 "for McBSP%d\n", mcbsp->tx_irq,
706 mcbsp->id);
707 goto err_clk_disable;
708 }
709
710 if (mcbsp->rx_irq) {
711 err = request_irq(mcbsp->rx_irq,
712 omap_mcbsp_rx_irq_handler,
713 0, "McBSP", (void *)mcbsp);
714 if (err != 0) {
715 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
716 "for McBSP%d\n", mcbsp->rx_irq,
717 mcbsp->id);
718 goto err_free_irq;
719 }
720 }
721
722 return 0;
723err_free_irq:
724 free_irq(mcbsp->tx_irq, (void *)mcbsp);
725err_clk_disable:
726 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
727 mcbsp->pdata->ops->free(id);
728
729 /* Disable wakeup behavior */
730 if (mcbsp->pdata->has_wakeup)
731 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
732
733 pm_runtime_put_sync(mcbsp->dev);
734
735 spin_lock(&mcbsp->lock);
736 mcbsp->free = true;
737 mcbsp->reg_cache = NULL;
738err_kfree:
739 spin_unlock(&mcbsp->lock);
740 kfree(reg_cache);
741
742 return err;
743}
744EXPORT_SYMBOL(omap_mcbsp_request);
745
746void omap_mcbsp_free(unsigned int id)
747{
748 struct omap_mcbsp *mcbsp;
749 void *reg_cache;
750
751 if (!omap_mcbsp_check_valid_id(id)) {
752 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
753 return;
754 }
755 mcbsp = id_to_mcbsp_ptr(id);
756
757 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
758 mcbsp->pdata->ops->free(id);
759
760 /* Disable wakeup behavior */
761 if (mcbsp->pdata->has_wakeup)
762 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
763
764 pm_runtime_put_sync(mcbsp->dev);
765
766 if (mcbsp->rx_irq)
767 free_irq(mcbsp->rx_irq, (void *)mcbsp);
768 free_irq(mcbsp->tx_irq, (void *)mcbsp);
769
770 reg_cache = mcbsp->reg_cache;
771
772 spin_lock(&mcbsp->lock);
773 if (mcbsp->free)
774 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
775 else
776 mcbsp->free = true;
777 mcbsp->reg_cache = NULL;
778 spin_unlock(&mcbsp->lock);
779
780 if (reg_cache)
781 kfree(reg_cache);
782}
783EXPORT_SYMBOL(omap_mcbsp_free);
784
785/*
786 * Here we start the McBSP, by enabling transmitter, receiver or both.
787 * If no transmitter or receiver is active prior calling, then sample-rate
788 * generator and frame sync are started.
789 */
790void omap_mcbsp_start(unsigned int id, int tx, int rx)
791{
792 struct omap_mcbsp *mcbsp;
793 int enable_srg = 0;
794 u16 w;
795
796 if (!omap_mcbsp_check_valid_id(id)) {
797 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
798 return;
799 }
800 mcbsp = id_to_mcbsp_ptr(id);
801
802 if (mcbsp->st_data)
803 omap_st_start(mcbsp);
804
805 /* Only enable SRG, if McBSP is master */
806 w = MCBSP_READ_CACHE(mcbsp, PCR0);
807 if (w & (FSXM | FSRM | CLKXM | CLKRM))
808 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
809 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
810
811 if (enable_srg) {
812 /* Start the sample generator */
813 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
814 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
815 }
816
817 /* Enable transmitter and receiver */
818 tx &= 1;
819 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
820 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
821
822 rx &= 1;
823 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
824 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
825
826 /*
827 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
828 * REVISIT: 100us may give enough time for two CLKSRG, however
829 * due to some unknown PM related, clock gating etc. reason it
830 * is now at 500us.
831 */
832 udelay(500);
833
834 if (enable_srg) {
835 /* Start frame sync */
836 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
837 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
838 }
839
840 if (mcbsp->pdata->has_ccr) {
841 /* Release the transmitter and receiver */
842 w = MCBSP_READ_CACHE(mcbsp, XCCR);
843 w &= ~(tx ? XDISABLE : 0);
844 MCBSP_WRITE(mcbsp, XCCR, w);
845 w = MCBSP_READ_CACHE(mcbsp, RCCR);
846 w &= ~(rx ? RDISABLE : 0);
847 MCBSP_WRITE(mcbsp, RCCR, w);
848 }
849
850 /* Dump McBSP Regs */
851 omap_mcbsp_dump_reg(id);
852}
853EXPORT_SYMBOL(omap_mcbsp_start);
854
855void omap_mcbsp_stop(unsigned int id, int tx, int rx)
856{
857 struct omap_mcbsp *mcbsp;
858 int idle;
859 u16 w;
860
861 if (!omap_mcbsp_check_valid_id(id)) {
862 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
863 return;
864 }
865
866 mcbsp = id_to_mcbsp_ptr(id);
867
868 /* Reset transmitter */
869 tx &= 1;
870 if (mcbsp->pdata->has_ccr) {
871 w = MCBSP_READ_CACHE(mcbsp, XCCR);
872 w |= (tx ? XDISABLE : 0);
873 MCBSP_WRITE(mcbsp, XCCR, w);
874 }
875 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
876 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
877
878 /* Reset receiver */
879 rx &= 1;
880 if (mcbsp->pdata->has_ccr) {
881 w = MCBSP_READ_CACHE(mcbsp, RCCR);
882 w |= (rx ? RDISABLE : 0);
883 MCBSP_WRITE(mcbsp, RCCR, w);
884 }
885 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
886 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
887
888 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
889 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
890
891 if (idle) {
892 /* Reset the sample rate generator */
893 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
894 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
895 }
896
897 if (mcbsp->st_data)
898 omap_st_stop(mcbsp);
899}
900EXPORT_SYMBOL(omap_mcbsp_stop);
901
902int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
903{
904 struct omap_mcbsp *mcbsp;
905 const char *src;
906
907 if (!omap_mcbsp_check_valid_id(id)) {
908 pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
909 return -EINVAL;
910 }
911 mcbsp = id_to_mcbsp_ptr(id);
912
913 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
914 src = "clks_ext";
915 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
916 src = "clks_fclk";
917 else
918 return -EINVAL;
919
920 if (mcbsp->pdata->set_clk_src)
921 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
922 else
923 return -EINVAL;
924}
925EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
926
927void omap2_mcbsp1_mux_clkr_src(u8 mux)
928{
929 struct omap_mcbsp *mcbsp;
930 const char *src;
931
932 if (mux == CLKR_SRC_CLKR)
933 src = "clkr";
934 else if (mux == CLKR_SRC_CLKX)
935 src = "clkx";
936 else
937 return;
938
939 mcbsp = id_to_mcbsp_ptr(0);
940 if (mcbsp->pdata->mux_signal)
941 mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
942}
943EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
944
945void omap2_mcbsp1_mux_fsr_src(u8 mux)
946{
947 struct omap_mcbsp *mcbsp;
948 const char *src;
949
950 if (mux == FSR_SRC_FSR)
951 src = "fsr";
952 else if (mux == FSR_SRC_FSX)
953 src = "fsx";
954 else
955 return;
956
957 mcbsp = id_to_mcbsp_ptr(0);
958 if (mcbsp->pdata->mux_signal)
959 mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
960}
961EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
962
963#define max_thres(m) (mcbsp->pdata->buffer_size)
964#define valid_threshold(m, val) ((val) <= max_thres(m))
965#define THRESHOLD_PROP_BUILDER(prop) \
966static ssize_t prop##_show(struct device *dev, \
967 struct device_attribute *attr, char *buf) \
968{ \
969 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
970 \
971 return sprintf(buf, "%u\n", mcbsp->prop); \
972} \
973 \
974static ssize_t prop##_store(struct device *dev, \
975 struct device_attribute *attr, \
976 const char *buf, size_t size) \
977{ \
978 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
979 unsigned long val; \
980 int status; \
981 \
982 status = strict_strtoul(buf, 0, &val); \
983 if (status) \
984 return status; \
985 \
986 if (!valid_threshold(mcbsp, val)) \
987 return -EDOM; \
988 \
989 mcbsp->prop = val; \
990 return size; \
991} \
992 \
993static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
994
995THRESHOLD_PROP_BUILDER(max_tx_thres);
996THRESHOLD_PROP_BUILDER(max_rx_thres);
997
998static const char *dma_op_modes[] = {
999 "element", "threshold", "frame",
1000};
1001
1002static ssize_t dma_op_mode_show(struct device *dev,
1003 struct device_attribute *attr, char *buf)
1004{
1005 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1006 int dma_op_mode, i = 0;
1007 ssize_t len = 0;
1008 const char * const *s;
1009
1010 dma_op_mode = mcbsp->dma_op_mode;
1011
1012 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1013 if (dma_op_mode == i)
1014 len += sprintf(buf + len, "[%s] ", *s);
1015 else
1016 len += sprintf(buf + len, "%s ", *s);
1017 }
1018 len += sprintf(buf + len, "\n");
1019
1020 return len;
1021}
1022
1023static ssize_t dma_op_mode_store(struct device *dev,
1024 struct device_attribute *attr,
1025 const char *buf, size_t size)
1026{
1027 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1028 const char * const *s;
1029 int i = 0;
1030
1031 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1032 if (sysfs_streq(buf, *s))
1033 break;
1034
1035 if (i == ARRAY_SIZE(dma_op_modes))
1036 return -EINVAL;
1037
1038 spin_lock_irq(&mcbsp->lock);
1039 if (!mcbsp->free) {
1040 size = -EBUSY;
1041 goto unlock;
1042 }
1043 mcbsp->dma_op_mode = i;
1044
1045unlock:
1046 spin_unlock_irq(&mcbsp->lock);
1047
1048 return size;
1049}
1050
1051static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1052
1053static const struct attribute *additional_attrs[] = {
1054 &dev_attr_max_tx_thres.attr,
1055 &dev_attr_max_rx_thres.attr,
1056 &dev_attr_dma_op_mode.attr,
1057 NULL,
1058};
1059
1060static const struct attribute_group additional_attr_group = {
1061 .attrs = (struct attribute **)additional_attrs,
1062};
1063
1064static ssize_t st_taps_show(struct device *dev,
1065 struct device_attribute *attr, char *buf)
1066{
1067 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1068 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1069 ssize_t status = 0;
1070 int i;
1071
1072 spin_lock_irq(&mcbsp->lock);
1073 for (i = 0; i < st_data->nr_taps; i++)
1074 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1075 st_data->taps[i]);
1076 if (i)
1077 status += sprintf(&buf[status], "\n");
1078 spin_unlock_irq(&mcbsp->lock);
1079
1080 return status;
1081}
1082
1083static ssize_t st_taps_store(struct device *dev,
1084 struct device_attribute *attr,
1085 const char *buf, size_t size)
1086{
1087 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1088 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1089 int val, tmp, status, i = 0;
1090
1091 spin_lock_irq(&mcbsp->lock);
1092 memset(st_data->taps, 0, sizeof(st_data->taps));
1093 st_data->nr_taps = 0;
1094
1095 do {
1096 status = sscanf(buf, "%d%n", &val, &tmp);
1097 if (status < 0 || status == 0) {
1098 size = -EINVAL;
1099 goto out;
1100 }
1101 if (val < -32768 || val > 32767) {
1102 size = -EINVAL;
1103 goto out;
1104 }
1105 st_data->taps[i++] = val;
1106 buf += tmp;
1107 if (*buf != ',')
1108 break;
1109 buf++;
1110 } while (1);
1111
1112 st_data->nr_taps = i;
1113
1114out:
1115 spin_unlock_irq(&mcbsp->lock);
1116
1117 return size;
1118}
1119
1120static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1121
1122static const struct attribute *sidetone_attrs[] = {
1123 &dev_attr_st_taps.attr,
1124 NULL,
1125};
1126
1127static const struct attribute_group sidetone_attr_group = {
1128 .attrs = (struct attribute **)sidetone_attrs,
1129};
1130
1131static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
1132 struct resource *res)
1133{
1134 struct omap_mcbsp_st_data *st_data;
1135 int err;
1136
1137 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1138 if (!st_data) {
1139 err = -ENOMEM;
1140 goto err1;
1141 }
1142
1143 st_data->io_base_st = ioremap(res->start, resource_size(res));
1144 if (!st_data->io_base_st) {
1145 err = -ENOMEM;
1146 goto err2;
1147 }
1148
1149 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1150 if (err)
1151 goto err3;
1152
1153 mcbsp->st_data = st_data;
1154 return 0;
1155
1156err3:
1157 iounmap(st_data->io_base_st);
1158err2:
1159 kfree(st_data);
1160err1:
1161 return err;
1162
1163}
1164
1165static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1166{
1167 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1168
1169 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1170 iounmap(st_data->io_base_st);
1171 kfree(st_data);
1172}
1173
1174/*
1175 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1176 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1177 */
1178static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1179{
1180 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1181 struct omap_mcbsp *mcbsp;
1182 int id = pdev->id - 1;
1183 struct resource *res;
1184 int ret = 0;
1185
1186 if (!pdata) {
1187 dev_err(&pdev->dev, "McBSP device initialized without"
1188 "platform data\n");
1189 ret = -EINVAL;
1190 goto exit;
1191 }
1192
1193 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1194
1195 if (id >= omap_mcbsp_count) {
1196 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1197 ret = -EINVAL;
1198 goto exit;
1199 }
1200
1201 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1202 if (!mcbsp) {
1203 ret = -ENOMEM;
1204 goto exit;
1205 }
1206
1207 spin_lock_init(&mcbsp->lock);
1208 mcbsp->id = id + 1;
1209 mcbsp->free = true;
1210
1211 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1212 if (!res) {
1213 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1214 if (!res) {
1215 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1216 "resource\n", __func__, pdev->id);
1217 ret = -ENOMEM;
1218 goto exit;
1219 }
1220 }
1221 mcbsp->phys_base = res->start;
1222 mcbsp->reg_cache_size = resource_size(res);
1223 mcbsp->io_base = ioremap(res->start, resource_size(res));
1224 if (!mcbsp->io_base) {
1225 ret = -ENOMEM;
1226 goto err_ioremap;
1227 }
1228
1229 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1230 if (!res)
1231 mcbsp->phys_dma_base = mcbsp->phys_base;
1232 else
1233 mcbsp->phys_dma_base = res->start;
1234
1235 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1236 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1237
1238 /* From OMAP4 there will be a single irq line */
1239 if (mcbsp->tx_irq == -ENXIO)
1240 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1241
1242 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1243 if (!res) {
1244 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1245 __func__, pdev->id);
1246 ret = -ENODEV;
1247 goto err_res;
1248 }
1249 mcbsp->dma_rx_sync = res->start;
1250
1251 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1252 if (!res) {
1253 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1254 __func__, pdev->id);
1255 ret = -ENODEV;
1256 goto err_res;
1257 }
1258 mcbsp->dma_tx_sync = res->start;
1259
1260 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1261 if (IS_ERR(mcbsp->fclk)) {
1262 ret = PTR_ERR(mcbsp->fclk);
1263 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1264 goto err_res;
1265 }
1266
1267 mcbsp->pdata = pdata;
1268 mcbsp->dev = &pdev->dev;
1269 mcbsp_ptr[id] = mcbsp;
1270 platform_set_drvdata(pdev, mcbsp);
1271 pm_runtime_enable(mcbsp->dev);
1272
1273 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1274 if (mcbsp->pdata->buffer_size) {
1275 /*
1276 * Initially configure the maximum thresholds to a safe value.
1277 * The McBSP FIFO usage with these values should not go under
1278 * 16 locations.
1279 * If the whole FIFO without safety buffer is used, than there
1280 * is a possibility that the DMA will be not able to push the
1281 * new data on time, causing channel shifts in runtime.
1282 */
1283 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1284 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1285
1286 ret = sysfs_create_group(&mcbsp->dev->kobj,
1287 &additional_attr_group);
1288 if (ret) {
1289 dev_err(mcbsp->dev,
1290 "Unable to create additional controls\n");
1291 goto err_thres;
1292 }
1293 } else {
1294 mcbsp->max_tx_thres = -EINVAL;
1295 mcbsp->max_rx_thres = -EINVAL;
1296 }
1297
1298 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1299 if (res) {
1300 ret = omap_st_add(mcbsp, res);
1301 if (ret) {
1302 dev_err(mcbsp->dev,
1303 "Unable to create sidetone controls\n");
1304 goto err_st;
1305 }
1306 }
1307
1308 return 0;
1309
1310err_st:
1311 if (mcbsp->pdata->buffer_size)
1312 sysfs_remove_group(&mcbsp->dev->kobj,
1313 &additional_attr_group);
1314err_thres:
1315 clk_put(mcbsp->fclk);
1316err_res:
1317 iounmap(mcbsp->io_base);
1318err_ioremap:
1319 kfree(mcbsp);
1320exit:
1321 return ret;
1322}
1323
1324static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1325{
1326 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1327
1328 platform_set_drvdata(pdev, NULL);
1329 if (mcbsp) {
1330
1331 if (mcbsp->pdata && mcbsp->pdata->ops &&
1332 mcbsp->pdata->ops->free)
1333 mcbsp->pdata->ops->free(mcbsp->id);
1334
1335 if (mcbsp->pdata->buffer_size)
1336 sysfs_remove_group(&mcbsp->dev->kobj,
1337 &additional_attr_group);
1338
1339 if (mcbsp->st_data)
1340 omap_st_remove(mcbsp);
1341
1342 clk_put(mcbsp->fclk);
1343
1344 iounmap(mcbsp->io_base);
1345 kfree(mcbsp);
1346 }
1347
1348 return 0;
1349}
1350
1351static struct platform_driver omap_mcbsp_driver = {
1352 .probe = omap_mcbsp_probe,
1353 .remove = __devexit_p(omap_mcbsp_remove),
1354 .driver = {
1355 .name = "omap-mcbsp",
1356 },
1357};
1358
1359module_platform_driver(omap_mcbsp_driver);
1360
1361MODULE_AUTHOR("Samuel Ortiz <samuel.ortiz@nokia.com>");
1362MODULE_DESCRIPTION("OMAP McBSP core driver");
1363MODULE_LICENSE("GPL");
1364MODULE_ALIAS("platform:omap-mcbsp");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 21:22:17 -0500