aboutsummaryrefslogtreecommitdiffstats
path: root/sound/soc/mxs
diff options
context:
space:
mode:
authorFabio Estevam <fabio.estevam@freescale.com>2012-11-01 13:57:11 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-11-02 11:03:06 -0400
commitf55f14752ecaccf7d6a52fd13929b73fcb191f19 (patch)
tree8b220c507ad69ff7b26eb0b95c3c1fa8f4b766b9 /sound/soc/mxs
parent9f4c3f1cde541d477633479a0203ef8a834ee5f9 (diff)
ASoC: mxs-saif: Fix channel swap for 24-bit format
Playing 24-bit format file leads to channel swap on mx28 and the reason is that the current driver performs one write/read to/from the SAIF_DATA register to trigger the transfer. This approach works fine for S16_LE case because SAIF_DATA is a 32-bit register and thus is capable of storing the 16-bit left and right channels, but for the S24_LE case it can only store one channel, so in order to not lose the FIFO sync an extra read/write is needed. Reported-by: Dan Winner <DWinner@tc-helicon.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Dan Winner <DWinner@tc-helicon.com> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/mxs')
-rw-r--r--sound/soc/mxs/mxs-saif.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
index 93380cc7cf97..c294fbb523fc 100644
--- a/sound/soc/mxs/mxs-saif.c
+++ b/sound/soc/mxs/mxs-saif.c
@@ -523,16 +523,24 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
523 523
524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
525 /* 525 /*
526 * write a data to saif data register to trigger 526 * write data to saif data register to trigger
527 * the transfer 527 * the transfer.
528 * For 24-bit format the 32-bit FIFO register stores
529 * only one channel, so we need to write twice.
530 * This is also safe for the other non 24-bit formats.
528 */ 531 */
529 __raw_writel(0, saif->base + SAIF_DATA); 532 __raw_writel(0, saif->base + SAIF_DATA);
533 __raw_writel(0, saif->base + SAIF_DATA);
530 } else { 534 } else {
531 /* 535 /*
532 * read a data from saif data register to trigger 536 * read data from saif data register to trigger
533 * the receive 537 * the receive.
538 * For 24-bit format the 32-bit FIFO register stores
539 * only one channel, so we need to read twice.
540 * This is also safe for the other non 24-bit formats.
534 */ 541 */
535 __raw_readl(saif->base + SAIF_DATA); 542 __raw_readl(saif->base + SAIF_DATA);
543 __raw_readl(saif->base + SAIF_DATA);
536 } 544 }
537 545
538 master_saif->ongoing = 1; 546 master_saif->ongoing = 1;