ASoC: fsl-esai: big-endian support

For most platforms, the CPU and ESAI device is in the same endianess
mode. While for the LS1 platform, the CPU is in LE mode and the ESAI
is in BE mode.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

1 files changed, 4 insertions, 1 deletions

diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index f55341e52970..d8e13abd1bca 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -678,7 +678,7 @@ static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
         }
 }
 
-static const struct regmap_config fsl_esai_regmap_config = {
+static struct regmap_config fsl_esai_regmap_config = {
         .reg_bits = 32,
         .reg_stride = 4,
         .val_bits = 32,
@@ -704,6 +704,9 @@ static int fsl_esai_probe(struct platform_device *pdev)
         esai_priv->pdev = pdev;
         strcpy(esai_priv->name, np->name);
 
+        if (of_property_read_bool(np, "big-endian"))
+                fsl_esai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
+
         /* Get the addresses and IRQ */
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         regs = devm_ioremap_resource(&pdev->dev, res);