ASoC: fsl-esai: fix ESAI TDM slot setting

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

2 files changed, 3 insertions, 3 deletions

diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index d0c72ed261e7..c84026c99134 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -326,7 +326,7 @@ static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
         regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
                            ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
         regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
-                           ESAI_xSMA_xS_MASK, ESAI_xSMB_xS(tx_mask));
+                           ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
 
         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
                            ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
@@ -334,7 +334,7 @@ static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
         regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
                            ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
         regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
-                           ESAI_xSMA_xS_MASK, ESAI_xSMB_xS(rx_mask));
+                           ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
 
         esai_priv->slot_width = slot_width;
 
diff --git a/sound/soc/fsl/fsl_esai.h b/sound/soc/fsl/fsl_esai.h
index 9c9f957fcae1..75e14033e8d8 100644
--- a/sound/soc/fsl/fsl_esai.h
+++ b/sound/soc/fsl/fsl_esai.h
@@ -322,7 +322,7 @@
 #define ESAI_xSMB_xS_SHIFT      0
 #define ESAI_xSMB_xS_WIDTH      16
 #define ESAI_xSMB_xS_MASK       (((1 << ESAI_xSMB_xS_WIDTH) - 1) << ESAI_xSMB_xS_SHIFT)
-#define ESAI_xSMB_xS(v)         (((v) >> ESAI_xSMA_xS_WIDTH) & ESAI_xSMA_xS_MASK)
+#define ESAI_xSMB_xS(v)         (((v) >> ESAI_xSMA_xS_WIDTH) & ESAI_xSMB_xS_MASK)
 
 /* Port C Direction Register -- REG_ESAI_PRRC 0xF8 */
 #define ESAI_PRRC_PDC_SHIFT     0