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authorTimur Tabi <timur@freescale.com>2008-01-11 12:15:26 -0500
committerJaroslav Kysela <perex@perex.cz>2008-01-31 11:29:55 -0500
commit17467f23395f05ba7b361f7b504fe0f1095d5bb7 (patch)
tree8afcd6fa89cfd6e152635719fd935f5cb3cb2532 /sound/soc/fsl/fsl_dma.c
parentce22e03e62fd37fb2612abb7af1c66cc17038606 (diff)
[ALSA] Add ASoC drivers for the Freescale MPC8610 SoC
Add the ASoC drivers for the Freescale MPC8610 SoC and the MPC8610 HPCD reference board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
Diffstat (limited to 'sound/soc/fsl/fsl_dma.c')
-rw-r--r--sound/soc/fsl/fsl_dma.c839
1 files changed, 839 insertions, 0 deletions
diff --git a/sound/soc/fsl/fsl_dma.c b/sound/soc/fsl/fsl_dma.c
new file mode 100644
index 000000000000..2173203b29ab
--- /dev/null
+++ b/sound/soc/fsl/fsl_dma.c
@@ -0,0 +1,839 @@
1/*
2 * Freescale DMA ALSA SoC PCM driver
3 *
4 * Author: Timur Tabi <timur@freescale.com>
5 *
6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed
7 * under the terms of the GNU General Public License version 2. This
8 * program is licensed "as is" without any warranty of any kind, whether
9 * express or implied.
10 *
11 * This driver implements ASoC support for the Elo DMA controller, which is
12 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
13 * the PCM driver is what handles the DMA buffer.
14 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22
23#include <sound/driver.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28
29#include <asm/io.h>
30
31#include "fsl_dma.h"
32
33/*
34 * The formats that the DMA controller supports, which is anything
35 * that is 8, 16, or 32 bits.
36 */
37#define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
38 SNDRV_PCM_FMTBIT_U8 | \
39 SNDRV_PCM_FMTBIT_S16_LE | \
40 SNDRV_PCM_FMTBIT_S16_BE | \
41 SNDRV_PCM_FMTBIT_U16_LE | \
42 SNDRV_PCM_FMTBIT_U16_BE | \
43 SNDRV_PCM_FMTBIT_S24_LE | \
44 SNDRV_PCM_FMTBIT_S24_BE | \
45 SNDRV_PCM_FMTBIT_U24_LE | \
46 SNDRV_PCM_FMTBIT_U24_BE | \
47 SNDRV_PCM_FMTBIT_S32_LE | \
48 SNDRV_PCM_FMTBIT_S32_BE | \
49 SNDRV_PCM_FMTBIT_U32_LE | \
50 SNDRV_PCM_FMTBIT_U32_BE)
51
52#define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
53 SNDRV_PCM_RATE_CONTINUOUS)
54
55/* DMA global data. This structure is used by fsl_dma_open() to determine
56 * which DMA channels to assign to a substream. Unfortunately, ASoC V1 does
57 * not allow the machine driver to provide this information to the PCM
58 * driver in advance, and there's no way to differentiate between the two
59 * DMA controllers. So for now, this driver only supports one SSI device
60 * using two DMA channels. We cannot support multiple DMA devices.
61 *
62 * ssi_stx_phys: bus address of SSI STX register
63 * ssi_srx_phys: bus address of SSI SRX register
64 * dma_channel: pointer to the DMA channel's registers
65 * irq: IRQ for this DMA channel
66 * assigned: set to 1 if that DMA channel is assigned to a substream
67 */
68static struct {
69 dma_addr_t ssi_stx_phys;
70 dma_addr_t ssi_srx_phys;
71 struct ccsr_dma_channel __iomem *dma_channel[2];
72 unsigned int irq[2];
73 unsigned int assigned[2];
74} dma_global_data;
75
76/*
77 * The number of DMA links to use. Two is the bare minimum, but if you
78 * have really small links you might need more.
79 */
80#define NUM_DMA_LINKS 2
81
82/** fsl_dma_private: p-substream DMA data
83 *
84 * Each substream has a 1-to-1 association with a DMA channel.
85 *
86 * The link[] array is first because it needs to be aligned on a 32-byte
87 * boundary, so putting it first will ensure alignment without padding the
88 * structure.
89 *
90 * @link[]: array of link descriptors
91 * @controller_id: which DMA controller (0, 1, ...)
92 * @channel_id: which DMA channel on the controller (0, 1, 2, ...)
93 * @dma_channel: pointer to the DMA channel's registers
94 * @irq: IRQ for this DMA channel
95 * @substream: pointer to the substream object, needed by the ISR
96 * @ssi_sxx_phys: bus address of the STX or SRX register to use
97 * @ld_buf_phys: physical address of the LD buffer
98 * @current_link: index into link[] of the link currently being processed
99 * @dma_buf_phys: physical address of the DMA buffer
100 * @dma_buf_next: physical address of the next period to process
101 * @dma_buf_end: physical address of the byte after the end of the DMA
102 * @buffer period_size: the size of a single period
103 * @num_periods: the number of periods in the DMA buffer
104 */
105struct fsl_dma_private {
106 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
107 unsigned int controller_id;
108 unsigned int channel_id;
109 struct ccsr_dma_channel __iomem *dma_channel;
110 unsigned int irq;
111 struct snd_pcm_substream *substream;
112 dma_addr_t ssi_sxx_phys;
113 dma_addr_t ld_buf_phys;
114 unsigned int current_link;
115 dma_addr_t dma_buf_phys;
116 dma_addr_t dma_buf_next;
117 dma_addr_t dma_buf_end;
118 size_t period_size;
119 unsigned int num_periods;
120};
121
122/**
123 * fsl_dma_hardare: define characteristics of the PCM hardware.
124 *
125 * The PCM hardware is the Freescale DMA controller. This structure defines
126 * the capabilities of that hardware.
127 *
128 * Since the sampling rate and data format are not controlled by the DMA
129 * controller, we specify no limits for those values. The only exception is
130 * period_bytes_min, which is set to a reasonably low value to prevent the
131 * DMA controller from generating too many interrupts per second.
132 *
133 * Since each link descriptor has a 32-bit byte count field, we set
134 * period_bytes_max to the largest 32-bit number. We also have no maximum
135 * number of periods.
136 */
137static const struct snd_pcm_hardware fsl_dma_hardware = {
138
139 .info = SNDRV_PCM_INFO_INTERLEAVED,
140 .formats = FSLDMA_PCM_FORMATS,
141 .rates = FSLDMA_PCM_RATES,
142 .rate_min = 5512,
143 .rate_max = 192000,
144 .period_bytes_min = 512, /* A reasonable limit */
145 .period_bytes_max = (u32) -1,
146 .periods_min = NUM_DMA_LINKS,
147 .periods_max = (unsigned int) -1,
148 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */
149};
150
151/**
152 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
153 *
154 * This function should be called by the ISR whenever the DMA controller
155 * halts data transfer.
156 */
157static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
158{
159 unsigned long flags;
160
161 snd_pcm_stream_lock_irqsave(substream, flags);
162
163 if (snd_pcm_running(substream))
164 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
165
166 snd_pcm_stream_unlock_irqrestore(substream, flags);
167}
168
169/**
170 * fsl_dma_update_pointers - update LD pointers to point to the next period
171 *
172 * As each period is completed, this function changes the the link
173 * descriptor pointers for that period to point to the next period.
174 */
175static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
176{
177 struct fsl_dma_link_descriptor *link =
178 &dma_private->link[dma_private->current_link];
179
180 /* Update our link descriptors to point to the next period */
181 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
182 link->source_addr =
183 cpu_to_be32(dma_private->dma_buf_next);
184 else
185 link->dest_addr =
186 cpu_to_be32(dma_private->dma_buf_next);
187
188 /* Update our variables for next time */
189 dma_private->dma_buf_next += dma_private->period_size;
190
191 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
192 dma_private->dma_buf_next = dma_private->dma_buf_phys;
193
194 if (++dma_private->current_link >= NUM_DMA_LINKS)
195 dma_private->current_link = 0;
196}
197
198/**
199 * fsl_dma_isr: interrupt handler for the DMA controller
200 *
201 * @irq: IRQ of the DMA channel
202 * @dev_id: pointer to the dma_private structure for this DMA channel
203 */
204static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
205{
206 struct fsl_dma_private *dma_private = dev_id;
207 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
208 irqreturn_t ret = IRQ_NONE;
209 u32 sr, sr2 = 0;
210
211 /* We got an interrupt, so read the status register to see what we
212 were interrupted for.
213 */
214 sr = in_be32(&dma_channel->sr);
215
216 if (sr & CCSR_DMA_SR_TE) {
217 dev_err(dma_private->substream->pcm->card->dev,
218 "DMA transmit error (controller=%u channel=%u irq=%u\n",
219 dma_private->controller_id,
220 dma_private->channel_id, irq);
221 fsl_dma_abort_stream(dma_private->substream);
222 sr2 |= CCSR_DMA_SR_TE;
223 ret = IRQ_HANDLED;
224 }
225
226 if (sr & CCSR_DMA_SR_CH)
227 ret = IRQ_HANDLED;
228
229 if (sr & CCSR_DMA_SR_PE) {
230 dev_err(dma_private->substream->pcm->card->dev,
231 "DMA%u programming error (channel=%u irq=%u)\n",
232 dma_private->controller_id,
233 dma_private->channel_id, irq);
234 fsl_dma_abort_stream(dma_private->substream);
235 sr2 |= CCSR_DMA_SR_PE;
236 ret = IRQ_HANDLED;
237 }
238
239 if (sr & CCSR_DMA_SR_EOLNI) {
240 sr2 |= CCSR_DMA_SR_EOLNI;
241 ret = IRQ_HANDLED;
242 }
243
244 if (sr & CCSR_DMA_SR_CB)
245 ret = IRQ_HANDLED;
246
247 if (sr & CCSR_DMA_SR_EOSI) {
248 struct snd_pcm_substream *substream = dma_private->substream;
249
250 /* Tell ALSA we completed a period. */
251 snd_pcm_period_elapsed(substream);
252
253 /*
254 * Update our link descriptors to point to the next period. We
255 * only need to do this if the number of periods is not equal to
256 * the number of links.
257 */
258 if (dma_private->num_periods != NUM_DMA_LINKS)
259 fsl_dma_update_pointers(dma_private);
260
261 sr2 |= CCSR_DMA_SR_EOSI;
262 ret = IRQ_HANDLED;
263 }
264
265 if (sr & CCSR_DMA_SR_EOLSI) {
266 sr2 |= CCSR_DMA_SR_EOLSI;
267 ret = IRQ_HANDLED;
268 }
269
270 /* Clear the bits that we set */
271 if (sr2)
272 out_be32(&dma_channel->sr, sr2);
273
274 return ret;
275}
276
277/**
278 * fsl_dma_new: initialize this PCM driver.
279 *
280 * This function is called when the codec driver calls snd_soc_new_pcms(),
281 * once for each .dai_link in the machine driver's snd_soc_machine
282 * structure.
283 */
284static int fsl_dma_new(struct snd_card *card, struct snd_soc_codec_dai *dai,
285 struct snd_pcm *pcm)
286{
287 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32);
288 int ret;
289
290 if (!card->dev->dma_mask)
291 card->dev->dma_mask = &fsl_dma_dmamask;
292
293 if (!card->dev->coherent_dma_mask)
294 card->dev->coherent_dma_mask = fsl_dma_dmamask;
295
296 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev,
297 fsl_dma_hardware.buffer_bytes_max,
298 &pcm->streams[0].substream->dma_buffer);
299 if (ret) {
300 dev_err(card->dev,
301 "Can't allocate playback DMA buffer (size=%u)\n",
302 fsl_dma_hardware.buffer_bytes_max);
303 return -ENOMEM;
304 }
305
306 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev,
307 fsl_dma_hardware.buffer_bytes_max,
308 &pcm->streams[1].substream->dma_buffer);
309 if (ret) {
310 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer);
311 dev_err(card->dev,
312 "Can't allocate capture DMA buffer (size=%u)\n",
313 fsl_dma_hardware.buffer_bytes_max);
314 return -ENOMEM;
315 }
316
317 return 0;
318}
319
320/**
321 * fsl_dma_open: open a new substream.
322 *
323 * Each substream has its own DMA buffer.
324 */
325static int fsl_dma_open(struct snd_pcm_substream *substream)
326{
327 struct snd_pcm_runtime *runtime = substream->runtime;
328 struct fsl_dma_private *dma_private;
329 dma_addr_t ld_buf_phys;
330 unsigned int channel;
331 int ret = 0;
332
333 /*
334 * Reject any DMA buffer whose size is not a multiple of the period
335 * size. We need to make sure that the DMA buffer can be evenly divided
336 * into periods.
337 */
338 ret = snd_pcm_hw_constraint_integer(runtime,
339 SNDRV_PCM_HW_PARAM_PERIODS);
340 if (ret < 0) {
341 dev_err(substream->pcm->card->dev, "invalid buffer size\n");
342 return ret;
343 }
344
345 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
346
347 if (dma_global_data.assigned[channel]) {
348 dev_err(substream->pcm->card->dev,
349 "DMA channel already assigned\n");
350 return -EBUSY;
351 }
352
353 dma_private = dma_alloc_coherent(substream->pcm->dev,
354 sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL);
355 if (!dma_private) {
356 dev_err(substream->pcm->card->dev,
357 "can't allocate DMA private data\n");
358 return -ENOMEM;
359 }
360 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
361 dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys;
362 else
363 dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys;
364
365 dma_private->dma_channel = dma_global_data.dma_channel[channel];
366 dma_private->irq = dma_global_data.irq[channel];
367 dma_private->substream = substream;
368 dma_private->ld_buf_phys = ld_buf_phys;
369 dma_private->dma_buf_phys = substream->dma_buffer.addr;
370
371 /* We only support one DMA controller for now */
372 dma_private->controller_id = 0;
373 dma_private->channel_id = channel;
374
375 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private);
376 if (ret) {
377 dev_err(substream->pcm->card->dev,
378 "can't register ISR for IRQ %u (ret=%i)\n",
379 dma_private->irq, ret);
380 dma_free_coherent(substream->pcm->dev,
381 sizeof(struct fsl_dma_private),
382 dma_private, dma_private->ld_buf_phys);
383 return ret;
384 }
385
386 dma_global_data.assigned[channel] = 1;
387
388 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
389 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
390 runtime->private_data = dma_private;
391
392 return 0;
393}
394
395/**
396 * fsl_dma_hw_params: allocate the DMA buffer and the DMA link descriptors.
397 *
398 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
399 * descriptors that ping-pong from one period to the next. For example, if
400 * there are six periods and two link descriptors, this is how they look
401 * before playback starts:
402 *
403 * The last link descriptor
404 * ____________ points back to the first
405 * | |
406 * V |
407 * ___ ___ |
408 * | |->| |->|
409 * |___| |___|
410 * | |
411 * | |
412 * V V
413 * _________________________________________
414 * | | | | | | | The DMA buffer is
415 * | | | | | | | divided into 6 parts
416 * |______|______|______|______|______|______|
417 *
418 * and here's how they look after the first period is finished playing:
419 *
420 * ____________
421 * | |
422 * V |
423 * ___ ___ |
424 * | |->| |->|
425 * |___| |___|
426 * | |
427 * |______________
428 * | |
429 * V V
430 * _________________________________________
431 * | | | | | | |
432 * | | | | | | |
433 * |______|______|______|______|______|______|
434 *
435 * The first link descriptor now points to the third period. The DMA
436 * controller is currently playing the second period. When it finishes, it
437 * will jump back to the first descriptor and play the third period.
438 *
439 * There are four reasons we do this:
440 *
441 * 1. The only way to get the DMA controller to automatically restart the
442 * transfer when it gets to the end of the buffer is to use chaining
443 * mode. Basic direct mode doesn't offer that feature.
444 * 2. We need to receive an interrupt at the end of every period. The DMA
445 * controller can generate an interrupt at the end of every link transfer
446 * (aka segment). Making each period into a DMA segment will give us the
447 * interrupts we need.
448 * 3. By creating only two link descriptors, regardless of the number of
449 * periods, we do not need to reallocate the link descriptors if the
450 * number of periods changes.
451 * 4. All of the audio data is still stored in a single, contiguous DMA
452 * buffer, which is what ALSA expects. We're just dividing it into
453 * contiguous parts, and creating a link descriptor for each one.
454 *
455 * Note that due to a quirk of the SSI's STX register, the target address
456 * for the DMA operations depends on the sample size. So we don't program
457 * the dest_addr (for playback -- source_addr for capture) fields in the
458 * link descriptors here. We do that in fsl_dma_prepare()
459 */
460static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
461 struct snd_pcm_hw_params *hw_params)
462{
463 struct snd_pcm_runtime *runtime = substream->runtime;
464 struct fsl_dma_private *dma_private = runtime->private_data;
465 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
466
467 dma_addr_t temp_addr; /* Pointer to next period */
468 u64 temp_link; /* Pointer to next link descriptor */
469 u32 mr; /* Temporary variable for MR register */
470
471 unsigned int i;
472
473 /* Get all the parameters we need */
474 size_t buffer_size = params_buffer_bytes(hw_params);
475 size_t period_size = params_period_bytes(hw_params);
476
477 /* Initialize our DMA tracking variables */
478 dma_private->period_size = period_size;
479 dma_private->num_periods = params_periods(hw_params);
480 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
481 dma_private->dma_buf_next = dma_private->dma_buf_phys +
482 (NUM_DMA_LINKS * period_size);
483 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
484 dma_private->dma_buf_next = dma_private->dma_buf_phys;
485
486 /*
487 * Initialize each link descriptor.
488 *
489 * The actual address in STX0 (destination for playback, source for
490 * capture) is based on the sample size, but we don't know the sample
491 * size in this function, so we'll have to adjust that later. See
492 * comments in fsl_dma_prepare().
493 *
494 * The DMA controller does not have a cache, so the CPU does not
495 * need to tell it to flush its cache. However, the DMA
496 * controller does need to tell the CPU to flush its cache.
497 * That's what the SNOOP bit does.
498 *
499 * Also, even though the DMA controller supports 36-bit addressing, for
500 * simplicity we currently support only 32-bit addresses for the audio
501 * buffer itself.
502 */
503 temp_addr = substream->dma_buffer.addr;
504 temp_link = dma_private->ld_buf_phys +
505 sizeof(struct fsl_dma_link_descriptor);
506
507 for (i = 0; i < NUM_DMA_LINKS; i++) {
508 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
509
510 link->count = cpu_to_be32(period_size);
511 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
512 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
513 link->next = cpu_to_be64(temp_link);
514
515 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
516 link->source_addr = cpu_to_be32(temp_addr);
517 else
518 link->dest_addr = cpu_to_be32(temp_addr);
519
520 temp_addr += period_size;
521 temp_link += sizeof(struct fsl_dma_link_descriptor);
522 }
523 /* The last link descriptor points to the first */
524 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
525
526 /* Tell the DMA controller where the first link descriptor is */
527 out_be32(&dma_channel->clndar,
528 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
529 out_be32(&dma_channel->eclndar,
530 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
531
532 /* The manual says the BCR must be clear before enabling EMP */
533 out_be32(&dma_channel->bcr, 0);
534
535 /*
536 * Program the mode register for interrupts, external master control,
537 * and source/destination hold. Also clear the Channel Abort bit.
538 */
539 mr = in_be32(&dma_channel->mr) &
540 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
541
542 /*
543 * We want External Master Start and External Master Pause enabled,
544 * because the SSI is controlling the DMA controller. We want the DMA
545 * controller to be set up in advance, and then we signal only the SSI
546 * to start transfering.
547 *
548 * We want End-Of-Segment Interrupts enabled, because this will generate
549 * an interrupt at the end of each segment (each link descriptor
550 * represents one segment). Each DMA segment is the same thing as an
551 * ALSA period, so this is how we get an interrupt at the end of every
552 * period.
553 *
554 * We want Error Interrupt enabled, so that we can get an error if
555 * the DMA controller is mis-programmed somehow.
556 */
557 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
558 CCSR_DMA_MR_EMS_EN;
559
560 /* For playback, we want the destination address to be held. For
561 capture, set the source address to be held. */
562 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
563 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
564
565 out_be32(&dma_channel->mr, mr);
566
567 return 0;
568}
569
570/**
571 * fsl_dma_prepare - prepare the DMA registers for playback.
572 *
573 * This function is called after the specifics of the audio data are known,
574 * i.e. snd_pcm_runtime is initialized.
575 *
576 * In this function, we finish programming the registers of the DMA
577 * controller that are dependent on the sample size.
578 *
579 * One of the drawbacks with big-endian is that when copying integers of
580 * different sizes to a fixed-sized register, the address to which the
581 * integer must be copied is dependent on the size of the integer.
582 *
583 * For example, if P is the address of a 32-bit register, and X is a 32-bit
584 * integer, then X should be copied to address P. However, if X is a 16-bit
585 * integer, then it should be copied to P+2. If X is an 8-bit register,
586 * then it should be copied to P+3.
587 *
588 * So for playback of 8-bit samples, the DMA controller must transfer single
589 * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
590 * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
591 *
592 * For 24-bit samples, the offset is 1 byte. However, the DMA controller
593 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
594 * and 8 bytes at a time). So we do not support packed 24-bit samples.
595 * 24-bit data must be padded to 32 bits.
596 */
597static int fsl_dma_prepare(struct snd_pcm_substream *substream)
598{
599 struct snd_pcm_runtime *runtime = substream->runtime;
600 struct fsl_dma_private *dma_private = runtime->private_data;
601 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
602 u32 mr;
603 unsigned int i;
604 dma_addr_t ssi_sxx_phys; /* Bus address of SSI STX register */
605 unsigned int frame_size; /* Number of bytes per frame */
606
607 ssi_sxx_phys = dma_private->ssi_sxx_phys;
608
609 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
610 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
611
612 switch (runtime->sample_bits) {
613 case 8:
614 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
615 ssi_sxx_phys += 3;
616 break;
617 case 16:
618 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
619 ssi_sxx_phys += 2;
620 break;
621 case 32:
622 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
623 break;
624 default:
625 dev_err(substream->pcm->card->dev,
626 "unsupported sample size %u\n", runtime->sample_bits);
627 return -EINVAL;
628 }
629
630 frame_size = runtime->frame_bits / 8;
631 /*
632 * BWC should always be a multiple of the frame size. BWC determines
633 * how many bytes are sent/received before the DMA controller checks the
634 * SSI to see if it needs to stop. For playback, the transmit FIFO can
635 * hold three frames, so we want to send two frames at a time. For
636 * capture, the receive FIFO is triggered when it contains one frame, so
637 * we want to receive one frame at a time.
638 */
639
640 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
641 mr |= CCSR_DMA_MR_BWC(2 * frame_size);
642 else
643 mr |= CCSR_DMA_MR_BWC(frame_size);
644
645 out_be32(&dma_channel->mr, mr);
646
647 /*
648 * Program the address of the DMA transfer to/from the SSI.
649 */
650 for (i = 0; i < NUM_DMA_LINKS; i++) {
651 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
652
653 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
654 link->dest_addr = cpu_to_be32(ssi_sxx_phys);
655 else
656 link->source_addr = cpu_to_be32(ssi_sxx_phys);
657 }
658
659 return 0;
660}
661
662/**
663 * fsl_dma_pointer: determine the current position of the DMA transfer
664 *
665 * This function is called by ALSA when ALSA wants to know where in the
666 * stream buffer the hardware currently is.
667 *
668 * For playback, the SAR register contains the physical address of the most
669 * recent DMA transfer. For capture, the value is in the DAR register.
670 *
671 * The base address of the buffer is stored in the source_addr field of the
672 * first link descriptor.
673 */
674static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream)
675{
676 struct snd_pcm_runtime *runtime = substream->runtime;
677 struct fsl_dma_private *dma_private = runtime->private_data;
678 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
679 dma_addr_t position;
680 snd_pcm_uframes_t frames;
681
682 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
683 position = in_be32(&dma_channel->sar);
684 else
685 position = in_be32(&dma_channel->dar);
686
687 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
688
689 /*
690 * If the current address is just past the end of the buffer, wrap it
691 * around.
692 */
693 if (frames == runtime->buffer_size)
694 frames = 0;
695
696 return frames;
697}
698
699/**
700 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
701 *
702 * Release the resources allocated in fsl_dma_hw_params() and de-program the
703 * registers.
704 *
705 * This function can be called multiple times.
706 */
707static int fsl_dma_hw_free(struct snd_pcm_substream *substream)
708{
709 struct snd_pcm_runtime *runtime = substream->runtime;
710 struct fsl_dma_private *dma_private = runtime->private_data;
711
712 if (dma_private) {
713 struct ccsr_dma_channel __iomem *dma_channel;
714
715 dma_channel = dma_private->dma_channel;
716
717 /* Stop the DMA */
718 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
719 out_be32(&dma_channel->mr, 0);
720
721 /* Reset all the other registers */
722 out_be32(&dma_channel->sr, -1);
723 out_be32(&dma_channel->clndar, 0);
724 out_be32(&dma_channel->eclndar, 0);
725 out_be32(&dma_channel->satr, 0);
726 out_be32(&dma_channel->sar, 0);
727 out_be32(&dma_channel->datr, 0);
728 out_be32(&dma_channel->dar, 0);
729 out_be32(&dma_channel->bcr, 0);
730 out_be32(&dma_channel->nlndar, 0);
731 out_be32(&dma_channel->enlndar, 0);
732 }
733
734 return 0;
735}
736
737/**
738 * fsl_dma_close: close the stream.
739 */
740static int fsl_dma_close(struct snd_pcm_substream *substream)
741{
742 struct snd_pcm_runtime *runtime = substream->runtime;
743 struct fsl_dma_private *dma_private = runtime->private_data;
744 int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
745
746 if (dma_private) {
747 if (dma_private->irq)
748 free_irq(dma_private->irq, dma_private);
749
750 if (dma_private->ld_buf_phys) {
751 dma_unmap_single(substream->pcm->dev,
752 dma_private->ld_buf_phys,
753 sizeof(dma_private->link), DMA_TO_DEVICE);
754 }
755
756 /* Deallocate the fsl_dma_private structure */
757 dma_free_coherent(substream->pcm->dev,
758 sizeof(struct fsl_dma_private),
759 dma_private, dma_private->ld_buf_phys);
760 substream->runtime->private_data = NULL;
761 }
762
763 dma_global_data.assigned[dir] = 0;
764
765 return 0;
766}
767
768/*
769 * Remove this PCM driver.
770 */
771static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm)
772{
773 struct snd_pcm_substream *substream;
774 unsigned int i;
775
776 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
777 substream = pcm->streams[i].substream;
778 if (substream) {
779 snd_dma_free_pages(&substream->dma_buffer);
780 substream->dma_buffer.area = NULL;
781 substream->dma_buffer.addr = 0;
782 }
783 }
784}
785
786static struct snd_pcm_ops fsl_dma_ops = {
787 .open = fsl_dma_open,
788 .close = fsl_dma_close,
789 .ioctl = snd_pcm_lib_ioctl,
790 .hw_params = fsl_dma_hw_params,
791 .hw_free = fsl_dma_hw_free,
792 .prepare = fsl_dma_prepare,
793 .pointer = fsl_dma_pointer,
794};
795
796struct snd_soc_platform fsl_soc_platform = {
797 .name = "fsl-dma",
798 .pcm_ops = &fsl_dma_ops,
799 .pcm_new = fsl_dma_new,
800 .pcm_free = fsl_dma_free_dma_buffers,
801};
802EXPORT_SYMBOL_GPL(fsl_soc_platform);
803
804/**
805 * fsl_dma_configure: store the DMA parameters from the fabric driver.
806 *
807 * This function is called by the ASoC fabric driver to give us the DMA and
808 * SSI channel information.
809 *
810 * Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI
811 * data when a substream is created, so for now we need to store this data
812 * into a global variable. This means that we can only support one DMA
813 * controller, and hence only one SSI.
814 */
815int fsl_dma_configure(struct fsl_dma_info *dma_info)
816{
817 static int initialized;
818
819 /* We only support one DMA controller for now */
820 if (initialized)
821 return 0;
822
823 dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys;
824 dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys;
825 dma_global_data.dma_channel[0] = dma_info->dma_channel[0];
826 dma_global_data.dma_channel[1] = dma_info->dma_channel[1];
827 dma_global_data.irq[0] = dma_info->dma_irq[0];
828 dma_global_data.irq[1] = dma_info->dma_irq[1];
829 dma_global_data.assigned[0] = 0;
830 dma_global_data.assigned[1] = 0;
831
832 initialized = 1;
833 return 1;
834}
835EXPORT_SYMBOL_GPL(fsl_dma_configure);
836
837MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
838MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module");
839MODULE_LICENSE("GPL");