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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2014-04-04 07:31:45 -0400
committerMark Brown <broonie@linaro.org>2014-04-14 12:24:24 -0400
commitffd950f75dd71f13194b5d5c8ec67926a1996102 (patch)
treeb34d421c814369f6ca5b14bbeec7c2a3ff9bc211 /sound/soc/davinci/davinci-mcasp.c
parent83f12503bd1fb18d3fd460871660b34faf671918 (diff)
ASoC: davinci-mcasp: Add support for I2S format
The FS needs to be inverted in McASP compared to other supported formats. Use a flag to indicate if the FS needs to be inverted. At the same time fail when non supported format is asked since the default case was anyways configuring McASP to a not valid format. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc/davinci/davinci-mcasp.c')
-rw-r--r--sound/soc/davinci/davinci-mcasp.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 113e74c9479f..d4d640004bed 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -273,6 +273,7 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
273 int ret = 0; 273 int ret = 0;
274 u32 data_delay; 274 u32 data_delay;
275 bool fs_pol_rising; 275 bool fs_pol_rising;
276 bool inv_fs = false;
276 277
277 pm_runtime_get_sync(mcasp->dev); 278 pm_runtime_get_sync(mcasp->dev);
278 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 279 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -291,14 +292,19 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
291 /* No delay after FS */ 292 /* No delay after FS */
292 data_delay = 0; 293 data_delay = 0;
293 break; 294 break;
294 default: 295 case SND_SOC_DAIFMT_I2S:
295 /* configure a full-word SYNC pulse (LRCLK) */ 296 /* configure a full-word SYNC pulse (LRCLK) */
296 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 297 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
297 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 298 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
298 299
299 /* 1st data bit occur one ACLK cycle after the frame sync */ 300 /* 1st data bit occur one ACLK cycle after the frame sync */
300 data_delay = 1; 301 data_delay = 1;
302 /* FS need to be inverted */
303 inv_fs = true;
301 break; 304 break;
305 default:
306 ret = -EINVAL;
307 goto out;
302 } 308 }
303 309
304 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 310 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
@@ -379,6 +385,9 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
379 goto out; 385 goto out;
380 } 386 }
381 387
388 if (inv_fs)
389 fs_pol_rising = !fs_pol_rising;
390
382 if (fs_pol_rising) { 391 if (fs_pol_rising) {
383 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 392 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
384 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 393 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);