aboutsummaryrefslogtreecommitdiffstats
path: root/sound/soc/davinci/davinci-mcasp.c
diff options
context:
space:
mode:
authorPeter Ujfalusi <peter.ujfalusi@ti.com>2013-11-14 04:35:36 -0500
committerMark Brown <broonie@linaro.org>2013-12-10 06:22:16 -0500
commitf68205a7f8c0b1fd02cec6116bbb66bb4fd7bc51 (patch)
tree0dee6fcafd3aadc173577d091cf1fc1e84e890c5 /sound/soc/davinci/davinci-mcasp.c
parent453c499028bf2ecf3b31ccb7c3657fe1b0b28943 (diff)
ASoC: davinci-mcasp: Change IO functions parameter list
Instead of passing __iomem address (mcasp->base + register_offset) pass the main mcasp structure and only access the mcasp->base in the low level IO functions. In most cases this helps with code readability and it will make it easier to switch over to regmap in the future. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc/davinci/davinci-mcasp.c')
-rw-r--r--sound/soc/davinci/davinci-mcasp.c336
1 files changed, 161 insertions, 175 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index fc8c13d2f31e..19c66625af4e 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -71,60 +71,67 @@ struct davinci_mcasp {
71#endif 71#endif
72}; 72};
73 73
74static inline void mcasp_set_bits(void __iomem *reg, u32 val) 74static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
75 u32 val)
75{ 76{
77 void __iomem *reg = mcasp->base + offset;
76 __raw_writel(__raw_readl(reg) | val, reg); 78 __raw_writel(__raw_readl(reg) | val, reg);
77} 79}
78 80
79static inline void mcasp_clr_bits(void __iomem *reg, u32 val) 81static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
82 u32 val)
80{ 83{
84 void __iomem *reg = mcasp->base + offset;
81 __raw_writel((__raw_readl(reg) & ~(val)), reg); 85 __raw_writel((__raw_readl(reg) & ~(val)), reg);
82} 86}
83 87
84static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask) 88static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
89 u32 val, u32 mask)
85{ 90{
91 void __iomem *reg = mcasp->base + offset;
86 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 92 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
87} 93}
88 94
89static inline void mcasp_set_reg(void __iomem *reg, u32 val) 95static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
96 u32 val)
90{ 97{
91 __raw_writel(val, reg); 98 __raw_writel(val, mcasp->base + offset);
92} 99}
93 100
94static inline u32 mcasp_get_reg(void __iomem *reg) 101static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
95{ 102{
96 return (unsigned int)__raw_readl(reg); 103 return (u32)__raw_readl(mcasp->base + offset);
97} 104}
98 105
99static void mcasp_set_ctl_reg(void __iomem *regs, u32 val) 106static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
100{ 107{
101 int i = 0; 108 int i = 0;
102 109
103 mcasp_set_bits(regs, val); 110 mcasp_set_bits(mcasp, ctl_reg, val);
104 111
105 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 112 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
106 /* loop count is to avoid the lock-up */ 113 /* loop count is to avoid the lock-up */
107 for (i = 0; i < 1000; i++) { 114 for (i = 0; i < 1000; i++) {
108 if ((mcasp_get_reg(regs) & val) == val) 115 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
109 break; 116 break;
110 } 117 }
111 118
112 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val)) 119 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
113 printk(KERN_ERR "GBLCTL write error\n"); 120 printk(KERN_ERR "GBLCTL write error\n");
114} 121}
115 122
116static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 123static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
117{ 124{
118 u32 rxfmctl = mcasp_get_reg(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG); 125 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
119 u32 aclkxctl = mcasp_get_reg(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG); 126 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
120 127
121 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; 128 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
122} 129}
123 130
124static void mcasp_start_rx(struct davinci_mcasp *mcasp) 131static void mcasp_start_rx(struct davinci_mcasp *mcasp)
125{ 132{
126 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 133 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
127 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 134 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
128 135
129 /* 136 /*
130 * When ASYNC == 0 the transmit and receive sections operate 137 * When ASYNC == 0 the transmit and receive sections operate
@@ -132,25 +139,22 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
132 * sure that the TX signlas are enabled when starting reception. 139 * sure that the TX signlas are enabled when starting reception.
133 */ 140 */
134 if (mcasp_is_synchronous(mcasp)) { 141 if (mcasp_is_synchronous(mcasp)) {
135 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, 142 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
136 TXHCLKRST); 143 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
137 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG,
138 TXCLKRST);
139 } 144 }
140 145
141 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 146 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
142 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXBUF_REG, 0); 147 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
143 148
144 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 149 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
145 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 150 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
146 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXBUF_REG, 0); 151 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
147 152
148 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 153 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
149 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 154 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
150 155
151 if (mcasp_is_synchronous(mcasp)) 156 if (mcasp_is_synchronous(mcasp))
152 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, 157 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
153 TXFSRST);
154} 158}
155 159
156static void mcasp_start_tx(struct davinci_mcasp *mcasp) 160static void mcasp_start_tx(struct davinci_mcasp *mcasp)
@@ -158,14 +162,14 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp)
158 u8 offset = 0, i; 162 u8 offset = 0, i;
159 u32 cnt; 163 u32 cnt;
160 164
161 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 165 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
162 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 166 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
163 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 167 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
164 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0); 168 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
165 169
166 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 170 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
167 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 171 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
168 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0); 172 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
169 for (i = 0; i < mcasp->num_serializer; i++) { 173 for (i = 0; i < mcasp->num_serializer; i++) {
170 if (mcasp->serial_dir[i] == TX_MODE) { 174 if (mcasp->serial_dir[i] == TX_MODE) {
171 offset = i; 175 offset = i;
@@ -175,11 +179,11 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp)
175 179
176 /* wait for TX ready */ 180 /* wait for TX ready */
177 cnt = 0; 181 cnt = 0;
178 while (!(mcasp_get_reg(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) & 182 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
179 TXSTATE) && (cnt < 100000)) 183 TXSTATE) && (cnt < 100000))
180 cnt++; 184 cnt++;
181 185
182 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0); 186 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
183} 187}
184 188
185static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 189static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
@@ -191,15 +195,15 @@ static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
191 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 195 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
192 if (mcasp->txnumevt) { /* enable FIFO */ 196 if (mcasp->txnumevt) { /* enable FIFO */
193 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 197 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
194 mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE); 198 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
195 mcasp_set_bits(mcasp->base + reg, FIFO_ENABLE); 199 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
196 } 200 }
197 mcasp_start_tx(mcasp); 201 mcasp_start_tx(mcasp);
198 } else { 202 } else {
199 if (mcasp->rxnumevt) { /* enable FIFO */ 203 if (mcasp->rxnumevt) { /* enable FIFO */
200 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 204 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
201 mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE); 205 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
202 mcasp_set_bits(mcasp->base + reg, FIFO_ENABLE); 206 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
203 } 207 }
204 mcasp_start_rx(mcasp); 208 mcasp_start_rx(mcasp);
205 } 209 }
@@ -212,10 +216,10 @@ static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
212 * running 216 * running
213 */ 217 */
214 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) 218 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
215 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, 0); 219 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
216 220
217 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, 0); 221 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
218 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 222 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
219} 223}
220 224
221static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 225static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
@@ -229,8 +233,8 @@ static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
229 if (mcasp_is_synchronous(mcasp) && mcasp->streams) 233 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
230 val = TXHCLKRST | TXCLKRST | TXFSRST; 234 val = TXHCLKRST | TXCLKRST | TXFSRST;
231 235
232 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, val); 236 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
233 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 237 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
234} 238}
235 239
236static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 240static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
@@ -242,13 +246,13 @@ static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
242 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 246 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
243 if (mcasp->txnumevt) { /* disable FIFO */ 247 if (mcasp->txnumevt) { /* disable FIFO */
244 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 248 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
245 mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE); 249 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
246 } 250 }
247 mcasp_stop_tx(mcasp); 251 mcasp_stop_tx(mcasp);
248 } else { 252 } else {
249 if (mcasp->rxnumevt) { /* disable FIFO */ 253 if (mcasp->rxnumevt) { /* disable FIFO */
250 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 254 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
251 mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE); 255 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
252 } 256 }
253 mcasp_stop_rx(mcasp); 257 mcasp_stop_rx(mcasp);
254 } 258 }
@@ -258,62 +262,57 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
258 unsigned int fmt) 262 unsigned int fmt)
259{ 263{
260 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 264 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
261 void __iomem *base = mcasp->base;
262 265
263 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 266 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
264 case SND_SOC_DAIFMT_DSP_B: 267 case SND_SOC_DAIFMT_DSP_B:
265 case SND_SOC_DAIFMT_AC97: 268 case SND_SOC_DAIFMT_AC97:
266 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 269 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
267 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 270 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
268 break; 271 break;
269 default: 272 default:
270 /* configure a full-word SYNC pulse (LRCLK) */ 273 /* configure a full-word SYNC pulse (LRCLK) */
271 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 274 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
272 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 275 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
273 276
274 /* make 1st data bit occur one ACLK cycle after the frame sync */ 277 /* make 1st data bit occur one ACLK cycle after the frame sync */
275 mcasp_set_bits(base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1)); 278 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
276 mcasp_set_bits(base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1)); 279 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
277 break; 280 break;
278 } 281 }
279 282
280 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 283 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
281 case SND_SOC_DAIFMT_CBS_CFS: 284 case SND_SOC_DAIFMT_CBS_CFS:
282 /* codec is clock and frame slave */ 285 /* codec is clock and frame slave */
283 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 286 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
284 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 287 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
285 288
286 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 289 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
287 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 290 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
288 291
289 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, 292 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
290 ACLKX | ACLKR); 293 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
291 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
292 AFSX | AFSR);
293 break; 294 break;
294 case SND_SOC_DAIFMT_CBM_CFS: 295 case SND_SOC_DAIFMT_CBM_CFS:
295 /* codec is clock master and frame slave */ 296 /* codec is clock master and frame slave */
296 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 297 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
297 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 298 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
298 299
299 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 300 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
300 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 301 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
301 302
302 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, 303 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
303 ACLKX | ACLKR); 304 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
304 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
305 AFSX | AFSR);
306 break; 305 break;
307 case SND_SOC_DAIFMT_CBM_CFM: 306 case SND_SOC_DAIFMT_CBM_CFM:
308 /* codec is clock and frame master */ 307 /* codec is clock and frame master */
309 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 308 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
310 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 309 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
311 310
312 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 311 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
313 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 312 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
314 313
315 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, 314 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
316 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); 315 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
317 break; 316 break;
318 317
319 default: 318 default:
@@ -322,35 +321,35 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
322 321
323 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 322 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
324 case SND_SOC_DAIFMT_IB_NF: 323 case SND_SOC_DAIFMT_IB_NF:
325 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 324 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
326 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 325 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
327 326
328 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 327 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
329 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 328 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
330 break; 329 break;
331 330
332 case SND_SOC_DAIFMT_NB_IF: 331 case SND_SOC_DAIFMT_NB_IF:
333 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 332 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
334 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 333 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
335 334
336 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 335 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
337 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 336 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
338 break; 337 break;
339 338
340 case SND_SOC_DAIFMT_IB_IF: 339 case SND_SOC_DAIFMT_IB_IF:
341 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 340 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
342 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 341 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
343 342
344 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 343 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
345 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 344 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
346 break; 345 break;
347 346
348 case SND_SOC_DAIFMT_NB_NF: 347 case SND_SOC_DAIFMT_NB_NF:
349 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 348 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
350 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 349 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
351 350
352 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 351 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
353 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 352 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
354 break; 353 break;
355 354
356 default: 355 default:
@@ -366,16 +365,16 @@ static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div
366 365
367 switch (div_id) { 366 switch (div_id) {
368 case 0: /* MCLK divider */ 367 case 0: /* MCLK divider */
369 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, 368 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
370 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 369 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
371 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG, 370 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
372 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 371 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
373 break; 372 break;
374 373
375 case 1: /* BCLK divider */ 374 case 1: /* BCLK divider */
376 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG, 375 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
377 ACLKXDIV(div - 1), ACLKXDIV_MASK); 376 ACLKXDIV(div - 1), ACLKXDIV_MASK);
378 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_ACLKRCTL_REG, 377 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
379 ACLKRDIV(div - 1), ACLKRDIV_MASK); 378 ACLKRDIV(div - 1), ACLKRDIV_MASK);
380 break; 379 break;
381 380
@@ -396,13 +395,13 @@ static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
396 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 395 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
397 396
398 if (dir == SND_SOC_CLOCK_OUT) { 397 if (dir == SND_SOC_CLOCK_OUT) {
399 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 398 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
400 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 399 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
401 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, AHCLKX); 400 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
402 } else { 401 } else {
403 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 402 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
404 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
405 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, AHCLKX); 404 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
406 } 405 }
407 406
408 return 0; 407 return 0;
@@ -432,19 +431,18 @@ static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
432 fmt = (word_length >> 1) - 1; 431 fmt = (word_length >> 1) - 1;
433 432
434 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 433 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
435 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG, 434 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
436 RXSSZ(fmt), RXSSZ(0x0F)); 435 RXSSZ(0x0F));
437 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG, 436 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
438 TXSSZ(fmt), TXSSZ(0x0F)); 437 TXSSZ(0x0F));
439 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG, 438 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
440 TXROT(tx_rotate), TXROT(7)); 439 TXROT(7));
441 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG, 440 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
442 RXROT(rx_rotate), RXROT(7)); 441 RXROT(7));
443 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXMASK_REG, 442 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
444 mask);
445 } 443 }
446 444
447 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXMASK_REG, mask); 445 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
448 446
449 return 0; 447 return 0;
450} 448}
@@ -461,38 +459,33 @@ static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
461 u32 reg; 459 u32 reg;
462 /* Default configuration */ 460 /* Default configuration */
463 if (mcasp->version != MCASP_VERSION_4) 461 if (mcasp->version != MCASP_VERSION_4)
464 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PWREMUMGT_REG, 462 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
465 MCASP_SOFT);
466 463
467 /* All PINS as McASP */ 464 /* All PINS as McASP */
468 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000); 465 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
469 466
470 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 467 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
471 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 468 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
472 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_XEVTCTL_REG, 469 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
473 TXDATADMADIS);
474 } else { 470 } else {
475 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 471 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
476 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_REVTCTL_REG, 472 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
477 RXDATADMADIS);
478 } 473 }
479 474
480 for (i = 0; i < mcasp->num_serializer; i++) { 475 for (i = 0; i < mcasp->num_serializer; i++) {
481 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(i), 476 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
482 mcasp->serial_dir[i]); 477 mcasp->serial_dir[i]);
483 if (mcasp->serial_dir[i] == TX_MODE && 478 if (mcasp->serial_dir[i] == TX_MODE &&
484 tx_ser < max_active_serializers) { 479 tx_ser < max_active_serializers) {
485 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, 480 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
486 AXR(i));
487 tx_ser++; 481 tx_ser++;
488 } else if (mcasp->serial_dir[i] == RX_MODE && 482 } else if (mcasp->serial_dir[i] == RX_MODE &&
489 rx_ser < max_active_serializers) { 483 rx_ser < max_active_serializers) {
490 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, 484 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
491 AXR(i));
492 rx_ser++; 485 rx_ser++;
493 } else { 486 } else {
494 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(i), 487 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
495 SRMOD_INACTIVE, SRMOD_MASK); 488 SRMOD_INACTIVE, SRMOD_MASK);
496 } 489 }
497 } 490 }
498 491
@@ -512,9 +505,9 @@ static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
512 mcasp->txnumevt = 1; 505 mcasp->txnumevt = 1;
513 506
514 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 507 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
515 mcasp_mod_bits(mcasp->base + reg, tx_ser, NUMDMA_MASK); 508 mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
516 mcasp_mod_bits(mcasp->base + reg, 509 mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
517 ((mcasp->txnumevt * tx_ser) << 8), NUMEVT_MASK); 510 NUMEVT_MASK);
518 } 511 }
519 512
520 if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) { 513 if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
@@ -522,9 +515,9 @@ static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
522 mcasp->rxnumevt = 1; 515 mcasp->rxnumevt = 1;
523 516
524 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 517 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
525 mcasp_mod_bits(mcasp->base + reg, rx_ser, NUMDMA_MASK); 518 mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
526 mcasp_mod_bits(mcasp->base + reg, 519 mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
527 ((mcasp->rxnumevt * rx_ser) << 8), NUMEVT_MASK); 520 NUMEVT_MASK);
528 } 521 }
529 522
530 return 0; 523 return 0;
@@ -540,7 +533,7 @@ static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream)
540 for (i = 0; i < active_slots; i++) 533 for (i = 0; i < active_slots; i++)
541 mask |= (1 << i); 534 mask |= (1 << i);
542 535
543 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 536 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
544 537
545 if (!mcasp->dat_port) 538 if (!mcasp->dat_port)
546 busel = TXSEL; 539 busel = TXSEL;
@@ -548,26 +541,24 @@ static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream)
548 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 541 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
549 /* bit stream is MSB first with no delay */ 542 /* bit stream is MSB first with no delay */
550 /* DSP_B mode */ 543 /* DSP_B mode */
551 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXTDM_REG, mask); 544 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
552 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG, 545 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
553 busel | TXORD);
554 546
555 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32)) 547 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
556 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG, 548 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
557 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); 549 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
558 else 550 else
559 printk(KERN_ERR "playback tdm slot %d not supported\n", 551 printk(KERN_ERR "playback tdm slot %d not supported\n",
560 mcasp->tdm_slots); 552 mcasp->tdm_slots);
561 } else { 553 } else {
562 /* bit stream is MSB first with no delay */ 554 /* bit stream is MSB first with no delay */
563 /* DSP_B mode */ 555 /* DSP_B mode */
564 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG, 556 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
565 busel | RXORD); 557 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
566 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXTDM_REG, mask);
567 558
568 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32)) 559 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
569 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG, 560 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
570 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF)); 561 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
571 else 562 else
572 printk(KERN_ERR "capture tdm slot %d not supported\n", 563 printk(KERN_ERR "capture tdm slot %d not supported\n",
573 mcasp->tdm_slots); 564 mcasp->tdm_slots);
@@ -579,27 +570,24 @@ static void davinci_hw_dit_param(struct davinci_mcasp *mcasp)
579{ 570{
580 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 571 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
581 and LSB first */ 572 and LSB first */
582 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG, 573 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
583 TXROT(6) | TXSSZ(15));
584 574
585 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 575 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
586 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG, 576 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
587 AFSXE | FSXMOD(0x180));
588 577
589 /* Set the TX tdm : for all the slots */ 578 /* Set the TX tdm : for all the slots */
590 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 579 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
591 580
592 /* Set the TX clock controls : div = 1 and internal */ 581 /* Set the TX clock controls : div = 1 and internal */
593 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG, 582 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
594 ACLKXE | TX_ASYNC);
595 583
596 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 584 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
597 585
598 /* Only 44100 and 48000 are valid, both have the same setting */ 586 /* Only 44100 and 48000 are valid, both have the same setting */
599 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); 587 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
600 588
601 /* Enable the DIT */ 589 /* Enable the DIT */
602 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN); 590 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
603} 591}
604 592
605static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 593static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
@@ -1106,15 +1094,14 @@ static int davinci_mcasp_remove(struct platform_device *pdev)
1106static int davinci_mcasp_suspend(struct device *dev) 1094static int davinci_mcasp_suspend(struct device *dev)
1107{ 1095{
1108 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 1096 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1109 void __iomem *base = mcasp->base;
1110 1097
1111 mcasp->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG); 1098 mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
1112 mcasp->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG); 1099 mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
1113 mcasp->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG); 1100 mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
1114 mcasp->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG); 1101 mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
1115 mcasp->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG); 1102 mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
1116 mcasp->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG); 1103 mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
1117 mcasp->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG); 1104 mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1118 1105
1119 return 0; 1106 return 0;
1120} 1107}
@@ -1122,15 +1109,14 @@ static int davinci_mcasp_suspend(struct device *dev)
1122static int davinci_mcasp_resume(struct device *dev) 1109static int davinci_mcasp_resume(struct device *dev)
1123{ 1110{
1124 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 1111 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1125 void __iomem *base = mcasp->base; 1112
1126 1113 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
1127 mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl); 1114 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
1128 mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl); 1115 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
1129 mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt); 1116 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
1130 mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt); 1117 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
1131 mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl); 1118 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
1132 mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl); 1119 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1133 mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1134 1120
1135 return 0; 1121 return 0;
1136} 1122}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 07:53:18 -0500