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authorHugo Villeneuve <hugo.villeneuve@lyrtech.com>2008-11-08 13:26:09 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2008-11-10 06:41:18 -0500
commitb402dff8739cd82c58b632ba472caf26ae8741ed (patch)
tree5db47a61a8e772570ccd6cbfa9be3d24dac42368 /sound/soc/davinci/davinci-i2s.c
parent53599bbc30343f0cbfe750d2af19c9c45b841b82 (diff)
ASoC: Add Right-Justified mode and Codec clock master to davinci-i2s
The TI DVEVM board uses the SND_SOC_DAIFMT_CBM_CFM & I2S formats, but the Lyrtech SFFSDR board uses the SND_SOC_DAIFMT_CBM_CFS & RIGHT-JUSTIFIED formats. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/davinci/davinci-i2s.c')
-rw-r--r--sound/soc/davinci/davinci-i2s.c40
1 files changed, 33 insertions, 7 deletions
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index abb5fedb0b1e..d814ec8947e5 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -59,6 +59,7 @@
59#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) 59#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
60#define DAVINCI_MCBSP_PCR_FSRP (1 << 2) 60#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
61#define DAVINCI_MCBSP_PCR_FSXP (1 << 3) 61#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
62#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
62#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) 63#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
63#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) 64#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
64#define DAVINCI_MCBSP_PCR_FSRM (1 << 10) 65#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
@@ -171,6 +172,16 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
171 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, 172 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
172 DAVINCI_MCBSP_SRGR_FSGM); 173 DAVINCI_MCBSP_SRGR_FSGM);
173 break; 174 break;
175 case SND_SOC_DAIFMT_CBM_CFS:
176 /* McBSP CLKR pin is the input for the Sample Rate Generator.
177 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
178 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
179 DAVINCI_MCBSP_PCR_SCLKME |
180 DAVINCI_MCBSP_PCR_FSXM |
181 DAVINCI_MCBSP_PCR_FSRM);
182 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
183 DAVINCI_MCBSP_SRGR_FSGM);
184 break;
174 case SND_SOC_DAIFMT_CBM_CFM: 185 case SND_SOC_DAIFMT_CBM_CFM:
175 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0); 186 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
176 break; 187 break;
@@ -205,6 +216,28 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
205 return -EINVAL; 216 return -EINVAL;
206 } 217 }
207 218
219 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
220 case SND_SOC_DAIFMT_RIGHT_J:
221 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
222 DAVINCI_MCBSP_RCR_RFRLEN1(1) |
223 DAVINCI_MCBSP_RCR_RDATDLY(0));
224 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
225 DAVINCI_MCBSP_XCR_XFRLEN1(1) |
226 DAVINCI_MCBSP_XCR_XDATDLY(0) |
227 DAVINCI_MCBSP_XCR_XFIG);
228 break;
229 case SND_SOC_DAIFMT_I2S:
230 default:
231 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
232 DAVINCI_MCBSP_RCR_RFRLEN1(1) |
233 DAVINCI_MCBSP_RCR_RDATDLY(1));
234 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
235 DAVINCI_MCBSP_XCR_XFRLEN1(1) |
236 DAVINCI_MCBSP_XCR_XDATDLY(1) |
237 DAVINCI_MCBSP_XCR_XFIG);
238 break;
239 }
240
208 return 0; 241 return 0;
209} 242}
210 243
@@ -223,13 +256,6 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
223 DAVINCI_MCBSP_SPCR_RINTM(3) | 256 DAVINCI_MCBSP_SPCR_RINTM(3) |
224 DAVINCI_MCBSP_SPCR_XINTM(3) | 257 DAVINCI_MCBSP_SPCR_XINTM(3) |
225 DAVINCI_MCBSP_SPCR_FREE); 258 DAVINCI_MCBSP_SPCR_FREE);
226 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
227 DAVINCI_MCBSP_RCR_RFRLEN1(1) |
228 DAVINCI_MCBSP_RCR_RDATDLY(1));
229 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
230 DAVINCI_MCBSP_XCR_XFRLEN1(1) |
231 DAVINCI_MCBSP_XCR_XDATDLY(1) |
232 DAVINCI_MCBSP_XCR_XFIG);
233 259
234 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); 260 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
235 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG); 261 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);