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authorPeter Ujfalusi <peter.ujfalusi@nokia.com>2010-04-23 03:10:01 -0400
committerLiam Girdwood <lrg@slimlogic.co.uk>2010-04-26 10:16:39 -0400
commitf57d2cfaad0d6858d700b5671e01cf3aba6ef779 (patch)
tree592557de5cb0020fc6bc993296c3574a3a3ab233 /sound/soc/codecs
parent76f471274dc9acacd521f151ac9171fd7bbc34c3 (diff)
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes. DAC33 has FIFO depth status register(s), but it can not be used, since inside of pcm_pointer we can not send I2C commands. Timestamp based estimation need to be used. The method of calculating the delay depends on the active FIFO mode. Bypass mode: FIFO is bypassed, report 0 as delay Mode1: nSample fill mode. In this mode I need to use two timestamp ts1: taken when the interrupt has been received ts2: taken before writing to nSample register. Interrupts are coming when DAC33 FIFO depth goes under alarm threshold. Phase1: when we received the alarm threshold, but our workqueue has not been executed (safeguard phase). Just count the played out samples since ts1 and subtract it from the alarm threshold value. Phase2: During nSample burst (after writing to nSample register), count the played out samples since ts1, count the samples received since ts2 (in a burst). Estimate the FIFO depth using these and alarm threshold value. Phase3: Draining phase (after the burst read), count the played out samples since ts1. Estimate the FIFO depth using the nSample configuration and the alarm threshold value. Mode7: Threshold based fill mode. In this mode one timestamp is enough. ts1: taken when the interrupt has been received Interrupts are coming when DAC33 FIFO depth reaches upper threshold. Phase1: Draining phase (after the burst), counting the played out samples since ts1, and subtract it from the upper threshold value. Phase2: During burst operation. Using the pre calculated time needed to play out samples from the buffer during the drain period (from upper to lower threshold), move the time window to cover the estimated time from the burst start to the current time. Calculate the samples played out since lower threshold and also the samples received during the same time. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'sound/soc/codecs')
-rw-r--r--sound/soc/codecs/tlv320dac33.c222
1 files changed, 217 insertions, 5 deletions
diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index a8eb19b9b6c5..3eddaec728c1 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -55,6 +55,13 @@
55 55
56#define BURST_BASEFREQ_HZ 49152000 56#define BURST_BASEFREQ_HZ 49152000
57 57
58#define SAMPLES_TO_US(rate, samples) \
59 (1000000000 / ((rate * 1000) / samples))
60
61#define US_TO_SAMPLES(rate, us) \
62 (rate / (1000000 / us))
63
64
58static struct snd_soc_codec *tlv320dac33_codec; 65static struct snd_soc_codec *tlv320dac33_codec;
59 66
60enum dac33_state { 67enum dac33_state {
@@ -101,6 +108,14 @@ struct tlv320dac33_priv {
101 108
102 int keep_bclk; /* Keep the BCLK continuously running 109 int keep_bclk; /* Keep the BCLK continuously running
103 * in FIFO modes */ 110 * in FIFO modes */
111 spinlock_t lock;
112 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
113 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
114
115 unsigned int mode1_us_burst; /* Time to burst read n number of
116 * samples */
117 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
118
104 enum dac33_state state; 119 enum dac33_state state;
105}; 120};
106 121
@@ -390,10 +405,14 @@ static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
390 return 0; 405 return 0;
391 406
392 if (ucontrol->value.integer.value[0] < dac33->nsample_min || 407 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
393 ucontrol->value.integer.value[0] > dac33->nsample_max) 408 ucontrol->value.integer.value[0] > dac33->nsample_max) {
394 ret = -EINVAL; 409 ret = -EINVAL;
395 else 410 } else {
396 dac33->nsample = ucontrol->value.integer.value[0]; 411 dac33->nsample = ucontrol->value.integer.value[0];
412 /* Re calculate the burst time */
413 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
414 dac33->nsample);
415 }
397 416
398 return ret; 417 return ret;
399} 418}
@@ -564,6 +583,13 @@ static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
564 case DAC33_FIFO_MODE1: 583 case DAC33_FIFO_MODE1:
565 dac33_write16(codec, DAC33_NSAMPLE_MSB, 584 dac33_write16(codec, DAC33_NSAMPLE_MSB,
566 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold)); 585 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
586
587 /* Take the timestamps */
588 spin_lock_irq(&dac33->lock);
589 dac33->t_stamp2 = ktime_to_us(ktime_get());
590 dac33->t_stamp1 = dac33->t_stamp2;
591 spin_unlock_irq(&dac33->lock);
592
567 dac33_write16(codec, DAC33_PREFILL_MSB, 593 dac33_write16(codec, DAC33_PREFILL_MSB,
568 DAC33_THRREG(dac33->alarm_threshold)); 594 DAC33_THRREG(dac33->alarm_threshold));
569 /* Enable Alarm Threshold IRQ with a delay */ 595 /* Enable Alarm Threshold IRQ with a delay */
@@ -572,8 +598,18 @@ static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
572 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT); 598 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
573 break; 599 break;
574 case DAC33_FIFO_MODE7: 600 case DAC33_FIFO_MODE7:
601 /* Take the timestamp */
602 spin_lock_irq(&dac33->lock);
603 dac33->t_stamp1 = ktime_to_us(ktime_get());
604 /* Move back the timestamp with drain time */
605 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
606 spin_unlock_irq(&dac33->lock);
607
575 dac33_write16(codec, DAC33_PREFILL_MSB, 608 dac33_write16(codec, DAC33_PREFILL_MSB,
576 DAC33_THRREG(MODE7_LTHR)); 609 DAC33_THRREG(MODE7_LTHR));
610
611 /* Enable Upper Threshold IRQ */
612 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
577 break; 613 break;
578 default: 614 default:
579 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 615 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
@@ -590,6 +626,11 @@ static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
590 626
591 switch (dac33->fifo_mode) { 627 switch (dac33->fifo_mode) {
592 case DAC33_FIFO_MODE1: 628 case DAC33_FIFO_MODE1:
629 /* Take the timestamp */
630 spin_lock_irq(&dac33->lock);
631 dac33->t_stamp2 = ktime_to_us(ktime_get());
632 spin_unlock_irq(&dac33->lock);
633
593 dac33_write16(codec, DAC33_NSAMPLE_MSB, 634 dac33_write16(codec, DAC33_NSAMPLE_MSB,
594 DAC33_THRREG(dac33->nsample)); 635 DAC33_THRREG(dac33->nsample));
595 break; 636 break;
@@ -642,7 +683,13 @@ static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
642 struct snd_soc_codec *codec = dev; 683 struct snd_soc_codec *codec = dev;
643 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 684 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
644 685
645 queue_work(dac33->dac33_wq, &dac33->work); 686 spin_lock(&dac33->lock);
687 dac33->t_stamp1 = ktime_to_us(ktime_get());
688 spin_unlock(&dac33->lock);
689
690 /* Do not schedule the workqueue in Mode7 */
691 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
692 queue_work(dac33->dac33_wq, &dac33->work);
646 693
647 return IRQ_HANDLED; 694 return IRQ_HANDLED;
648} 695}
@@ -794,8 +841,8 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
794 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); 841 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
795 break; 842 break;
796 case DAC33_FIFO_MODE7: 843 case DAC33_FIFO_MODE7:
797 /* Disable all interrupts */ 844 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
798 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); 845 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
799 break; 846 break;
800 default: 847 default:
801 /* in FIFO bypass mode, the interrupts are not used */ 848 /* in FIFO bypass mode, the interrupts are not used */
@@ -930,6 +977,24 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream)
930 977
931 if (dac33->nsample > dac33->nsample_max) 978 if (dac33->nsample > dac33->nsample_max)
932 dac33->nsample = dac33->nsample_max; 979 dac33->nsample = dac33->nsample_max;
980
981 switch (dac33->fifo_mode) {
982 case DAC33_FIFO_MODE1:
983 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
984 dac33->nsample);
985 dac33->t_stamp1 = 0;
986 dac33->t_stamp2 = 0;
987 break;
988 case DAC33_FIFO_MODE7:
989 dac33->mode7_us_to_lthr =
990 SAMPLES_TO_US(substream->runtime->rate,
991 MODE7_UTHR - MODE7_LTHR + 1);
992 dac33->t_stamp1 = 0;
993 break;
994 default:
995 break;
996 }
997
933} 998}
934 999
935static int dac33_pcm_prepare(struct snd_pcm_substream *substream, 1000static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
@@ -974,6 +1039,151 @@ static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
974 return ret; 1039 return ret;
975} 1040}
976 1041
1042static snd_pcm_sframes_t dac33_dai_delay(
1043 struct snd_pcm_substream *substream,
1044 struct snd_soc_dai *dai)
1045{
1046 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1047 struct snd_soc_device *socdev = rtd->socdev;
1048 struct snd_soc_codec *codec = socdev->card->codec;
1049 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1050 unsigned long long t0, t1, t_now;
1051 unsigned int time_delta;
1052 int samples_out, samples_in, samples;
1053 snd_pcm_sframes_t delay = 0;
1054
1055 switch (dac33->fifo_mode) {
1056 case DAC33_FIFO_BYPASS:
1057 break;
1058 case DAC33_FIFO_MODE1:
1059 spin_lock(&dac33->lock);
1060 t0 = dac33->t_stamp1;
1061 t1 = dac33->t_stamp2;
1062 spin_unlock(&dac33->lock);
1063 t_now = ktime_to_us(ktime_get());
1064
1065 /* We have not started to fill the FIFO yet, delay is 0 */
1066 if (!t1)
1067 goto out;
1068
1069 if (t0 > t1) {
1070 /*
1071 * Phase 1:
1072 * After Alarm threshold, and before nSample write
1073 */
1074 time_delta = t_now - t0;
1075 samples_out = time_delta ? US_TO_SAMPLES(
1076 substream->runtime->rate,
1077 time_delta) : 0;
1078
1079 if (likely(dac33->alarm_threshold > samples_out))
1080 delay = dac33->alarm_threshold - samples_out;
1081 else
1082 delay = 0;
1083 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1084 /*
1085 * Phase 2:
1086 * After nSample write (during burst operation)
1087 */
1088 time_delta = t_now - t0;
1089 samples_out = time_delta ? US_TO_SAMPLES(
1090 substream->runtime->rate,
1091 time_delta) : 0;
1092
1093 time_delta = t_now - t1;
1094 samples_in = time_delta ? US_TO_SAMPLES(
1095 dac33->burst_rate,
1096 time_delta) : 0;
1097
1098 samples = dac33->alarm_threshold;
1099 samples += (samples_in - samples_out);
1100
1101 if (likely(samples > 0))
1102 delay = samples;
1103 else
1104 delay = 0;
1105 } else {
1106 /*
1107 * Phase 3:
1108 * After burst operation, before next alarm threshold
1109 */
1110 time_delta = t_now - t0;
1111 samples_out = time_delta ? US_TO_SAMPLES(
1112 substream->runtime->rate,
1113 time_delta) : 0;
1114
1115 samples_in = dac33->nsample;
1116 samples = dac33->alarm_threshold;
1117 samples += (samples_in - samples_out);
1118
1119 if (likely(samples > 0))
1120 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1121 DAC33_BUFFER_SIZE_SAMPLES : samples;
1122 else
1123 delay = 0;
1124 }
1125 break;
1126 case DAC33_FIFO_MODE7:
1127 spin_lock(&dac33->lock);
1128 t0 = dac33->t_stamp1;
1129 spin_unlock(&dac33->lock);
1130 t_now = ktime_to_us(ktime_get());
1131
1132 /* We have not started to fill the FIFO yet, delay is 0 */
1133 if (!t0)
1134 goto out;
1135
1136 if (t_now <= t0) {
1137 /*
1138 * Either the timestamps are messed or equal. Report
1139 * maximum delay
1140 */
1141 delay = MODE7_UTHR;
1142 goto out;
1143 }
1144
1145 time_delta = t_now - t0;
1146 if (time_delta <= dac33->mode7_us_to_lthr) {
1147 /*
1148 * Phase 1:
1149 * After burst (draining phase)
1150 */
1151 samples_out = US_TO_SAMPLES(
1152 substream->runtime->rate,
1153 time_delta);
1154
1155 if (likely(MODE7_UTHR > samples_out))
1156 delay = MODE7_UTHR - samples_out;
1157 else
1158 delay = 0;
1159 } else {
1160 /*
1161 * Phase 2:
1162 * During burst operation
1163 */
1164 time_delta = time_delta - dac33->mode7_us_to_lthr;
1165
1166 samples_out = US_TO_SAMPLES(
1167 substream->runtime->rate,
1168 time_delta);
1169 samples_in = US_TO_SAMPLES(
1170 dac33->burst_rate,
1171 time_delta);
1172 delay = MODE7_LTHR + samples_in - samples_out;
1173
1174 if (unlikely(delay > MODE7_UTHR))
1175 delay = MODE7_UTHR;
1176 }
1177 break;
1178 default:
1179 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1180 dac33->fifo_mode);
1181 break;
1182 }
1183out:
1184 return delay;
1185}
1186
977static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1187static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
978 int clk_id, unsigned int freq, int dir) 1188 int clk_id, unsigned int freq, int dir)
979{ 1189{
@@ -1185,6 +1395,7 @@ static struct snd_soc_dai_ops dac33_dai_ops = {
1185 .hw_params = dac33_hw_params, 1395 .hw_params = dac33_hw_params,
1186 .prepare = dac33_pcm_prepare, 1396 .prepare = dac33_pcm_prepare,
1187 .trigger = dac33_pcm_trigger, 1397 .trigger = dac33_pcm_trigger,
1398 .delay = dac33_dai_delay,
1188 .set_sysclk = dac33_set_dai_sysclk, 1399 .set_sysclk = dac33_set_dai_sysclk,
1189 .set_fmt = dac33_set_dai_fmt, 1400 .set_fmt = dac33_set_dai_fmt,
1190}; 1401};
@@ -1225,6 +1436,7 @@ static int __devinit dac33_i2c_probe(struct i2c_client *client,
1225 1436
1226 mutex_init(&codec->mutex); 1437 mutex_init(&codec->mutex);
1227 mutex_init(&dac33->mutex); 1438 mutex_init(&dac33->mutex);
1439 spin_lock_init(&dac33->lock);
1228 INIT_LIST_HEAD(&codec->dapm_widgets); 1440 INIT_LIST_HEAD(&codec->dapm_widgets);
1229 INIT_LIST_HEAD(&codec->dapm_paths); 1441 INIT_LIST_HEAD(&codec->dapm_paths);
1230 1442