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authorMark Brown <broonie@opensource.wolfsonmicro.com>2008-06-05 08:49:33 -0400
committerTakashi Iwai <tiwai@suse.de>2008-06-06 05:54:32 -0400
commitf10485e79882bf09cf442a673511154987b43e3b (patch)
treed778a95b6d28e6b3a25c49d0208b40789df827e9 /sound/soc/codecs
parent5d421516670e8009436e299bd25cff1a6d3a4707 (diff)
[ALSA] ASoC: Add WM8990 driver
The WM8990 is a highly integrated ultra-low power hi-fi codec designed for handsets rich in multimedia features such as mobile TV, digital audio playback and gaming. The bulk of this driver was written by Liam Girdwood with some additional development and updates for new ASoC APIs by me. Signed-off-by: Liam Girdwood <lg@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/soc/codecs')
-rw-r--r--sound/soc/codecs/Kconfig3
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/wm8990.c1645
-rw-r--r--sound/soc/codecs/wm8990.h832
4 files changed, 2482 insertions, 0 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index ef400b363440..f439138db843 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -17,6 +17,9 @@ config SND_SOC_WM8750
17config SND_SOC_WM8753 17config SND_SOC_WM8753
18 tristate 18 tristate
19 19
20config SND_SOC_WM8990
21 tristate
22
20config SND_SOC_WM9712 23config SND_SOC_WM9712
21 tristate 24 tristate
22 25
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index b92c66541663..d9826f35d8c0 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -4,6 +4,7 @@ snd-soc-wm8510-objs := wm8510.o
4snd-soc-wm8731-objs := wm8731.o 4snd-soc-wm8731-objs := wm8731.o
5snd-soc-wm8750-objs := wm8750.o 5snd-soc-wm8750-objs := wm8750.o
6snd-soc-wm8753-objs := wm8753.o 6snd-soc-wm8753-objs := wm8753.o
7snd-soc-wm8990-objs := wm8990.o
7snd-soc-wm9712-objs := wm9712.o 8snd-soc-wm9712-objs := wm9712.o
8snd-soc-wm9713-objs := wm9713.o 9snd-soc-wm9713-objs := wm9713.o
9snd-soc-cs4270-objs := cs4270.o 10snd-soc-cs4270-objs := cs4270.o
@@ -15,6 +16,7 @@ obj-$(CONFIG_SND_SOC_WM8510) += snd-soc-wm8510.o
15obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o 16obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o
16obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o 17obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o
17obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o 18obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o
19obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
18obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o 20obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o
19obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o 21obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
20obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o 22obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
new file mode 100644
index 000000000000..a7d25e2f2522
--- /dev/null
+++ b/sound/soc/codecs/wm8990.c
@@ -0,0 +1,1645 @@
1/*
2 * wm8990.c -- WM8990 ALSA Soc Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * lg@opensource.wolfsonmicro.com or linux@wolfsonmicro.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <asm/div64.h>
30
31#include "wm8990.h"
32
33#define AUDIO_NAME "wm8990"
34#define WM8990_VERSION "0.2"
35
36/*
37 * Debug
38 */
39
40#define WM8990_DEBUG 0
41
42#ifdef WM8990_DEBUG
43#define dbg(format, arg...) \
44 printk(KERN_DEBUG AUDIO_NAME ": " format "\n" , ## arg)
45#else
46#define dbg(format, arg...) do {} while (0)
47#endif
48#define err(format, arg...) \
49 printk(KERN_ERR AUDIO_NAME ": " format "\n" , ## arg)
50#define info(format, arg...) \
51 printk(KERN_INFO AUDIO_NAME ": " format "\n" , ## arg)
52#define warn(format, arg...) \
53 printk(KERN_WARNING AUDIO_NAME ": " format "\n" , ## arg)
54
55/* codec private data */
56struct wm8990_priv {
57 unsigned int sysclk;
58 unsigned int pcmclk;
59};
60
61/*
62 * wm8990 register cache. Note that register 0 is not included in the
63 * cache.
64 */
65static const u16 wm8990_reg[] = {
66 0x8990, /* R0 - Reset */
67 0x0000, /* R1 - Power Management (1) */
68 0x6000, /* R2 - Power Management (2) */
69 0x0000, /* R3 - Power Management (3) */
70 0x4050, /* R4 - Audio Interface (1) */
71 0x4000, /* R5 - Audio Interface (2) */
72 0x01C8, /* R6 - Clocking (1) */
73 0x0000, /* R7 - Clocking (2) */
74 0x0040, /* R8 - Audio Interface (3) */
75 0x0040, /* R9 - Audio Interface (4) */
76 0x0004, /* R10 - DAC CTRL */
77 0x00C0, /* R11 - Left DAC Digital Volume */
78 0x00C0, /* R12 - Right DAC Digital Volume */
79 0x0000, /* R13 - Digital Side Tone */
80 0x0100, /* R14 - ADC CTRL */
81 0x00C0, /* R15 - Left ADC Digital Volume */
82 0x00C0, /* R16 - Right ADC Digital Volume */
83 0x0000, /* R17 */
84 0x0000, /* R18 - GPIO CTRL 1 */
85 0x1000, /* R19 - GPIO1 & GPIO2 */
86 0x1010, /* R20 - GPIO3 & GPIO4 */
87 0x1010, /* R21 - GPIO5 & GPIO6 */
88 0x8000, /* R22 - GPIOCTRL 2 */
89 0x0800, /* R23 - GPIO_POL */
90 0x008B, /* R24 - Left Line Input 1&2 Volume */
91 0x008B, /* R25 - Left Line Input 3&4 Volume */
92 0x008B, /* R26 - Right Line Input 1&2 Volume */
93 0x008B, /* R27 - Right Line Input 3&4 Volume */
94 0x0000, /* R28 - Left Output Volume */
95 0x0000, /* R29 - Right Output Volume */
96 0x0066, /* R30 - Line Outputs Volume */
97 0x0022, /* R31 - Out3/4 Volume */
98 0x0079, /* R32 - Left OPGA Volume */
99 0x0079, /* R33 - Right OPGA Volume */
100 0x0003, /* R34 - Speaker Volume */
101 0x0003, /* R35 - ClassD1 */
102 0x0000, /* R36 */
103 0x0100, /* R37 - ClassD3 */
104 0x0000, /* R38 */
105 0x0000, /* R39 - Input Mixer1 */
106 0x0000, /* R40 - Input Mixer2 */
107 0x0000, /* R41 - Input Mixer3 */
108 0x0000, /* R42 - Input Mixer4 */
109 0x0000, /* R43 - Input Mixer5 */
110 0x0000, /* R44 - Input Mixer6 */
111 0x0000, /* R45 - Output Mixer1 */
112 0x0000, /* R46 - Output Mixer2 */
113 0x0000, /* R47 - Output Mixer3 */
114 0x0000, /* R48 - Output Mixer4 */
115 0x0000, /* R49 - Output Mixer5 */
116 0x0000, /* R50 - Output Mixer6 */
117 0x0180, /* R51 - Out3/4 Mixer */
118 0x0000, /* R52 - Line Mixer1 */
119 0x0000, /* R53 - Line Mixer2 */
120 0x0000, /* R54 - Speaker Mixer */
121 0x0000, /* R55 - Additional Control */
122 0x0000, /* R56 - AntiPOP1 */
123 0x0000, /* R57 - AntiPOP2 */
124 0x0000, /* R58 - MICBIAS */
125 0x0000, /* R59 */
126 0x0008, /* R60 - PLL1 */
127 0x0031, /* R61 - PLL2 */
128 0x0026, /* R62 - PLL3 */
129};
130
131/*
132 * read wm8990 register cache
133 */
134static inline unsigned int wm8990_read_reg_cache(struct snd_soc_codec *codec,
135 unsigned int reg)
136{
137 u16 *cache = codec->reg_cache;
138 BUG_ON(reg > (ARRAY_SIZE(wm8990_reg)) - 1);
139 return cache[reg];
140}
141
142/*
143 * write wm8990 register cache
144 */
145static inline void wm8990_write_reg_cache(struct snd_soc_codec *codec,
146 unsigned int reg, unsigned int value)
147{
148 u16 *cache = codec->reg_cache;
149 BUG_ON(reg > (ARRAY_SIZE(wm8990_reg)) - 1);
150
151 /* Reset register is uncached */
152 if (reg == 0)
153 return;
154
155 cache[reg] = value;
156}
157
158/*
159 * write to the wm8990 register space
160 */
161static int wm8990_write(struct snd_soc_codec *codec, unsigned int reg,
162 unsigned int value)
163{
164 u8 data[3];
165
166 data[0] = reg & 0xFF;
167 data[1] = (value >> 8) & 0xFF;
168 data[2] = value & 0xFF;
169
170 wm8990_write_reg_cache(codec, reg, value);
171
172 if (codec->hw_write(codec->control_data, data, 3) == 2)
173 return 0;
174 else
175 return -EIO;
176}
177
178#define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0)
179
180static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600);
181
182static const DECLARE_TLV_DB_LINEAR(in_pga_tlv, -1650, 3000);
183
184static const DECLARE_TLV_DB_LINEAR(out_mix_tlv, 0, -2100);
185
186static const DECLARE_TLV_DB_LINEAR(out_pga_tlv, -7300, 600);
187
188static const DECLARE_TLV_DB_LINEAR(out_omix_tlv, -600, 0);
189
190static const DECLARE_TLV_DB_LINEAR(out_dac_tlv, -7163, 0);
191
192static const DECLARE_TLV_DB_LINEAR(in_adc_tlv, -7163, 1763);
193
194static const DECLARE_TLV_DB_LINEAR(out_sidetone_tlv, -3600, 0);
195
196static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
197 struct snd_ctl_elem_value *ucontrol)
198{
199 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
200 int reg = kcontrol->private_value & 0xff;
201 int ret;
202 u16 val;
203
204 ret = snd_soc_put_volsw(kcontrol, ucontrol);
205 if (ret < 0)
206 return ret;
207
208 /* now hit the volume update bits (always bit 8) */
209 val = wm8990_read_reg_cache(codec, reg);
210 return wm8990_write(codec, reg, val | 0x0100);
211}
212
213#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
214 tlv_array) {\
215 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
216 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
217 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
218 .tlv.p = (tlv_array), \
219 .info = snd_soc_info_volsw, \
220 .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \
221 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
222
223
224static const char *wm8990_digital_sidetone[] =
225 {"None", "Left ADC", "Right ADC", "Reserved"};
226
227static const struct soc_enum wm8990_left_digital_sidetone_enum =
228SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
229 WM8990_ADC_TO_DACL_SHIFT,
230 WM8990_ADC_TO_DACL_MASK,
231 wm8990_digital_sidetone);
232
233static const struct soc_enum wm8990_right_digital_sidetone_enum =
234SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
235 WM8990_ADC_TO_DACR_SHIFT,
236 WM8990_ADC_TO_DACR_MASK,
237 wm8990_digital_sidetone);
238
239static const char *wm8990_adcmode[] =
240 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
241
242static const struct soc_enum wm8990_right_adcmode_enum =
243SOC_ENUM_SINGLE(WM8990_ADC_CTRL,
244 WM8990_ADC_HPF_CUT_SHIFT,
245 WM8990_ADC_HPF_CUT_MASK,
246 wm8990_adcmode);
247
248static const struct snd_kcontrol_new wm8990_snd_controls[] = {
249/* INMIXL */
250SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
251SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
252/* INMIXR */
253SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
254SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
255
256/* LOMIX */
257SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
258 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
259SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
260 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
261SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
262 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
263SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
264 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
265SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
266 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
267SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
268 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
269
270/* ROMIX */
271SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
272 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
273SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
274 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
275SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
276 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
277SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
278 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
279SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
280 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
281SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
282 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
283
284/* LOUT */
285SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
286 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
287SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
288
289/* ROUT */
290SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
291 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
292SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
293
294/* LOPGA */
295SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
296 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
297SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
298 WM8990_LOPGAZC_BIT, 1, 0),
299
300/* ROPGA */
301SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
302 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
303SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
304 WM8990_ROPGAZC_BIT, 1, 0),
305
306SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
307 WM8990_LONMUTE_BIT, 1, 0),
308SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
309 WM8990_LOPMUTE_BIT, 1, 0),
310SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
311 WM8990_LOATTN_BIT, 1, 0),
312SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
313 WM8990_RONMUTE_BIT, 1, 0),
314SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
315 WM8990_ROPMUTE_BIT, 1, 0),
316SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
317 WM8990_ROATTN_BIT, 1, 0),
318
319SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
320 WM8990_OUT3MUTE_BIT, 1, 0),
321SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
322 WM8990_OUT3ATTN_BIT, 1, 0),
323
324SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
325 WM8990_OUT4MUTE_BIT, 1, 0),
326SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
327 WM8990_OUT4ATTN_BIT, 1, 0),
328
329SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
330 WM8990_CDMODE_BIT, 1, 0),
331
332SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
333 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0),
334SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
335 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
336SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
337 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
338
339SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
340 WM8990_LEFT_DAC_DIGITAL_VOLUME,
341 WM8990_DACL_VOL_SHIFT,
342 WM8990_DACL_VOL_MASK,
343 0,
344 out_dac_tlv),
345
346SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
347 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
348 WM8990_DACR_VOL_SHIFT,
349 WM8990_DACR_VOL_MASK,
350 0,
351 out_dac_tlv),
352
353SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
354SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
355
356SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
357 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
358 out_sidetone_tlv),
359SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
360 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
361 out_sidetone_tlv),
362
363SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
364 WM8990_ADC_HPF_ENA_BIT, 1, 0),
365
366SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
367
368SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
369 WM8990_LEFT_ADC_DIGITAL_VOLUME,
370 WM8990_ADCL_VOL_SHIFT,
371 WM8990_ADCL_VOL_MASK,
372 0,
373 in_adc_tlv),
374
375SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
376 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
377 WM8990_ADCR_VOL_SHIFT,
378 WM8990_ADCR_VOL_MASK,
379 0,
380 in_adc_tlv),
381
382SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
383 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
384 WM8990_LIN12VOL_SHIFT,
385 WM8990_LIN12VOL_MASK,
386 0,
387 in_pga_tlv),
388
389SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
390 WM8990_LI12ZC_BIT, 1, 0),
391
392SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
393 WM8990_LI12MUTE_BIT, 1, 0),
394
395SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
396 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
397 WM8990_LIN34VOL_SHIFT,
398 WM8990_LIN34VOL_MASK,
399 0,
400 in_pga_tlv),
401
402SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
403 WM8990_LI34ZC_BIT, 1, 0),
404
405SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
406 WM8990_LI34MUTE_BIT, 1, 0),
407
408SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
409 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
410 WM8990_RIN12VOL_SHIFT,
411 WM8990_RIN12VOL_MASK,
412 0,
413 in_pga_tlv),
414
415SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
416 WM8990_RI12ZC_BIT, 1, 0),
417
418SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
419 WM8990_RI12MUTE_BIT, 1, 0),
420
421SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
422 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
423 WM8990_RIN34VOL_SHIFT,
424 WM8990_RIN34VOL_MASK,
425 0,
426 in_pga_tlv),
427
428SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
429 WM8990_RI34ZC_BIT, 1, 0),
430
431SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
432 WM8990_RI34MUTE_BIT, 1, 0),
433
434};
435
436/* add non dapm controls */
437static int wm8990_add_controls(struct snd_soc_codec *codec)
438{
439 int err, i;
440
441 for (i = 0; i < ARRAY_SIZE(wm8990_snd_controls); i++) {
442 err = snd_ctl_add(codec->card,
443 snd_soc_cnew(&wm8990_snd_controls[i], codec,
444 NULL));
445 if (err < 0)
446 return err;
447 }
448 return 0;
449}
450
451/*
452 * _DAPM_ Controls
453 */
454
455static int inmixer_event(struct snd_soc_dapm_widget *w,
456 struct snd_kcontrol *kcontrol, int event)
457{
458 u16 reg, fakepower;
459
460 reg = wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2);
461 fakepower = wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS);
462
463 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
464 (1 << WM8990_AINLMUX_PWR_BIT))) {
465 reg |= WM8990_AINL_ENA;
466 } else {
467 reg &= ~WM8990_AINL_ENA;
468 }
469
470 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) |
471 (1 << WM8990_AINRMUX_PWR_BIT))) {
472 reg |= WM8990_AINR_ENA;
473 } else {
474 reg &= ~WM8990_AINL_ENA;
475 }
476 wm8990_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
477
478 return 0;
479}
480
481static int outmixer_event(struct snd_soc_dapm_widget *w,
482 struct snd_kcontrol *kcontrol, int event)
483{
484 u32 reg_shift = kcontrol->private_value & 0xfff;
485 int ret = 0;
486 u16 reg;
487
488 switch (reg_shift) {
489 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
490 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1);
491 if (reg & WM8990_LDLO) {
492 printk(KERN_WARNING
493 "Cannot set as Output Mixer 1 LDLO Set\n");
494 ret = -1;
495 }
496 break;
497 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
498 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER2);
499 if (reg & WM8990_RDRO) {
500 printk(KERN_WARNING
501 "Cannot set as Output Mixer 2 RDRO Set\n");
502 ret = -1;
503 }
504 break;
505 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
506 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER);
507 if (reg & WM8990_LDSPK) {
508 printk(KERN_WARNING
509 "Cannot set as Speaker Mixer LDSPK Set\n");
510 ret = -1;
511 }
512 break;
513 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
514 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER);
515 if (reg & WM8990_RDSPK) {
516 printk(KERN_WARNING
517 "Cannot set as Speaker Mixer RDSPK Set\n");
518 ret = -1;
519 }
520 break;
521 }
522
523 return ret;
524}
525
526/* INMIX dB values */
527static const unsigned int in_mix_tlv[] = {
528 TLV_DB_RANGE_HEAD(1),
529 0, 7, TLV_DB_LINEAR_ITEM(-1200, 600),
530};
531
532/* Left In PGA Connections */
533static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
534SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
535SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
536};
537
538static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
539SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
540SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
541};
542
543/* Right In PGA Connections */
544static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
545SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
546SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
547};
548
549static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
550SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
551SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
552};
553
554/* INMIXL */
555static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
556SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
557 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
558SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
559 7, 0, in_mix_tlv),
560SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
561 1, 0),
562SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
563 1, 0),
564};
565
566/* INMIXR */
567static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
568SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
569 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
570SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
571 7, 0, in_mix_tlv),
572SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
573 1, 0),
574SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
575 1, 0),
576};
577
578/* AINLMUX */
579static const char *wm8990_ainlmux[] =
580 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
581
582static const struct soc_enum wm8990_ainlmux_enum =
583SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
584 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux);
585
586static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
587SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
588
589/* DIFFINL */
590
591/* AINRMUX */
592static const char *wm8990_ainrmux[] =
593 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
594
595static const struct soc_enum wm8990_ainrmux_enum =
596SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
597 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux);
598
599static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
600SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
601
602/* RXVOICE */
603static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
604SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
605 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
606SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
607 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
608};
609
610/* LOMIX */
611static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
612SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
613 WM8990_LRBLO_BIT, 1, 0),
614SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
615 WM8990_LLBLO_BIT, 1, 0),
616SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
617 WM8990_LRI3LO_BIT, 1, 0),
618SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
619 WM8990_LLI3LO_BIT, 1, 0),
620SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
621 WM8990_LR12LO_BIT, 1, 0),
622SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
623 WM8990_LL12LO_BIT, 1, 0),
624SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
625 WM8990_LDLO_BIT, 1, 0),
626};
627
628/* ROMIX */
629static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
630SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
631 WM8990_RLBRO_BIT, 1, 0),
632SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
633 WM8990_RRBRO_BIT, 1, 0),
634SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
635 WM8990_RLI3RO_BIT, 1, 0),
636SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
637 WM8990_RRI3RO_BIT, 1, 0),
638SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
639 WM8990_RL12RO_BIT, 1, 0),
640SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
641 WM8990_RR12RO_BIT, 1, 0),
642SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
643 WM8990_RDRO_BIT, 1, 0),
644};
645
646/* LONMIX */
647static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
648SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
649 WM8990_LLOPGALON_BIT, 1, 0),
650SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
651 WM8990_LROPGALON_BIT, 1, 0),
652SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
653 WM8990_LOPLON_BIT, 1, 0),
654};
655
656/* LOPMIX */
657static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
658SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
659 WM8990_LR12LOP_BIT, 1, 0),
660SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
661 WM8990_LL12LOP_BIT, 1, 0),
662SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
663 WM8990_LLOPGALOP_BIT, 1, 0),
664};
665
666/* RONMIX */
667static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
668SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
669 WM8990_RROPGARON_BIT, 1, 0),
670SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
671 WM8990_RLOPGARON_BIT, 1, 0),
672SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
673 WM8990_ROPRON_BIT, 1, 0),
674};
675
676/* ROPMIX */
677static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
678SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
679 WM8990_RL12ROP_BIT, 1, 0),
680SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
681 WM8990_RR12ROP_BIT, 1, 0),
682SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
683 WM8990_RROPGAROP_BIT, 1, 0),
684};
685
686/* OUT3MIX */
687static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
688SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
689 WM8990_LI4O3_BIT, 1, 0),
690SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
691 WM8990_LPGAO3_BIT, 1, 0),
692};
693
694/* OUT4MIX */
695static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
696SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
697 WM8990_RPGAO4_BIT, 1, 0),
698SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
699 WM8990_RI4O4_BIT, 1, 0),
700};
701
702/* SPKMIX */
703static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
704SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
705 WM8990_LI2SPK_BIT, 1, 0),
706SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
707 WM8990_LB2SPK_BIT, 1, 0),
708SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
709 WM8990_LOPGASPK_BIT, 1, 0),
710SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
711 WM8990_LDSPK_BIT, 1, 0),
712SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
713 WM8990_RDSPK_BIT, 1, 0),
714SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
715 WM8990_ROPGASPK_BIT, 1, 0),
716SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
717 WM8990_RL12ROP_BIT, 1, 0),
718SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
719 WM8990_RI2SPK_BIT, 1, 0),
720};
721
722static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
723/* Input Side */
724/* Input Lines */
725SND_SOC_DAPM_INPUT("LIN1"),
726SND_SOC_DAPM_INPUT("LIN2"),
727SND_SOC_DAPM_INPUT("LIN3"),
728SND_SOC_DAPM_INPUT("LIN4/RXN"),
729SND_SOC_DAPM_INPUT("RIN3"),
730SND_SOC_DAPM_INPUT("RIN4/RXP"),
731SND_SOC_DAPM_INPUT("RIN1"),
732SND_SOC_DAPM_INPUT("RIN2"),
733SND_SOC_DAPM_INPUT("Internal ADC Source"),
734
735/* DACs */
736SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
737 WM8990_ADCL_ENA_BIT, 0),
738SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
739 WM8990_ADCR_ENA_BIT, 0),
740
741/* Input PGAs */
742SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
743 0, &wm8990_dapm_lin12_pga_controls[0],
744 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
745SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
746 0, &wm8990_dapm_lin34_pga_controls[0],
747 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
748SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
749 0, &wm8990_dapm_rin12_pga_controls[0],
750 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
751SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
752 0, &wm8990_dapm_rin34_pga_controls[0],
753 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
754
755/* INMIXL */
756SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0,
757 &wm8990_dapm_inmixl_controls[0],
758 ARRAY_SIZE(wm8990_dapm_inmixl_controls),
759 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
760
761/* AINLMUX */
762SND_SOC_DAPM_MUX_E("AILNMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0,
763 &wm8990_dapm_ainlmux_controls, inmixer_event,
764 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
765
766/* INMIXR */
767SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0,
768 &wm8990_dapm_inmixr_controls[0],
769 ARRAY_SIZE(wm8990_dapm_inmixr_controls),
770 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
771
772/* AINRMUX */
773SND_SOC_DAPM_MUX_E("AIRNMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0,
774 &wm8990_dapm_ainrmux_controls, inmixer_event,
775 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
776
777/* Output Side */
778/* DACs */
779SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
780 WM8990_DACL_ENA_BIT, 0),
781SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
782 WM8990_DACR_ENA_BIT, 0),
783
784/* LOMIX */
785SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
786 0, &wm8990_dapm_lomix_controls[0],
787 ARRAY_SIZE(wm8990_dapm_lomix_controls),
788 outmixer_event, SND_SOC_DAPM_PRE_REG),
789
790/* LONMIX */
791SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
792 &wm8990_dapm_lonmix_controls[0],
793 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
794
795/* LOPMIX */
796SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
797 &wm8990_dapm_lopmix_controls[0],
798 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
799
800/* OUT3MIX */
801SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
802 &wm8990_dapm_out3mix_controls[0],
803 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
804
805/* SPKMIX */
806SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
807 &wm8990_dapm_spkmix_controls[0],
808 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
809 SND_SOC_DAPM_PRE_REG),
810
811/* OUT4MIX */
812SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
813 &wm8990_dapm_out4mix_controls[0],
814 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
815
816/* ROPMIX */
817SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
818 &wm8990_dapm_ropmix_controls[0],
819 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
820
821/* RONMIX */
822SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
823 &wm8990_dapm_ronmix_controls[0],
824 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
825
826/* ROMIX */
827SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
828 0, &wm8990_dapm_romix_controls[0],
829 ARRAY_SIZE(wm8990_dapm_romix_controls),
830 outmixer_event, SND_SOC_DAPM_PRE_REG),
831
832/* LOUT PGA */
833SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
834 NULL, 0),
835
836/* ROUT PGA */
837SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
838 NULL, 0),
839
840/* LOPGA */
841SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
842 NULL, 0),
843
844/* ROPGA */
845SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
846 NULL, 0),
847
848/* MICBIAS */
849SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1,
850 WM8990_MICBIAS_ENA_BIT, 0),
851
852SND_SOC_DAPM_OUTPUT("LON"),
853SND_SOC_DAPM_OUTPUT("LOP"),
854SND_SOC_DAPM_OUTPUT("OUT3"),
855SND_SOC_DAPM_OUTPUT("LOUT"),
856SND_SOC_DAPM_OUTPUT("SPKN"),
857SND_SOC_DAPM_OUTPUT("SPKP"),
858SND_SOC_DAPM_OUTPUT("ROUT"),
859SND_SOC_DAPM_OUTPUT("OUT4"),
860SND_SOC_DAPM_OUTPUT("ROP"),
861SND_SOC_DAPM_OUTPUT("RON"),
862
863SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
864};
865
866static const struct snd_soc_dapm_route audio_map[] = {
867 /* Make DACs turn on when playing even if not mixed into any outputs */
868 {"Internal DAC Sink", NULL, "Left DAC"},
869 {"Internal DAC Sink", NULL, "Right DAC"},
870
871 /* Make ADCs turn on when recording even if not mixed from any inputs */
872 {"Left ADC", NULL, "Internal ADC Source"},
873 {"Right ADC", NULL, "Internal ADC Source"},
874
875 /* Input Side */
876 /* LIN12 PGA */
877 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
878 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
879 /* LIN34 PGA */
880 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
881 {"LIN34 PGA", "LIN4 Switch", "LIN4"},
882 /* INMIXL */
883 {"INMIXL", "Record Left Volume", "LOMIX"},
884 {"INMIXL", "LIN2 Volume", "LIN2"},
885 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
886 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
887 /* AILNMUX */
888 {"AILNMUX", "INMIXL Mix", "INMIXL"},
889 {"AILNMUX", "DIFFINL Mix", "LIN12PGA"},
890 {"AILNMUX", "DIFFINL Mix", "LIN34PGA"},
891 {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
892 {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
893 /* ADC */
894 {"Left ADC", NULL, "AILNMUX"},
895
896 /* RIN12 PGA */
897 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
898 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
899 /* RIN34 PGA */
900 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
901 {"RIN34 PGA", "RIN4 Switch", "RIN4"},
902 /* INMIXL */
903 {"INMIXR", "Record Right Volume", "ROMIX"},
904 {"INMIXR", "RIN2 Volume", "RIN2"},
905 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
906 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
907 /* AIRNMUX */
908 {"AIRNMUX", "INMIXR Mix", "INMIXR"},
909 {"AIRNMUX", "DIFFINR Mix", "RIN12PGA"},
910 {"AIRNMUX", "DIFFINR Mix", "RIN34PGA"},
911 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXN"},
912 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
913 /* ADC */
914 {"Right ADC", NULL, "AIRNMUX"},
915
916 /* LOMIX */
917 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
918 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
919 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
920 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
921 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
922 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
923 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
924
925 /* ROMIX */
926 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
927 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
928 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
929 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
930 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
931 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
932 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
933
934 /* SPKMIX */
935 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
936 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
937 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
938 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
939 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
940 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
941 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
942 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
943
944 /* LONMIX */
945 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
946 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
947 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
948
949 /* LOPMIX */
950 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
951 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
952 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
953
954 /* OUT3MIX */
955 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXP"},
956 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
957
958 /* OUT4MIX */
959 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
960 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
961
962 /* RONMIX */
963 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
964 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
965 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
966
967 /* ROPMIX */
968 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
969 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
970 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
971
972 /* Out Mixer PGAs */
973 {"LOPGA", NULL, "LOMIX"},
974 {"ROPGA", NULL, "ROMIX"},
975
976 {"LOUT PGA", NULL, "LOMIX"},
977 {"ROUT PGA", NULL, "ROMIX"},
978
979 /* Output Pins */
980 {"LON", NULL, "LONMIX"},
981 {"LOP", NULL, "LOPMIX"},
982 {"OUT", NULL, "OUT3MIX"},
983 {"LOUT", NULL, "LOUT PGA"},
984 {"SPKN", NULL, "SPKMIX"},
985 {"ROUT", NULL, "ROUT PGA"},
986 {"OUT4", NULL, "OUT4MIX"},
987 {"ROP", NULL, "ROPMIX"},
988 {"RON", NULL, "RONMIX"},
989};
990
991static int wm8990_add_widgets(struct snd_soc_codec *codec)
992{
993 snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets,
994 ARRAY_SIZE(wm8990_dapm_widgets));
995
996 /* set up the WM8990 audio map */
997 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
998
999 snd_soc_dapm_new_widgets(codec);
1000 return 0;
1001}
1002
1003/* PLL divisors */
1004struct _pll_div {
1005 u32 div2;
1006 u32 n;
1007 u32 k;
1008};
1009
1010/* The size in bits of the pll divide multiplied by 10
1011 * to allow rounding later */
1012#define FIXED_PLL_SIZE ((1 << 16) * 10)
1013
1014static void pll_factors(struct _pll_div *pll_div, unsigned int target,
1015 unsigned int source)
1016{
1017 u64 Kpart;
1018 unsigned int K, Ndiv, Nmod;
1019
1020
1021 Ndiv = target / source;
1022 if (Ndiv < 6) {
1023 source >>= 1;
1024 pll_div->div2 = 1;
1025 Ndiv = target / source;
1026 } else
1027 pll_div->div2 = 0;
1028
1029 if ((Ndiv < 6) || (Ndiv > 12))
1030 printk(KERN_WARNING
1031 "WM8990 N value outwith recommended range! N = %d\n", Ndiv);
1032
1033 pll_div->n = Ndiv;
1034 Nmod = target % source;
1035 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
1036
1037 do_div(Kpart, source);
1038
1039 K = Kpart & 0xFFFFFFFF;
1040
1041 /* Check if we need to round */
1042 if ((K % 10) >= 5)
1043 K += 5;
1044
1045 /* Move down to proper range now rounding is done */
1046 K /= 10;
1047
1048 pll_div->k = K;
1049}
1050
1051static int wm8990_set_dai_pll(struct snd_soc_codec_dai *codec_dai,
1052 int pll_id, unsigned int freq_in, unsigned int freq_out)
1053{
1054 u16 reg;
1055 struct snd_soc_codec *codec = codec_dai->codec;
1056 struct _pll_div pll_div;
1057
1058 if (freq_in && freq_out) {
1059 pll_factors(&pll_div, freq_out * 4, freq_in);
1060
1061 /* Turn on PLL */
1062 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
1063 reg |= WM8990_PLL_ENA;
1064 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1065
1066 /* sysclk comes from PLL */
1067 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2);
1068 wm8990_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC);
1069
1070 /* set up N , fractional mode and pre-divisor if neccessary */
1071 wm8990_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
1072 (pll_div.div2?WM8990_PRESCALE:0));
1073 wm8990_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
1074 wm8990_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
1075 } else {
1076 /* Turn on PLL */
1077 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
1078 reg &= ~WM8990_PLL_ENA;
1079 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1080 }
1081 return 0;
1082}
1083
1084/*
1085 * Clock after PLL and dividers
1086 */
1087static int wm8990_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
1088 int clk_id, unsigned int freq, int dir)
1089{
1090 struct snd_soc_codec *codec = codec_dai->codec;
1091 struct wm8990_priv *wm8990 = codec->private_data;
1092
1093 wm8990->sysclk = freq;
1094 return 0;
1095}
1096
1097/*
1098 * Set's ADC and Voice DAC format.
1099 */
1100static int wm8990_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
1101 unsigned int fmt)
1102{
1103 struct snd_soc_codec *codec = codec_dai->codec;
1104 u16 audio1, audio3;
1105
1106 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1);
1107 audio3 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_3);
1108
1109 /* set master/slave audio interface */
1110 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1111 case SND_SOC_DAIFMT_CBS_CFS:
1112 audio3 &= ~WM8990_AIF_MSTR1;
1113 break;
1114 case SND_SOC_DAIFMT_CBM_CFM:
1115 audio3 |= WM8990_AIF_MSTR1;
1116 break;
1117 default:
1118 return -EINVAL;
1119 }
1120
1121 audio1 &= ~WM8990_AIF_FMT_MASK;
1122
1123 /* interface format */
1124 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1125 case SND_SOC_DAIFMT_I2S:
1126 audio1 |= WM8990_AIF_TMF_I2S;
1127 audio1 &= ~WM8990_AIF_LRCLK_INV;
1128 break;
1129 case SND_SOC_DAIFMT_RIGHT_J:
1130 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1131 audio1 &= ~WM8990_AIF_LRCLK_INV;
1132 break;
1133 case SND_SOC_DAIFMT_LEFT_J:
1134 audio1 |= WM8990_AIF_TMF_LEFTJ;
1135 audio1 &= ~WM8990_AIF_LRCLK_INV;
1136 break;
1137 case SND_SOC_DAIFMT_DSP_A:
1138 audio1 |= WM8990_AIF_TMF_DSP;
1139 audio1 &= ~WM8990_AIF_LRCLK_INV;
1140 break;
1141 case SND_SOC_DAIFMT_DSP_B:
1142 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1143 break;
1144 default:
1145 return -EINVAL;
1146 }
1147
1148 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1149 wm8990_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
1150 return 0;
1151}
1152
1153static int wm8990_set_dai_clkdiv(struct snd_soc_codec_dai *codec_dai,
1154 int div_id, int div)
1155{
1156 struct snd_soc_codec *codec = codec_dai->codec;
1157 u16 reg;
1158
1159 switch (div_id) {
1160 case WM8990_MCLK_DIV:
1161 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
1162 ~WM8990_MCLK_DIV_MASK;
1163 wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
1164 break;
1165 case WM8990_DACCLK_DIV:
1166 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
1167 ~WM8990_DAC_CLKDIV_MASK;
1168 wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
1169 break;
1170 case WM8990_ADCCLK_DIV:
1171 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
1172 ~WM8990_ADC_CLKDIV_MASK;
1173 wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
1174 break;
1175 case WM8990_BCLK_DIV:
1176 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_1) &
1177 ~WM8990_BCLK_DIV_MASK;
1178 wm8990_write(codec, WM8990_CLOCKING_1, reg | div);
1179 break;
1180 default:
1181 return -EINVAL;
1182 }
1183
1184 return 0;
1185}
1186
1187/*
1188 * Set PCM DAI bit size and sample rate.
1189 */
1190static int wm8990_hw_params(struct snd_pcm_substream *substream,
1191 struct snd_pcm_hw_params *params)
1192{
1193 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1194 struct snd_soc_device *socdev = rtd->socdev;
1195 struct snd_soc_codec *codec = socdev->codec;
1196 u16 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1);
1197
1198 audio1 &= ~WM8990_AIF_WL_MASK;
1199 /* bit size */
1200 switch (params_format(params)) {
1201 case SNDRV_PCM_FORMAT_S16_LE:
1202 break;
1203 case SNDRV_PCM_FORMAT_S20_3LE:
1204 audio1 |= WM8990_AIF_WL_20BITS;
1205 break;
1206 case SNDRV_PCM_FORMAT_S24_LE:
1207 audio1 |= WM8990_AIF_WL_24BITS;
1208 break;
1209 case SNDRV_PCM_FORMAT_S32_LE:
1210 audio1 |= WM8990_AIF_WL_32BITS;
1211 break;
1212 }
1213
1214 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1215 return 0;
1216}
1217
1218static int wm8990_mute(struct snd_soc_codec_dai *dai, int mute)
1219{
1220 struct snd_soc_codec *codec = dai->codec;
1221 u16 val;
1222
1223 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1224
1225 if (mute)
1226 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1227 else
1228 wm8990_write(codec, WM8990_DAC_CTRL, val);
1229
1230 return 0;
1231}
1232
1233static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1234 enum snd_soc_bias_level level)
1235{
1236 u16 val;
1237
1238 switch (level) {
1239 case SND_SOC_BIAS_ON:
1240 break;
1241 case SND_SOC_BIAS_PREPARE:
1242 break;
1243 case SND_SOC_BIAS_STANDBY:
1244 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1245 /* Enable all output discharge bits */
1246 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1247 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1248 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1249 WM8990_DIS_ROUT);
1250
1251 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1252 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1253 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1254 WM8990_VMIDTOG);
1255
1256 /* Delay to allow output caps to discharge */
1257 msleep(msecs_to_jiffies(300));
1258
1259 /* Disable VMIDTOG */
1260 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1261 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1262
1263 /* disable all output discharge bits */
1264 wm8990_write(codec, WM8990_ANTIPOP1, 0);
1265
1266 /* Enable outputs */
1267 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1268
1269 msleep(msecs_to_jiffies(50));
1270
1271 /* Enable VMID at 2x50k */
1272 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1273
1274 msleep(msecs_to_jiffies(100));
1275
1276 /* Enable VREF */
1277 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1278
1279 msleep(msecs_to_jiffies(600));
1280
1281 /* Enable BUFIOEN */
1282 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1283 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1284 WM8990_BUFIOEN);
1285
1286 /* Disable outputs */
1287 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1288
1289 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1290 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1291 } else {
1292 /* ON -> standby */
1293
1294 }
1295 break;
1296
1297 case SND_SOC_BIAS_OFF:
1298 /* Enable POBCTRL and SOFT_ST */
1299 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1300 WM8990_POBCTRL | WM8990_BUFIOEN);
1301
1302 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1303 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1304 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1305 WM8990_BUFIOEN);
1306
1307 /* mute DAC */
1308 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL);
1309 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1310
1311 /* Enable any disabled outputs */
1312 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1313
1314 /* Disable VMID */
1315 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1316
1317 msleep(msecs_to_jiffies(300));
1318
1319 /* Enable all output discharge bits */
1320 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1321 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1322 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1323 WM8990_DIS_ROUT);
1324
1325 /* Disable VREF */
1326 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1327
1328 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1329 wm8990_write(codec, WM8990_ANTIPOP2, 0x0);
1330 break;
1331 }
1332
1333 codec->bias_level = level;
1334 return 0;
1335}
1336
1337#define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1338 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1339 SNDRV_PCM_RATE_48000)
1340
1341#define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1342 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1343
1344/*
1345 * The WM8990 supports 2 different and mutually exclusive DAI
1346 * configurations.
1347 *
1348 * 1. ADC/DAC on Primary Interface
1349 * 2. ADC on Primary Interface/DAC on secondary
1350 */
1351struct snd_soc_codec_dai wm8990_dai = {
1352/* ADC/DAC on primary */
1353 .name = "WM8990 ADC/DAC Primary",
1354 .id = 1,
1355 .playback = {
1356 .stream_name = "Playback",
1357 .channels_min = 1,
1358 .channels_max = 2,
1359 .rates = WM8990_RATES,
1360 .formats = WM8990_FORMATS,},
1361 .capture = {
1362 .stream_name = "Capture",
1363 .channels_min = 1,
1364 .channels_max = 2,
1365 .rates = WM8990_RATES,
1366 .formats = WM8990_FORMATS,},
1367 .ops = {
1368 .hw_params = wm8990_hw_params,},
1369 .dai_ops = {
1370 .digital_mute = wm8990_mute,
1371 .set_fmt = wm8990_set_dai_fmt,
1372 .set_clkdiv = wm8990_set_dai_clkdiv,
1373 .set_pll = wm8990_set_dai_pll,
1374 .set_sysclk = wm8990_set_dai_sysclk,
1375 },
1376};
1377EXPORT_SYMBOL_GPL(wm8990_dai);
1378
1379static int wm8990_suspend(struct platform_device *pdev, pm_message_t state)
1380{
1381 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1382 struct snd_soc_codec *codec = socdev->codec;
1383
1384 /* we only need to suspend if we are a valid card */
1385 if (!codec->card)
1386 return 0;
1387
1388 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1389 return 0;
1390}
1391
1392static int wm8990_resume(struct platform_device *pdev)
1393{
1394 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1395 struct snd_soc_codec *codec = socdev->codec;
1396 int i;
1397 u8 data[2];
1398 u16 *cache = codec->reg_cache;
1399
1400 /* we only need to resume if we are a valid card */
1401 if (!codec->card)
1402 return 0;
1403
1404 /* Sync reg_cache with the hardware */
1405 for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) {
1406 if (i + 1 == WM8990_RESET)
1407 continue;
1408 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
1409 data[1] = cache[i] & 0x00ff;
1410 codec->hw_write(codec->control_data, data, 2);
1411 }
1412
1413 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1414 return 0;
1415}
1416
1417/*
1418 * initialise the WM8990 driver
1419 * register the mixer and dsp interfaces with the kernel
1420 */
1421static int wm8990_init(struct snd_soc_device *socdev)
1422{
1423 struct snd_soc_codec *codec = socdev->codec;
1424 u16 reg;
1425 int ret = 0;
1426
1427 codec->name = "WM8990";
1428 codec->owner = THIS_MODULE;
1429 codec->read = wm8990_read_reg_cache;
1430 codec->write = wm8990_write;
1431 codec->set_bias_level = wm8990_set_bias_level;
1432 codec->dai = &wm8990_dai;
1433 codec->num_dai = 2;
1434 codec->reg_cache_size = ARRAY_SIZE(wm8990_reg);
1435 codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL);
1436
1437 if (codec->reg_cache == NULL)
1438 return -ENOMEM;
1439
1440 wm8990_reset(codec);
1441
1442 /* register pcms */
1443 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1444 if (ret < 0) {
1445 printk(KERN_ERR "wm8990: failed to create pcms\n");
1446 goto pcm_err;
1447 }
1448
1449 /* charge output caps */
1450 codec->bias_level = SND_SOC_BIAS_OFF;
1451 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1452
1453 reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4);
1454 wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1);
1455
1456 reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) &
1457 ~WM8990_GPIO1_SEL_MASK;
1458 wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1);
1459
1460 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
1461 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA);
1462
1463 wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1464 wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1465
1466 wm8990_add_controls(codec);
1467 wm8990_add_widgets(codec);
1468 ret = snd_soc_register_card(socdev);
1469 if (ret < 0) {
1470 printk(KERN_ERR "wm8990: failed to register card\n");
1471 goto card_err;
1472 }
1473 return ret;
1474
1475card_err:
1476 snd_soc_free_pcms(socdev);
1477 snd_soc_dapm_free(socdev);
1478pcm_err:
1479 kfree(codec->reg_cache);
1480 return ret;
1481}
1482
1483/* If the i2c layer weren't so broken, we could pass this kind of data
1484 around */
1485static struct snd_soc_device *wm8990_socdev;
1486
1487#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1488
1489/*
1490 * WM891 2 wire address is determined by GPIO5
1491 * state during powerup.
1492 * low = 0x34
1493 * high = 0x36
1494 */
1495static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
1496
1497/* Magic definition of all other variables and things */
1498I2C_CLIENT_INSMOD;
1499
1500static struct i2c_driver wm8990_i2c_driver;
1501static struct i2c_client client_template;
1502
1503static int wm8990_codec_probe(struct i2c_adapter *adap, int addr, int kind)
1504{
1505 struct snd_soc_device *socdev = wm8990_socdev;
1506 struct wm8990_setup_data *setup = socdev->codec_data;
1507 struct snd_soc_codec *codec = socdev->codec;
1508 struct i2c_client *i2c;
1509 int ret;
1510
1511 if (addr != setup->i2c_address)
1512 return -ENODEV;
1513
1514 client_template.adapter = adap;
1515 client_template.addr = addr;
1516
1517 i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
1518 if (i2c == NULL) {
1519 kfree(codec);
1520 return -ENOMEM;
1521 }
1522 i2c_set_clientdata(i2c, codec);
1523 codec->control_data = i2c;
1524
1525 ret = i2c_attach_client(i2c);
1526 if (ret < 0) {
1527 err("failed to attach codec at addr %x\n", addr);
1528 goto err;
1529 }
1530
1531 ret = wm8990_init(socdev);
1532 if (ret < 0) {
1533 err("failed to initialise WM8990\n");
1534 goto err;
1535 }
1536 return ret;
1537
1538err:
1539 kfree(codec);
1540 kfree(i2c);
1541 return ret;
1542}
1543
1544static int wm8990_i2c_detach(struct i2c_client *client)
1545{
1546 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1547 i2c_detach_client(client);
1548 kfree(codec->reg_cache);
1549 kfree(client);
1550 return 0;
1551}
1552
1553static int wm8990_i2c_attach(struct i2c_adapter *adap)
1554{
1555 return i2c_probe(adap, &addr_data, wm8990_codec_probe);
1556}
1557
1558static struct i2c_driver wm8990_i2c_driver = {
1559 .driver = {
1560 .name = "WM8990 I2C Codec",
1561 .owner = THIS_MODULE,
1562 },
1563 .attach_adapter = wm8990_i2c_attach,
1564 .detach_client = wm8990_i2c_detach,
1565 .command = NULL,
1566};
1567
1568static struct i2c_client client_template = {
1569 .name = "WM8990",
1570 .driver = &wm8990_i2c_driver,
1571};
1572#endif
1573
1574static int wm8990_probe(struct platform_device *pdev)
1575{
1576 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1577 struct wm8990_setup_data *setup;
1578 struct snd_soc_codec *codec;
1579 struct wm8990_priv *wm8990;
1580 int ret = 0;
1581
1582 info("WM8990 Audio Codec %s\n", WM8990_VERSION);
1583
1584 setup = socdev->codec_data;
1585 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1586 if (codec == NULL)
1587 return -ENOMEM;
1588
1589 wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
1590 if (wm8990 == NULL) {
1591 kfree(codec);
1592 return -ENOMEM;
1593 }
1594
1595 codec->private_data = wm8990;
1596 socdev->codec = codec;
1597 mutex_init(&codec->mutex);
1598 INIT_LIST_HEAD(&codec->dapm_widgets);
1599 INIT_LIST_HEAD(&codec->dapm_paths);
1600 wm8990_socdev = socdev;
1601
1602#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1603 if (setup->i2c_address) {
1604 normal_i2c[0] = setup->i2c_address;
1605 codec->hw_write = (hw_write_t)i2c_master_send;
1606 ret = i2c_add_driver(&wm8990_i2c_driver);
1607 if (ret != 0)
1608 printk(KERN_ERR "can't add i2c driver");
1609 }
1610#else
1611 /* Add other interfaces here */
1612#endif
1613 return ret;
1614}
1615
1616/* power down chip */
1617static int wm8990_remove(struct platform_device *pdev)
1618{
1619 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1620 struct snd_soc_codec *codec = socdev->codec;
1621
1622 if (codec->control_data)
1623 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1624 snd_soc_free_pcms(socdev);
1625 snd_soc_dapm_free(socdev);
1626#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1627 i2c_del_driver(&wm8990_i2c_driver);
1628#endif
1629 kfree(codec->private_data);
1630 kfree(codec);
1631
1632 return 0;
1633}
1634
1635struct snd_soc_codec_device soc_codec_dev_wm8990 = {
1636 .probe = wm8990_probe,
1637 .remove = wm8990_remove,
1638 .suspend = wm8990_suspend,
1639 .resume = wm8990_resume,
1640};
1641EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990);
1642
1643MODULE_DESCRIPTION("ASoC WM8990 driver");
1644MODULE_AUTHOR("Liam Girdwood");
1645MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8990.h b/sound/soc/codecs/wm8990.h
new file mode 100644
index 000000000000..bf9f8823dfc9
--- /dev/null
+++ b/sound/soc/codecs/wm8990.h
@@ -0,0 +1,832 @@
1/*
2 * wm8990.h -- audio driver for WM8990
3 *
4 * Copyright 2007 Wolfson Microelectronics PLC.
5 * Author: Graeme Gregory
6 * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __WM8990REGISTERDEFS_H__
16#define __WM8990REGISTERDEFS_H__
17
18/*
19 * Register values.
20 */
21#define WM8990_RESET 0x00
22#define WM8990_POWER_MANAGEMENT_1 0x01
23#define WM8990_POWER_MANAGEMENT_2 0x02
24#define WM8990_POWER_MANAGEMENT_3 0x03
25#define WM8990_AUDIO_INTERFACE_1 0x04
26#define WM8990_AUDIO_INTERFACE_2 0x05
27#define WM8990_CLOCKING_1 0x06
28#define WM8990_CLOCKING_2 0x07
29#define WM8990_AUDIO_INTERFACE_3 0x08
30#define WM8990_AUDIO_INTERFACE_4 0x09
31#define WM8990_DAC_CTRL 0x0A
32#define WM8990_LEFT_DAC_DIGITAL_VOLUME 0x0B
33#define WM8990_RIGHT_DAC_DIGITAL_VOLUME 0x0C
34#define WM8990_DIGITAL_SIDE_TONE 0x0D
35#define WM8990_ADC_CTRL 0x0E
36#define WM8990_LEFT_ADC_DIGITAL_VOLUME 0x0F
37#define WM8990_RIGHT_ADC_DIGITAL_VOLUME 0x10
38#define WM8990_GPIO_CTRL_1 0x12
39#define WM8990_GPIO1_GPIO2 0x13
40#define WM8990_GPIO3_GPIO4 0x14
41#define WM8990_GPIO5_GPIO6 0x15
42#define WM8990_GPIOCTRL_2 0x16
43#define WM8990_GPIO_POL 0x17
44#define WM8990_LEFT_LINE_INPUT_1_2_VOLUME 0x18
45#define WM8990_LEFT_LINE_INPUT_3_4_VOLUME 0x19
46#define WM8990_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
47#define WM8990_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
48#define WM8990_LEFT_OUTPUT_VOLUME 0x1C
49#define WM8990_RIGHT_OUTPUT_VOLUME 0x1D
50#define WM8990_LINE_OUTPUTS_VOLUME 0x1E
51#define WM8990_OUT3_4_VOLUME 0x1F
52#define WM8990_LEFT_OPGA_VOLUME 0x20
53#define WM8990_RIGHT_OPGA_VOLUME 0x21
54#define WM8990_SPEAKER_VOLUME 0x22
55#define WM8990_CLASSD1 0x23
56#define WM8990_CLASSD3 0x25
57#define WM8990_INPUT_MIXER1 0x27
58#define WM8990_INPUT_MIXER2 0x28
59#define WM8990_INPUT_MIXER3 0x29
60#define WM8990_INPUT_MIXER4 0x2A
61#define WM8990_INPUT_MIXER5 0x2B
62#define WM8990_INPUT_MIXER6 0x2C
63#define WM8990_OUTPUT_MIXER1 0x2D
64#define WM8990_OUTPUT_MIXER2 0x2E
65#define WM8990_OUTPUT_MIXER3 0x2F
66#define WM8990_OUTPUT_MIXER4 0x30
67#define WM8990_OUTPUT_MIXER5 0x31
68#define WM8990_OUTPUT_MIXER6 0x32
69#define WM8990_OUT3_4_MIXER 0x33
70#define WM8990_LINE_MIXER1 0x34
71#define WM8990_LINE_MIXER2 0x35
72#define WM8990_SPEAKER_MIXER 0x36
73#define WM8990_ADDITIONAL_CONTROL 0x37
74#define WM8990_ANTIPOP1 0x38
75#define WM8990_ANTIPOP2 0x39
76#define WM8990_MICBIAS 0x3A
77#define WM8990_PLL1 0x3C
78#define WM8990_PLL2 0x3D
79#define WM8990_PLL3 0x3E
80#define WM8990_INTDRIVBITS 0x3F
81
82#define WM8990_REGISTER_COUNT 60
83#define WM8990_MAX_REGISTER 0x3F
84
85/*
86 * Field Definitions.
87 */
88
89/*
90 * R0 (0x00) - Reset
91 */
92#define WM8990_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET_CHIP_ID */
93
94/*
95 * R1 (0x01) - Power Management (1)
96 */
97#define WM8990_SPK_ENA 0x1000 /* SPK_ENA */
98#define WM8990_SPK_ENA_BIT 12
99#define WM8990_OUT3_ENA 0x0800 /* OUT3_ENA */
100#define WM8990_OUT3_ENA_BIT 11
101#define WM8990_OUT4_ENA 0x0400 /* OUT4_ENA */
102#define WM8990_OUT4_ENA_BIT 10
103#define WM8990_LOUT_ENA 0x0200 /* LOUT_ENA */
104#define WM8990_LOUT_ENA_BIT 9
105#define WM8990_ROUT_ENA 0x0100 /* ROUT_ENA */
106#define WM8990_ROUT_ENA_BIT 8
107#define WM8990_MICBIAS_ENA 0x0010 /* MICBIAS_ENA */
108#define WM8990_MICBIAS_ENA_BIT 4
109#define WM8990_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */
110#define WM8990_VREF_ENA 0x0001 /* VREF_ENA */
111#define WM8990_VREF_ENA_BIT 0
112
113/*
114 * R2 (0x02) - Power Management (2)
115 */
116#define WM8990_PLL_ENA 0x8000 /* PLL_ENA */
117#define WM8990_PLL_ENA_BIT 15
118#define WM8990_TSHUT_ENA 0x4000 /* TSHUT_ENA */
119#define WM8990_TSHUT_ENA_BIT 14
120#define WM8990_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
121#define WM8990_TSHUT_OPDIS_BIT 13
122#define WM8990_OPCLK_ENA 0x0800 /* OPCLK_ENA */
123#define WM8990_OPCLK_ENA_BIT 11
124#define WM8990_AINL_ENA 0x0200 /* AINL_ENA */
125#define WM8990_AINL_ENA_BIT 9
126#define WM8990_AINR_ENA 0x0100 /* AINR_ENA */
127#define WM8990_AINR_ENA_BIT 8
128#define WM8990_LIN34_ENA 0x0080 /* LIN34_ENA */
129#define WM8990_LIN34_ENA_BIT 7
130#define WM8990_LIN12_ENA 0x0040 /* LIN12_ENA */
131#define WM8990_LIN12_ENA_BIT 6
132#define WM8990_RIN34_ENA 0x0020 /* RIN34_ENA */
133#define WM8990_RIN34_ENA_BIT 5
134#define WM8990_RIN12_ENA 0x0010 /* RIN12_ENA */
135#define WM8990_RIN12_ENA_BIT 4
136#define WM8990_ADCL_ENA 0x0002 /* ADCL_ENA */
137#define WM8990_ADCL_ENA_BIT 1
138#define WM8990_ADCR_ENA 0x0001 /* ADCR_ENA */
139#define WM8990_ADCR_ENA_BIT 0
140
141/*
142 * R3 (0x03) - Power Management (3)
143 */
144#define WM8990_LON_ENA 0x2000 /* LON_ENA */
145#define WM8990_LON_ENA_BIT 13
146#define WM8990_LOP_ENA 0x1000 /* LOP_ENA */
147#define WM8990_LOP_ENA_BIT 12
148#define WM8990_RON_ENA 0x0800 /* RON_ENA */
149#define WM8990_RON_ENA_BIT 11
150#define WM8990_ROP_ENA 0x0400 /* ROP_ENA */
151#define WM8990_ROP_ENA_BIT 10
152#define WM8990_LOPGA_ENA 0x0080 /* LOPGA_ENA */
153#define WM8990_LOPGA_ENA_BIT 7
154#define WM8990_ROPGA_ENA 0x0040 /* ROPGA_ENA */
155#define WM8990_ROPGA_ENA_BIT 6
156#define WM8990_LOMIX_ENA 0x0020 /* LOMIX_ENA */
157#define WM8990_LOMIX_ENA_BIT 5
158#define WM8990_ROMIX_ENA 0x0010 /* ROMIX_ENA */
159#define WM8990_ROMIX_ENA_BIT 4
160#define WM8990_DACL_ENA 0x0002 /* DACL_ENA */
161#define WM8990_DACL_ENA_BIT 1
162#define WM8990_DACR_ENA 0x0001 /* DACR_ENA */
163#define WM8990_DACR_ENA_BIT 0
164
165/*
166 * R4 (0x04) - Audio Interface (1)
167 */
168#define WM8990_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */
169#define WM8990_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */
170#define WM8990_AIFADC_TDM 0x2000 /* AIFADC_TDM */
171#define WM8990_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */
172#define WM8990_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */
173#define WM8990_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */
174#define WM8990_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */
175#define WM8990_AIF_WL_16BITS (0 << 5)
176#define WM8990_AIF_WL_20BITS (1 << 5)
177#define WM8990_AIF_WL_24BITS (2 << 5)
178#define WM8990_AIF_WL_32BITS (3 << 5)
179#define WM8990_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */
180#define WM8990_AIF_TMF_RIGHTJ (0 << 3)
181#define WM8990_AIF_TMF_LEFTJ (1 << 3)
182#define WM8990_AIF_TMF_I2S (2 << 3)
183#define WM8990_AIF_TMF_DSP (3 << 3)
184
185/*
186 * R5 (0x05) - Audio Interface (2)
187 */
188#define WM8990_DACL_SRC 0x8000 /* DACL_SRC */
189#define WM8990_DACR_SRC 0x4000 /* DACR_SRC */
190#define WM8990_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
191#define WM8990_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
192#define WM8990_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST */
193#define WM8990_DAC_COMP 0x0010 /* DAC_COMP */
194#define WM8990_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */
195#define WM8990_ADC_COMP 0x0004 /* ADC_COMP */
196#define WM8990_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */
197#define WM8990_LOOPBACK 0x0001 /* LOOPBACK */
198
199/*
200 * R6 (0x06) - Clocking (1)
201 */
202#define WM8990_TOCLK_RATE 0x8000 /* TOCLK_RATE */
203#define WM8990_TOCLK_ENA 0x4000 /* TOCLK_ENA */
204#define WM8990_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */
205#define WM8990_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
206#define WM8990_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */
207#define WM8990_BCLK_DIV_1 (0x0 << 1)
208#define WM8990_BCLK_DIV_1_5 (0x1 << 1)
209#define WM8990_BCLK_DIV_2 (0x2 << 1)
210#define WM8990_BCLK_DIV_3 (0x3 << 1)
211#define WM8990_BCLK_DIV_4 (0x4 << 1)
212#define WM8990_BCLK_DIV_5_5 (0x5 << 1)
213#define WM8990_BCLK_DIV_6 (0x6 << 1)
214#define WM8990_BCLK_DIV_8 (0x7 << 1)
215#define WM8990_BCLK_DIV_11 (0x8 << 1)
216#define WM8990_BCLK_DIV_12 (0x9 << 1)
217#define WM8990_BCLK_DIV_16 (0xA << 1)
218#define WM8990_BCLK_DIV_22 (0xB << 1)
219#define WM8990_BCLK_DIV_24 (0xC << 1)
220#define WM8990_BCLK_DIV_32 (0xD << 1)
221#define WM8990_BCLK_DIV_44 (0xE << 1)
222#define WM8990_BCLK_DIV_48 (0xF << 1)
223
224/*
225 * R7 (0x07) - Clocking (2)
226 */
227#define WM8990_MCLK_SRC 0x8000 /* MCLK_SRC */
228#define WM8990_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */
229#define WM8990_CLK_FORCE 0x2000 /* CLK_FORCE */
230#define WM8990_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */
231#define WM8990_MCLK_DIV_1 (0 << 11)
232#define WM8990_MCLK_DIV_2 (2 << 11)
233#define WM8990_MCLK_INV 0x0400 /* MCLK_INV */
234#define WM8990_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV */
235#define WM8990_ADC_CLKDIV_1 (0 << 5)
236#define WM8990_ADC_CLKDIV_1_5 (1 << 5)
237#define WM8990_ADC_CLKDIV_2 (2 << 5)
238#define WM8990_ADC_CLKDIV_3 (3 << 5)
239#define WM8990_ADC_CLKDIV_4 (4 << 5)
240#define WM8990_ADC_CLKDIV_5_5 (5 << 5)
241#define WM8990_ADC_CLKDIV_6 (6 << 5)
242#define WM8990_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */
243#define WM8990_DAC_CLKDIV_1 (0 << 2)
244#define WM8990_DAC_CLKDIV_1_5 (1 << 2)
245#define WM8990_DAC_CLKDIV_2 (2 << 2)
246#define WM8990_DAC_CLKDIV_3 (3 << 2)
247#define WM8990_DAC_CLKDIV_4 (4 << 2)
248#define WM8990_DAC_CLKDIV_5_5 (5 << 2)
249#define WM8990_DAC_CLKDIV_6 (6 << 2)
250
251/*
252 * R8 (0x08) - Audio Interface (3)
253 */
254#define WM8990_AIF_MSTR1 0x8000 /* AIF_MSTR1 */
255#define WM8990_AIF_MSTR2 0x4000 /* AIF_MSTR2 */
256#define WM8990_AIF_SEL 0x2000 /* AIF_SEL */
257#define WM8990_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */
258#define WM8990_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE */
259
260/*
261 * R9 (0x09) - Audio Interface (4)
262 */
263#define WM8990_ALRCGPIO1 0x8000 /* ALRCGPIO1 */
264#define WM8990_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */
265#define WM8990_AIF_TRIS 0x2000 /* AIF_TRIS */
266#define WM8990_DACLRC_DIR 0x0800 /* DACLRC_DIR */
267#define WM8990_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE */
268
269/*
270 * R10 (0x0A) - DAC CTRL
271 */
272#define WM8990_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */
273#define WM8990_DAC_MONO 0x0200 /* DAC_MONO */
274#define WM8990_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */
275#define WM8990_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */
276#define WM8990_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */
277#define WM8990_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */
278#define WM8990_DAC_MUTE 0x0004 /* DAC_MUTE */
279#define WM8990_DACL_DATINV 0x0002 /* DACL_DATINV */
280#define WM8990_DACR_DATINV 0x0001 /* DACR_DATINV */
281
282/*
283 * R11 (0x0B) - Left DAC Digital Volume
284 */
285#define WM8990_DAC_VU 0x0100 /* DAC_VU */
286#define WM8990_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
287#define WM8990_DACL_VOL_SHIFT 0
288/*
289 * R12 (0x0C) - Right DAC Digital Volume
290 */
291#define WM8990_DAC_VU 0x0100 /* DAC_VU */
292#define WM8990_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
293#define WM8990_DACR_VOL_SHIFT 0
294/*
295 * R13 (0x0D) - Digital Side Tone
296 */
297#define WM8990_ADCL_DAC_SVOL_MASK 0x0F /* ADCL_DAC_SVOL */
298#define WM8990_ADCL_DAC_SVOL_SHIFT 9
299#define WM8990_ADCR_DAC_SVOL_MASK 0x0F /* ADCR_DAC_SVOL */
300#define WM8990_ADCR_DAC_SVOL_SHIFT 5
301#define WM8990_ADC_TO_DACL_MASK 0x03 /* ADC_TO_DACL - [3:2] */
302#define WM8990_ADC_TO_DACL_SHIFT 2
303#define WM8990_ADC_TO_DACR_MASK 0x03 /* ADC_TO_DACR - [1:0] */
304#define WM8990_ADC_TO_DACR_SHIFT 0
305
306/*
307 * R14 (0x0E) - ADC CTRL
308 */
309#define WM8990_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */
310#define WM8990_ADC_HPF_ENA_BIT 8
311#define WM8990_ADC_HPF_CUT_MASK 0x03 /* ADC_HPF_CUT - [6:5] */
312#define WM8990_ADC_HPF_CUT_SHIFT 5
313#define WM8990_ADCL_DATINV 0x0002 /* ADCL_DATINV */
314#define WM8990_ADCL_DATINV_BIT 1
315#define WM8990_ADCR_DATINV 0x0001 /* ADCR_DATINV */
316#define WM8990_ADCR_DATINV_BIT 0
317
318/*
319 * R15 (0x0F) - Left ADC Digital Volume
320 */
321#define WM8990_ADC_VU 0x0100 /* ADC_VU */
322#define WM8990_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
323#define WM8990_ADCL_VOL_SHIFT 0
324
325/*
326 * R16 (0x10) - Right ADC Digital Volume
327 */
328#define WM8990_ADC_VU 0x0100 /* ADC_VU */
329#define WM8990_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
330#define WM8990_ADCR_VOL_SHIFT 0
331
332/*
333 * R18 (0x12) - GPIO CTRL 1
334 */
335#define WM8990_IRQ 0x1000 /* IRQ */
336#define WM8990_TEMPOK 0x0800 /* TEMPOK */
337#define WM8990_MICSHRT 0x0400 /* MICSHRT */
338#define WM8990_MICDET 0x0200 /* MICDET */
339#define WM8990_PLL_LCK 0x0100 /* PLL_LCK */
340#define WM8990_GPI8_STATUS 0x0080 /* GPI8_STATUS */
341#define WM8990_GPI7_STATUS 0x0040 /* GPI7_STATUS */
342#define WM8990_GPIO6_STATUS 0x0020 /* GPIO6_STATUS */
343#define WM8990_GPIO5_STATUS 0x0010 /* GPIO5_STATUS */
344#define WM8990_GPIO4_STATUS 0x0008 /* GPIO4_STATUS */
345#define WM8990_GPIO3_STATUS 0x0004 /* GPIO3_STATUS */
346#define WM8990_GPIO2_STATUS 0x0002 /* GPIO2_STATUS */
347#define WM8990_GPIO1_STATUS 0x0001 /* GPIO1_STATUS */
348
349/*
350 * R19 (0x13) - GPIO1 & GPIO2
351 */
352#define WM8990_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */
353#define WM8990_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */
354#define WM8990_GPIO2_PU 0x2000 /* GPIO2_PU */
355#define WM8990_GPIO2_PD 0x1000 /* GPIO2_PD */
356#define WM8990_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */
357#define WM8990_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */
358#define WM8990_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */
359#define WM8990_GPIO1_PU 0x0020 /* GPIO1_PU */
360#define WM8990_GPIO1_PD 0x0010 /* GPIO1_PD */
361#define WM8990_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
362
363/*
364 * R20 (0x14) - GPIO3 & GPIO4
365 */
366#define WM8990_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */
367#define WM8990_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */
368#define WM8990_GPIO4_PU 0x2000 /* GPIO4_PU */
369#define WM8990_GPIO4_PD 0x1000 /* GPIO4_PD */
370#define WM8990_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */
371#define WM8990_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */
372#define WM8990_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */
373#define WM8990_GPIO3_PU 0x0020 /* GPIO3_PU */
374#define WM8990_GPIO3_PD 0x0010 /* GPIO3_PD */
375#define WM8990_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
376
377/*
378 * R21 (0x15) - GPIO5 & GPIO6
379 */
380#define WM8990_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */
381#define WM8990_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */
382#define WM8990_GPIO6_PU 0x2000 /* GPIO6_PU */
383#define WM8990_GPIO6_PD 0x1000 /* GPIO6_PD */
384#define WM8990_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */
385#define WM8990_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */
386#define WM8990_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */
387#define WM8990_GPIO5_PU 0x0020 /* GPIO5_PU */
388#define WM8990_GPIO5_PD 0x0010 /* GPIO5_PD */
389#define WM8990_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */
390
391/*
392 * R22 (0x16) - GPIOCTRL 2
393 */
394#define WM8990_RD_3W_ENA 0x8000 /* RD_3W_ENA */
395#define WM8990_MODE_3W4W 0x4000 /* MODE_3W4W */
396#define WM8990_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */
397#define WM8990_MICSHRT_IRQ_ENA 0x0400 /* MICSHRT_IRQ_ENA */
398#define WM8990_MICDET_IRQ_ENA 0x0200 /* MICDET_IRQ_ENA */
399#define WM8990_PLL_LCK_IRQ_ENA 0x0100 /* PLL_LCK_IRQ_ENA */
400#define WM8990_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */
401#define WM8990_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */
402#define WM8990_GPI8_ENA 0x0010 /* GPI8_ENA */
403#define WM8990_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */
404#define WM8990_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */
405#define WM8990_GPI7_ENA 0x0001 /* GPI7_ENA */
406
407/*
408 * R23 (0x17) - GPIO_POL
409 */
410#define WM8990_IRQ_INV 0x1000 /* IRQ_INV */
411#define WM8990_TEMPOK_POL 0x0800 /* TEMPOK_POL */
412#define WM8990_MICSHRT_POL 0x0400 /* MICSHRT_POL */
413#define WM8990_MICDET_POL 0x0200 /* MICDET_POL */
414#define WM8990_PLL_LCK_POL 0x0100 /* PLL_LCK_POL */
415#define WM8990_GPI8_POL 0x0080 /* GPI8_POL */
416#define WM8990_GPI7_POL 0x0040 /* GPI7_POL */
417#define WM8990_GPIO6_POL 0x0020 /* GPIO6_POL */
418#define WM8990_GPIO5_POL 0x0010 /* GPIO5_POL */
419#define WM8990_GPIO4_POL 0x0008 /* GPIO4_POL */
420#define WM8990_GPIO3_POL 0x0004 /* GPIO3_POL */
421#define WM8990_GPIO2_POL 0x0002 /* GPIO2_POL */
422#define WM8990_GPIO1_POL 0x0001 /* GPIO1_POL */
423
424/*
425 * R24 (0x18) - Left Line Input 1&2 Volume
426 */
427#define WM8990_IPVU 0x0100 /* IPVU */
428#define WM8990_LI12MUTE 0x0080 /* LI12MUTE */
429#define WM8990_LI12MUTE_BIT 7
430#define WM8990_LI12ZC 0x0040 /* LI12ZC */
431#define WM8990_LI12ZC_BIT 6
432#define WM8990_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */
433#define WM8990_LIN12VOL_SHIFT 0
434/*
435 * R25 (0x19) - Left Line Input 3&4 Volume
436 */
437#define WM8990_IPVU 0x0100 /* IPVU */
438#define WM8990_LI34MUTE 0x0080 /* LI34MUTE */
439#define WM8990_LI34MUTE_BIT 7
440#define WM8990_LI34ZC 0x0040 /* LI34ZC */
441#define WM8990_LI34ZC_BIT 6
442#define WM8990_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */
443#define WM8990_LIN34VOL_SHIFT 0
444
445/*
446 * R26 (0x1A) - Right Line Input 1&2 Volume
447 */
448#define WM8990_IPVU 0x0100 /* IPVU */
449#define WM8990_RI12MUTE 0x0080 /* RI12MUTE */
450#define WM8990_RI12MUTE_BIT 7
451#define WM8990_RI12ZC 0x0040 /* RI12ZC */
452#define WM8990_RI12ZC_BIT 6
453#define WM8990_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */
454#define WM8990_RIN12VOL_SHIFT 0
455
456/*
457 * R27 (0x1B) - Right Line Input 3&4 Volume
458 */
459#define WM8990_IPVU 0x0100 /* IPVU */
460#define WM8990_RI34MUTE 0x0080 /* RI34MUTE */
461#define WM8990_RI34MUTE_BIT 7
462#define WM8990_RI34ZC 0x0040 /* RI34ZC */
463#define WM8990_RI34ZC_BIT 6
464#define WM8990_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */
465#define WM8990_RIN34VOL_SHIFT 0
466
467/*
468 * R28 (0x1C) - Left Output Volume
469 */
470#define WM8990_OPVU 0x0100 /* OPVU */
471#define WM8990_LOZC 0x0080 /* LOZC */
472#define WM8990_LOZC_BIT 7
473#define WM8990_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */
474#define WM8990_LOUTVOL_SHIFT 0
475/*
476 * R29 (0x1D) - Right Output Volume
477 */
478#define WM8990_OPVU 0x0100 /* OPVU */
479#define WM8990_ROZC 0x0080 /* ROZC */
480#define WM8990_ROZC_BIT 7
481#define WM8990_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */
482#define WM8990_ROUTVOL_SHIFT 0
483/*
484 * R30 (0x1E) - Line Outputs Volume
485 */
486#define WM8990_LONMUTE 0x0040 /* LONMUTE */
487#define WM8990_LONMUTE_BIT 6
488#define WM8990_LOPMUTE 0x0020 /* LOPMUTE */
489#define WM8990_LOPMUTE_BIT 5
490#define WM8990_LOATTN 0x0010 /* LOATTN */
491#define WM8990_LOATTN_BIT 4
492#define WM8990_RONMUTE 0x0004 /* RONMUTE */
493#define WM8990_RONMUTE_BIT 2
494#define WM8990_ROPMUTE 0x0002 /* ROPMUTE */
495#define WM8990_ROPMUTE_BIT 1
496#define WM8990_ROATTN 0x0001 /* ROATTN */
497#define WM8990_ROATTN_BIT 0
498
499/*
500 * R31 (0x1F) - Out3/4 Volume
501 */
502#define WM8990_OUT3MUTE 0x0020 /* OUT3MUTE */
503#define WM8990_OUT3MUTE_BIT 5
504#define WM8990_OUT3ATTN 0x0010 /* OUT3ATTN */
505#define WM8990_OUT3ATTN_BIT 4
506#define WM8990_OUT4MUTE 0x0002 /* OUT4MUTE */
507#define WM8990_OUT4MUTE_BIT 1
508#define WM8990_OUT4ATTN 0x0001 /* OUT4ATTN */
509#define WM8990_OUT4ATTN_BIT 0
510
511/*
512 * R32 (0x20) - Left OPGA Volume
513 */
514#define WM8990_OPVU 0x0100 /* OPVU */
515#define WM8990_LOPGAZC 0x0080 /* LOPGAZC */
516#define WM8990_LOPGAZC_BIT 7
517#define WM8990_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */
518#define WM8990_LOPGAVOL_SHIFT 0
519
520/*
521 * R33 (0x21) - Right OPGA Volume
522 */
523#define WM8990_OPVU 0x0100 /* OPVU */
524#define WM8990_ROPGAZC 0x0080 /* ROPGAZC */
525#define WM8990_ROPGAZC_BIT 7
526#define WM8990_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */
527#define WM8990_ROPGAVOL_SHIFT 0
528/*
529 * R34 (0x22) - Speaker Volume
530 */
531#define WM8990_SPKVOL_MASK 0x0003 /* SPKVOL - [1:0] */
532#define WM8990_SPKVOL_SHIFT 0
533
534/*
535 * R35 (0x23) - ClassD1
536 */
537#define WM8990_CDMODE 0x0100 /* CDMODE */
538#define WM8990_CDMODE_BIT 8
539
540/*
541 * R37 (0x25) - ClassD3
542 */
543#define WM8990_DCGAIN_MASK 0x0007 /* DCGAIN - [5:3] */
544#define WM8990_DCGAIN_SHIFT 3
545#define WM8990_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */
546#define WM8990_ACGAIN_SHIFT 0
547/*
548 * R39 (0x27) - Input Mixer1
549 */
550#define WM8990_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */
551#define WM8990_AINLMODE_SHIFT 2
552#define WM8990_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */
553#define WM8990_AINRMODE_SHIFT 0
554
555/*
556 * R40 (0x28) - Input Mixer2
557 */
558#define WM8990_LMP4 0x0080 /* LMP4 */
559#define WM8990_LMP4_BIT 7 /* LMP4 */
560#define WM8990_LMN3 0x0040 /* LMN3 */
561#define WM8990_LMN3_BIT 6 /* LMN3 */
562#define WM8990_LMP2 0x0020 /* LMP2 */
563#define WM8990_LMP2_BIT 5 /* LMP2 */
564#define WM8990_LMN1 0x0010 /* LMN1 */
565#define WM8990_LMN1_BIT 4 /* LMN1 */
566#define WM8990_RMP4 0x0008 /* RMP4 */
567#define WM8990_RMP4_BIT 3 /* RMP4 */
568#define WM8990_RMN3 0x0004 /* RMN3 */
569#define WM8990_RMN3_BIT 2 /* RMN3 */
570#define WM8990_RMP2 0x0002 /* RMP2 */
571#define WM8990_RMP2_BIT 1 /* RMP2 */
572#define WM8990_RMN1 0x0001 /* RMN1 */
573#define WM8990_RMN1_BIT 0 /* RMN1 */
574
575/*
576 * R41 (0x29) - Input Mixer3
577 */
578#define WM8990_L34MNB 0x0100 /* L34MNB */
579#define WM8990_L34MNB_BIT 8
580#define WM8990_L34MNBST 0x0080 /* L34MNBST */
581#define WM8990_L34MNBST_BIT 7
582#define WM8990_L12MNB 0x0020 /* L12MNB */
583#define WM8990_L12MNB_BIT 5
584#define WM8990_L12MNBST 0x0010 /* L12MNBST */
585#define WM8990_L12MNBST_BIT 4
586#define WM8990_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */
587#define WM8990_LDBVOL_SHIFT 0
588
589/*
590 * R42 (0x2A) - Input Mixer4
591 */
592#define WM8990_R34MNB 0x0100 /* R34MNB */
593#define WM8990_R34MNB_BIT 8
594#define WM8990_R34MNBST 0x0080 /* R34MNBST */
595#define WM8990_R34MNBST_BIT 7
596#define WM8990_R12MNB 0x0020 /* R12MNB */
597#define WM8990_R12MNB_BIT 5
598#define WM8990_R12MNBST 0x0010 /* R12MNBST */
599#define WM8990_R12MNBST_BIT 4
600#define WM8990_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */
601#define WM8990_RDBVOL_SHIFT 0
602
603/*
604 * R43 (0x2B) - Input Mixer5
605 */
606#define WM8990_LI2BVOL_MASK 0x07 /* LI2BVOL - [8:6] */
607#define WM8990_LI2BVOL_SHIFT 6
608#define WM8990_LR4BVOL_MASK 0x07 /* LR4BVOL - [5:3] */
609#define WM8990_LR4BVOL_SHIFT 3
610#define WM8990_LL4BVOL_MASK 0x07 /* LL4BVOL - [2:0] */
611#define WM8990_LL4BVOL_SHIFT 0
612
613/*
614 * R44 (0x2C) - Input Mixer6
615 */
616#define WM8990_RI2BVOL_MASK 0x07 /* RI2BVOL - [8:6] */
617#define WM8990_RI2BVOL_SHIFT 6
618#define WM8990_RL4BVOL_MASK 0x07 /* RL4BVOL - [5:3] */
619#define WM8990_RL4BVOL_SHIFT 3
620#define WM8990_RR4BVOL_MASK 0x07 /* RR4BVOL - [2:0] */
621#define WM8990_RR4BVOL_SHIFT 0
622
623/*
624 * R45 (0x2D) - Output Mixer1
625 */
626#define WM8990_LRBLO 0x0080 /* LRBLO */
627#define WM8990_LRBLO_BIT 7
628#define WM8990_LLBLO 0x0040 /* LLBLO */
629#define WM8990_LLBLO_BIT 6
630#define WM8990_LRI3LO 0x0020 /* LRI3LO */
631#define WM8990_LRI3LO_BIT 5
632#define WM8990_LLI3LO 0x0010 /* LLI3LO */
633#define WM8990_LLI3LO_BIT 4
634#define WM8990_LR12LO 0x0008 /* LR12LO */
635#define WM8990_LR12LO_BIT 3
636#define WM8990_LL12LO 0x0004 /* LL12LO */
637#define WM8990_LL12LO_BIT 2
638#define WM8990_LDLO 0x0001 /* LDLO */
639#define WM8990_LDLO_BIT 0
640
641/*
642 * R46 (0x2E) - Output Mixer2
643 */
644#define WM8990_RLBRO 0x0080 /* RLBRO */
645#define WM8990_RLBRO_BIT 7
646#define WM8990_RRBRO 0x0040 /* RRBRO */
647#define WM8990_RRBRO_BIT 6
648#define WM8990_RLI3RO 0x0020 /* RLI3RO */
649#define WM8990_RLI3RO_BIT 5
650#define WM8990_RRI3RO 0x0010 /* RRI3RO */
651#define WM8990_RRI3RO_BIT 4
652#define WM8990_RL12RO 0x0008 /* RL12RO */
653#define WM8990_RL12RO_BIT 3
654#define WM8990_RR12RO 0x0004 /* RR12RO */
655#define WM8990_RR12RO_BIT 2
656#define WM8990_RDRO 0x0001 /* RDRO */
657#define WM8990_RDRO_BIT 0
658
659/*
660 * R47 (0x2F) - Output Mixer3
661 */
662#define WM8990_LLI3LOVOL_MASK 0x07 /* LLI3LOVOL - [8:6] */
663#define WM8990_LLI3LOVOL_SHIFT 6
664#define WM8990_LR12LOVOL_MASK 0x07 /* LR12LOVOL - [5:3] */
665#define WM8990_LR12LOVOL_SHIFT 3
666#define WM8990_LL12LOVOL_MASK 0x07 /* LL12LOVOL - [2:0] */
667#define WM8990_LL12LOVOL_SHIFT 0
668
669/*
670 * R48 (0x30) - Output Mixer4
671 */
672#define WM8990_RRI3ROVOL_MASK 0x07 /* RRI3ROVOL - [8:6] */
673#define WM8990_RRI3ROVOL_SHIFT 6
674#define WM8990_RL12ROVOL_MASK 0x07 /* RL12ROVOL - [5:3] */
675#define WM8990_RL12ROVOL_SHIFT 3
676#define WM8990_RR12ROVOL_MASK 0x07 /* RR12ROVOL - [2:0] */
677#define WM8990_RR12ROVOL_SHIFT 0
678
679/*
680 * R49 (0x31) - Output Mixer5
681 */
682#define WM8990_LRI3LOVOL_MASK 0x07 /* LRI3LOVOL - [8:6] */
683#define WM8990_LRI3LOVOL_SHIFT 6
684#define WM8990_LRBLOVOL_MASK 0x07 /* LRBLOVOL - [5:3] */
685#define WM8990_LRBLOVOL_SHIFT 3
686#define WM8990_LLBLOVOL_MASK 0x07 /* LLBLOVOL - [2:0] */
687#define WM8990_LLBLOVOL_SHIFT 0
688
689/*
690 * R50 (0x32) - Output Mixer6
691 */
692#define WM8990_RLI3ROVOL_MASK 0x07 /* RLI3ROVOL - [8:6] */
693#define WM8990_RLI3ROVOL_SHIFT 6
694#define WM8990_RLBROVOL_MASK 0x07 /* RLBROVOL - [5:3] */
695#define WM8990_RLBROVOL_SHIFT 3
696#define WM8990_RRBROVOL_MASK 0x07 /* RRBROVOL - [2:0] */
697#define WM8990_RRBROVOL_SHIFT 0
698
699/*
700 * R51 (0x33) - Out3/4 Mixer
701 */
702#define WM8990_VSEL_MASK 0x0180 /* VSEL - [8:7] */
703#define WM8990_LI4O3 0x0020 /* LI4O3 */
704#define WM8990_LI4O3_BIT 5
705#define WM8990_LPGAO3 0x0010 /* LPGAO3 */
706#define WM8990_LPGAO3_BIT 4
707#define WM8990_RI4O4 0x0002 /* RI4O4 */
708#define WM8990_RI4O4_BIT 1
709#define WM8990_RPGAO4 0x0001 /* RPGAO4 */
710#define WM8990_RPGAO4_BIT 0
711/*
712 * R52 (0x34) - Line Mixer1
713 */
714#define WM8990_LLOPGALON 0x0040 /* LLOPGALON */
715#define WM8990_LLOPGALON_BIT 6
716#define WM8990_LROPGALON 0x0020 /* LROPGALON */
717#define WM8990_LROPGALON_BIT 5
718#define WM8990_LOPLON 0x0010 /* LOPLON */
719#define WM8990_LOPLON_BIT 4
720#define WM8990_LR12LOP 0x0004 /* LR12LOP */
721#define WM8990_LR12LOP_BIT 2
722#define WM8990_LL12LOP 0x0002 /* LL12LOP */
723#define WM8990_LL12LOP_BIT 1
724#define WM8990_LLOPGALOP 0x0001 /* LLOPGALOP */
725#define WM8990_LLOPGALOP_BIT 0
726/*
727 * R53 (0x35) - Line Mixer2
728 */
729#define WM8990_RROPGARON 0x0040 /* RROPGARON */
730#define WM8990_RROPGARON_BIT 6
731#define WM8990_RLOPGARON 0x0020 /* RLOPGARON */
732#define WM8990_RLOPGARON_BIT 5
733#define WM8990_ROPRON 0x0010 /* ROPRON */
734#define WM8990_ROPRON_BIT 4
735#define WM8990_RL12ROP 0x0004 /* RL12ROP */
736#define WM8990_RL12ROP_BIT 2
737#define WM8990_RR12ROP 0x0002 /* RR12ROP */
738#define WM8990_RR12ROP_BIT 1
739#define WM8990_RROPGAROP 0x0001 /* RROPGAROP */
740#define WM8990_RROPGAROP_BIT 0
741
742/*
743 * R54 (0x36) - Speaker Mixer
744 */
745#define WM8990_LB2SPK 0x0080 /* LB2SPK */
746#define WM8990_LB2SPK_BIT 7
747#define WM8990_RB2SPK 0x0040 /* RB2SPK */
748#define WM8990_RB2SPK_BIT 6
749#define WM8990_LI2SPK 0x0020 /* LI2SPK */
750#define WM8990_LI2SPK_BIT 5
751#define WM8990_RI2SPK 0x0010 /* RI2SPK */
752#define WM8990_RI2SPK_BIT 4
753#define WM8990_LOPGASPK 0x0008 /* LOPGASPK */
754#define WM8990_LOPGASPK_BIT 3
755#define WM8990_ROPGASPK 0x0004 /* ROPGASPK */
756#define WM8990_ROPGASPK_BIT 2
757#define WM8990_LDSPK 0x0002 /* LDSPK */
758#define WM8990_LDSPK_BIT 1
759#define WM8990_RDSPK 0x0001 /* RDSPK */
760#define WM8990_RDSPK_BIT 0
761
762/*
763 * R55 (0x37) - Additional Control
764 */
765#define WM8990_VROI 0x0001 /* VROI */
766
767/*
768 * R56 (0x38) - AntiPOP1
769 */
770#define WM8990_DIS_LLINE 0x0020 /* DIS_LLINE */
771#define WM8990_DIS_RLINE 0x0010 /* DIS_RLINE */
772#define WM8990_DIS_OUT3 0x0008 /* DIS_OUT3 */
773#define WM8990_DIS_OUT4 0x0004 /* DIS_OUT4 */
774#define WM8990_DIS_LOUT 0x0002 /* DIS_LOUT */
775#define WM8990_DIS_ROUT 0x0001 /* DIS_ROUT */
776
777/*
778 * R57 (0x39) - AntiPOP2
779 */
780#define WM8990_SOFTST 0x0040 /* SOFTST */
781#define WM8990_BUFIOEN 0x0008 /* BUFIOEN */
782#define WM8990_BUFDCOPEN 0x0004 /* BUFDCOPEN */
783#define WM8990_POBCTRL 0x0002 /* POBCTRL */
784#define WM8990_VMIDTOG 0x0001 /* VMIDTOG */
785
786/*
787 * R58 (0x3A) - MICBIAS
788 */
789#define WM8990_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */
790#define WM8990_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */
791#define WM8990_MCD 0x0004 /* MCD */
792#define WM8990_MBSEL 0x0001 /* MBSEL */
793
794/*
795 * R60 (0x3C) - PLL1
796 */
797#define WM8990_SDM 0x0080 /* SDM */
798#define WM8990_PRESCALE 0x0040 /* PRESCALE */
799#define WM8990_PLLN_MASK 0x000F /* PLLN - [3:0] */
800
801/*
802 * R61 (0x3D) - PLL2
803 */
804#define WM8990_PLLK1_MASK 0x00FF /* PLLK1 - [7:0] */
805
806/*
807 * R62 (0x3E) - PLL3
808 */
809#define WM8990_PLLK2_MASK 0x00FF /* PLLK2 - [7:0] */
810
811/*
812 * R63 (0x3F) - Internal Driver Bits
813 */
814#define WM8990_INMIXL_PWR_BIT 0
815#define WM8990_AINLMUX_PWR_BIT 1
816#define WM8990_INMIXR_PWR_BIT 2
817#define WM8990_AINRMUX_PWR_BIT 3
818
819struct wm8990_setup_data {
820 unsigned short i2c_address;
821};
822
823#define WM8990_MCLK_DIV 0
824#define WM8990_DACCLK_DIV 1
825#define WM8990_ADCCLK_DIV 2
826#define WM8990_BCLK_DIV 3
827
828extern struct snd_soc_codec_dai wm8990_dai;
829extern struct snd_soc_codec_device soc_codec_dev_wm8990;
830
831#endif /* __WM8990REGISTERDEFS_H__ */
832/*------------------------------ END OF FILE ---------------------------------*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-27 21:24:06 -0400