diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-05-22 10:01:19 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-05-22 10:11:22 -0400 |
commit | 86ed3669f068b514ab85ffd548456a342b3fb8d3 (patch) | |
tree | 16b3063567dbdaeb6375208e070cef4e095c0cf3 /sound/soc/codecs/wm9081.c | |
parent | b4852b793a1dd74ccde5572d8a8f73e948a5b1a1 (diff) |
ASoC: WM9081 mono DAC with integrated 2.6W class AB/D amplifier driver
The WM9081 is designed to provide high power output at low distortion
levels in space-constrained portable applications.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/wm9081.c')
-rw-r--r-- | sound/soc/codecs/wm9081.c | 1532 |
1 files changed, 1532 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c new file mode 100644 index 000000000000..83e3148c258b --- /dev/null +++ b/sound/soc/codecs/wm9081.c | |||
@@ -0,0 +1,1532 @@ | |||
1 | /* | ||
2 | * wm9081.c -- WM9081 ALSA SoC Audio driver | ||
3 | * | ||
4 | * Author: Mark Brown | ||
5 | * | ||
6 | * Copyright 2009 Wolfson Microelectronics plc | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/module.h> | ||
15 | #include <linux/moduleparam.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/delay.h> | ||
18 | #include <linux/pm.h> | ||
19 | #include <linux/i2c.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <sound/core.h> | ||
22 | #include <sound/pcm.h> | ||
23 | #include <sound/pcm_params.h> | ||
24 | #include <sound/soc.h> | ||
25 | #include <sound/soc-dapm.h> | ||
26 | #include <sound/initval.h> | ||
27 | #include <sound/tlv.h> | ||
28 | |||
29 | #include <sound/wm9081.h> | ||
30 | #include "wm9081.h" | ||
31 | |||
32 | static u16 wm9081_reg_defaults[] = { | ||
33 | 0x0000, /* R0 - Software Reset */ | ||
34 | 0x0000, /* R1 */ | ||
35 | 0x00B9, /* R2 - Analogue Lineout */ | ||
36 | 0x00B9, /* R3 - Analogue Speaker PGA */ | ||
37 | 0x0001, /* R4 - VMID Control */ | ||
38 | 0x0068, /* R5 - Bias Control 1 */ | ||
39 | 0x0000, /* R6 */ | ||
40 | 0x0000, /* R7 - Analogue Mixer */ | ||
41 | 0x0000, /* R8 - Anti Pop Control */ | ||
42 | 0x01DB, /* R9 - Analogue Speaker 1 */ | ||
43 | 0x0018, /* R10 - Analogue Speaker 2 */ | ||
44 | 0x0180, /* R11 - Power Management */ | ||
45 | 0x0000, /* R12 - Clock Control 1 */ | ||
46 | 0x0038, /* R13 - Clock Control 2 */ | ||
47 | 0x4000, /* R14 - Clock Control 3 */ | ||
48 | 0x0000, /* R15 */ | ||
49 | 0x0000, /* R16 - FLL Control 1 */ | ||
50 | 0x0200, /* R17 - FLL Control 2 */ | ||
51 | 0x0000, /* R18 - FLL Control 3 */ | ||
52 | 0x0204, /* R19 - FLL Control 4 */ | ||
53 | 0x0000, /* R20 - FLL Control 5 */ | ||
54 | 0x0000, /* R21 */ | ||
55 | 0x0000, /* R22 - Audio Interface 1 */ | ||
56 | 0x0002, /* R23 - Audio Interface 2 */ | ||
57 | 0x0008, /* R24 - Audio Interface 3 */ | ||
58 | 0x0022, /* R25 - Audio Interface 4 */ | ||
59 | 0x0000, /* R26 - Interrupt Status */ | ||
60 | 0x0006, /* R27 - Interrupt Status Mask */ | ||
61 | 0x0000, /* R28 - Interrupt Polarity */ | ||
62 | 0x0000, /* R29 - Interrupt Control */ | ||
63 | 0x00C0, /* R30 - DAC Digital 1 */ | ||
64 | 0x0008, /* R31 - DAC Digital 2 */ | ||
65 | 0x09AF, /* R32 - DRC 1 */ | ||
66 | 0x4201, /* R33 - DRC 2 */ | ||
67 | 0x0000, /* R34 - DRC 3 */ | ||
68 | 0x0000, /* R35 - DRC 4 */ | ||
69 | 0x0000, /* R36 */ | ||
70 | 0x0000, /* R37 */ | ||
71 | 0x0000, /* R38 - Write Sequencer 1 */ | ||
72 | 0x0000, /* R39 - Write Sequencer 2 */ | ||
73 | 0x0002, /* R40 - MW Slave 1 */ | ||
74 | 0x0000, /* R41 */ | ||
75 | 0x0000, /* R42 - EQ 1 */ | ||
76 | 0x0000, /* R43 - EQ 2 */ | ||
77 | 0x0FCA, /* R44 - EQ 3 */ | ||
78 | 0x0400, /* R45 - EQ 4 */ | ||
79 | 0x00B8, /* R46 - EQ 5 */ | ||
80 | 0x1EB5, /* R47 - EQ 6 */ | ||
81 | 0xF145, /* R48 - EQ 7 */ | ||
82 | 0x0B75, /* R49 - EQ 8 */ | ||
83 | 0x01C5, /* R50 - EQ 9 */ | ||
84 | 0x169E, /* R51 - EQ 10 */ | ||
85 | 0xF829, /* R52 - EQ 11 */ | ||
86 | 0x07AD, /* R53 - EQ 12 */ | ||
87 | 0x1103, /* R54 - EQ 13 */ | ||
88 | 0x1C58, /* R55 - EQ 14 */ | ||
89 | 0xF373, /* R56 - EQ 15 */ | ||
90 | 0x0A54, /* R57 - EQ 16 */ | ||
91 | 0x0558, /* R58 - EQ 17 */ | ||
92 | 0x0564, /* R59 - EQ 18 */ | ||
93 | 0x0559, /* R60 - EQ 19 */ | ||
94 | 0x4000, /* R61 - EQ 20 */ | ||
95 | }; | ||
96 | |||
97 | static struct { | ||
98 | int ratio; | ||
99 | int clk_sys_rate; | ||
100 | } clk_sys_rates[] = { | ||
101 | { 64, 0 }, | ||
102 | { 128, 1 }, | ||
103 | { 192, 2 }, | ||
104 | { 256, 3 }, | ||
105 | { 384, 4 }, | ||
106 | { 512, 5 }, | ||
107 | { 768, 6 }, | ||
108 | { 1024, 7 }, | ||
109 | { 1408, 8 }, | ||
110 | { 1536, 9 }, | ||
111 | }; | ||
112 | |||
113 | static struct { | ||
114 | int rate; | ||
115 | int sample_rate; | ||
116 | } sample_rates[] = { | ||
117 | { 8000, 0 }, | ||
118 | { 11025, 1 }, | ||
119 | { 12000, 2 }, | ||
120 | { 16000, 3 }, | ||
121 | { 22050, 4 }, | ||
122 | { 24000, 5 }, | ||
123 | { 32000, 6 }, | ||
124 | { 44100, 7 }, | ||
125 | { 48000, 8 }, | ||
126 | { 88200, 9 }, | ||
127 | { 96000, 10 }, | ||
128 | }; | ||
129 | |||
130 | static struct { | ||
131 | int div; /* *10 due to .5s */ | ||
132 | int bclk_div; | ||
133 | } bclk_divs[] = { | ||
134 | { 10, 0 }, | ||
135 | { 15, 1 }, | ||
136 | { 20, 2 }, | ||
137 | { 30, 3 }, | ||
138 | { 40, 4 }, | ||
139 | { 50, 5 }, | ||
140 | { 55, 6 }, | ||
141 | { 60, 7 }, | ||
142 | { 80, 8 }, | ||
143 | { 100, 9 }, | ||
144 | { 110, 10 }, | ||
145 | { 120, 11 }, | ||
146 | { 160, 12 }, | ||
147 | { 200, 13 }, | ||
148 | { 220, 14 }, | ||
149 | { 240, 15 }, | ||
150 | { 250, 16 }, | ||
151 | { 300, 17 }, | ||
152 | { 320, 18 }, | ||
153 | { 440, 19 }, | ||
154 | { 480, 20 }, | ||
155 | }; | ||
156 | |||
157 | struct wm9081_priv { | ||
158 | struct snd_soc_codec codec; | ||
159 | u16 reg_cache[WM9081_MAX_REGISTER + 1]; | ||
160 | int sysclk_source; | ||
161 | int mclk_rate; | ||
162 | int sysclk_rate; | ||
163 | int fs; | ||
164 | int bclk; | ||
165 | int master; | ||
166 | int fll_fref; | ||
167 | int fll_fout; | ||
168 | struct wm9081_retune_mobile_config *retune; | ||
169 | }; | ||
170 | |||
171 | static int wm9081_reg_is_volatile(int reg) | ||
172 | { | ||
173 | switch (reg) { | ||
174 | default: | ||
175 | return 0; | ||
176 | } | ||
177 | } | ||
178 | |||
179 | static unsigned int wm9081_read_reg_cache(struct snd_soc_codec *codec, | ||
180 | unsigned int reg) | ||
181 | { | ||
182 | u16 *cache = codec->reg_cache; | ||
183 | BUG_ON(reg > WM9081_MAX_REGISTER); | ||
184 | return cache[reg]; | ||
185 | } | ||
186 | |||
187 | static unsigned int wm9081_read_hw(struct snd_soc_codec *codec, u8 reg) | ||
188 | { | ||
189 | struct i2c_msg xfer[2]; | ||
190 | u16 data; | ||
191 | int ret; | ||
192 | struct i2c_client *client = codec->control_data; | ||
193 | |||
194 | BUG_ON(reg > WM9081_MAX_REGISTER); | ||
195 | |||
196 | /* Write register */ | ||
197 | xfer[0].addr = client->addr; | ||
198 | xfer[0].flags = 0; | ||
199 | xfer[0].len = 1; | ||
200 | xfer[0].buf = ® | ||
201 | |||
202 | /* Read data */ | ||
203 | xfer[1].addr = client->addr; | ||
204 | xfer[1].flags = I2C_M_RD; | ||
205 | xfer[1].len = 2; | ||
206 | xfer[1].buf = (u8 *)&data; | ||
207 | |||
208 | ret = i2c_transfer(client->adapter, xfer, 2); | ||
209 | if (ret != 2) { | ||
210 | dev_err(&client->dev, "i2c_transfer() returned %d\n", ret); | ||
211 | return 0; | ||
212 | } | ||
213 | |||
214 | return (data >> 8) | ((data & 0xff) << 8); | ||
215 | } | ||
216 | |||
217 | static unsigned int wm9081_read(struct snd_soc_codec *codec, unsigned int reg) | ||
218 | { | ||
219 | if (wm9081_reg_is_volatile(reg)) | ||
220 | return wm9081_read_hw(codec, reg); | ||
221 | else | ||
222 | return wm9081_read_reg_cache(codec, reg); | ||
223 | } | ||
224 | |||
225 | static int wm9081_write(struct snd_soc_codec *codec, unsigned int reg, | ||
226 | unsigned int value) | ||
227 | { | ||
228 | u16 *cache = codec->reg_cache; | ||
229 | u8 data[3]; | ||
230 | |||
231 | BUG_ON(reg > WM9081_MAX_REGISTER); | ||
232 | |||
233 | if (!wm9081_reg_is_volatile(reg)) | ||
234 | cache[reg] = value; | ||
235 | |||
236 | data[0] = reg; | ||
237 | data[1] = value >> 8; | ||
238 | data[2] = value & 0x00ff; | ||
239 | |||
240 | if (codec->hw_write(codec->control_data, data, 3) == 3) | ||
241 | return 0; | ||
242 | else | ||
243 | return -EIO; | ||
244 | } | ||
245 | |||
246 | static int wm9081_reset(struct snd_soc_codec *codec) | ||
247 | { | ||
248 | return wm9081_write(codec, WM9081_SOFTWARE_RESET, 0); | ||
249 | } | ||
250 | |||
251 | static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0); | ||
252 | static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0); | ||
253 | static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0); | ||
254 | static unsigned int drc_max_tlv[] = { | ||
255 | TLV_DB_RANGE_HEAD(4), | ||
256 | 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0), | ||
257 | 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0), | ||
258 | 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), | ||
259 | 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0), | ||
260 | }; | ||
261 | static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0); | ||
262 | static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0); | ||
263 | |||
264 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | ||
265 | |||
266 | static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0); | ||
267 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1); | ||
268 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); | ||
269 | |||
270 | static const char *drc_high_text[] = { | ||
271 | "1", | ||
272 | "1/2", | ||
273 | "1/4", | ||
274 | "1/8", | ||
275 | "1/16", | ||
276 | "0", | ||
277 | }; | ||
278 | |||
279 | static const struct soc_enum drc_high = | ||
280 | SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text); | ||
281 | |||
282 | static const char *drc_low_text[] = { | ||
283 | "1", | ||
284 | "1/2", | ||
285 | "1/4", | ||
286 | "1/8", | ||
287 | "0", | ||
288 | }; | ||
289 | |||
290 | static const struct soc_enum drc_low = | ||
291 | SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text); | ||
292 | |||
293 | static const char *drc_atk_text[] = { | ||
294 | "181us", | ||
295 | "181us", | ||
296 | "363us", | ||
297 | "726us", | ||
298 | "1.45ms", | ||
299 | "2.9ms", | ||
300 | "5.8ms", | ||
301 | "11.6ms", | ||
302 | "23.2ms", | ||
303 | "46.4ms", | ||
304 | "92.8ms", | ||
305 | "185.6ms", | ||
306 | }; | ||
307 | |||
308 | static const struct soc_enum drc_atk = | ||
309 | SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text); | ||
310 | |||
311 | static const char *drc_dcy_text[] = { | ||
312 | "186ms", | ||
313 | "372ms", | ||
314 | "743ms", | ||
315 | "1.49s", | ||
316 | "2.97s", | ||
317 | "5.94s", | ||
318 | "11.89s", | ||
319 | "23.78s", | ||
320 | "47.56s", | ||
321 | }; | ||
322 | |||
323 | static const struct soc_enum drc_dcy = | ||
324 | SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text); | ||
325 | |||
326 | static const char *drc_qr_dcy_text[] = { | ||
327 | "0.725ms", | ||
328 | "1.45ms", | ||
329 | "5.8ms", | ||
330 | }; | ||
331 | |||
332 | static const struct soc_enum drc_qr_dcy = | ||
333 | SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text); | ||
334 | |||
335 | static const char *dac_deemph_text[] = { | ||
336 | "None", | ||
337 | "32kHz", | ||
338 | "44.1kHz", | ||
339 | "48kHz", | ||
340 | }; | ||
341 | |||
342 | static const struct soc_enum dac_deemph = | ||
343 | SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text); | ||
344 | |||
345 | static const char *speaker_mode_text[] = { | ||
346 | "Class D", | ||
347 | "Class AB", | ||
348 | }; | ||
349 | |||
350 | static const struct soc_enum speaker_mode = | ||
351 | SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text); | ||
352 | |||
353 | static int speaker_mode_get(struct snd_kcontrol *kcontrol, | ||
354 | struct snd_ctl_elem_value *ucontrol) | ||
355 | { | ||
356 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | ||
357 | unsigned int reg; | ||
358 | |||
359 | reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); | ||
360 | if (reg & WM9081_SPK_MODE) | ||
361 | ucontrol->value.integer.value[0] = 1; | ||
362 | else | ||
363 | ucontrol->value.integer.value[0] = 0; | ||
364 | |||
365 | return 0; | ||
366 | } | ||
367 | |||
368 | /* | ||
369 | * Stop any attempts to change speaker mode while the speaker is enabled. | ||
370 | * | ||
371 | * We also have some special anti-pop controls dependant on speaker | ||
372 | * mode which must be changed along with the mode. | ||
373 | */ | ||
374 | static int speaker_mode_put(struct snd_kcontrol *kcontrol, | ||
375 | struct snd_ctl_elem_value *ucontrol) | ||
376 | { | ||
377 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | ||
378 | unsigned int reg_pwr = wm9081_read(codec, WM9081_POWER_MANAGEMENT); | ||
379 | unsigned int reg2 = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); | ||
380 | |||
381 | /* Are we changing anything? */ | ||
382 | if (ucontrol->value.integer.value[0] == | ||
383 | ((reg2 & WM9081_SPK_MODE) != 0)) | ||
384 | return 0; | ||
385 | |||
386 | /* Don't try to change modes while enabled */ | ||
387 | if (reg_pwr & WM9081_SPK_ENA) | ||
388 | return -EINVAL; | ||
389 | |||
390 | if (ucontrol->value.integer.value[0]) { | ||
391 | /* Class AB */ | ||
392 | reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL); | ||
393 | reg2 |= WM9081_SPK_MODE; | ||
394 | } else { | ||
395 | /* Class D */ | ||
396 | reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL; | ||
397 | reg2 &= ~WM9081_SPK_MODE; | ||
398 | } | ||
399 | |||
400 | wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2); | ||
401 | |||
402 | return 0; | ||
403 | } | ||
404 | |||
405 | static const struct snd_kcontrol_new wm9081_snd_controls[] = { | ||
406 | SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv), | ||
407 | SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv), | ||
408 | |||
409 | SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv), | ||
410 | |||
411 | SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1), | ||
412 | SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0), | ||
413 | SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv), | ||
414 | |||
415 | SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0), | ||
416 | SOC_ENUM("DRC High Slope", drc_high), | ||
417 | SOC_ENUM("DRC Low Slope", drc_low), | ||
418 | SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv), | ||
419 | SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv), | ||
420 | SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv), | ||
421 | SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv), | ||
422 | SOC_ENUM("DRC Attack", drc_atk), | ||
423 | SOC_ENUM("DRC Decay", drc_dcy), | ||
424 | SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0), | ||
425 | SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv), | ||
426 | SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy), | ||
427 | SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv), | ||
428 | |||
429 | SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0), | ||
430 | |||
431 | SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0), | ||
432 | SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0), | ||
433 | SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1), | ||
434 | SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0), | ||
435 | SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0, | ||
436 | out_tlv), | ||
437 | SOC_ENUM("DAC Deemphasis", dac_deemph), | ||
438 | SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put), | ||
439 | }; | ||
440 | |||
441 | static const struct snd_kcontrol_new wm9081_eq_controls[] = { | ||
442 | SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv), | ||
443 | SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv), | ||
444 | SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv), | ||
445 | SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv), | ||
446 | SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv), | ||
447 | }; | ||
448 | |||
449 | static const struct snd_kcontrol_new mixer[] = { | ||
450 | SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0), | ||
451 | SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0), | ||
452 | SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0), | ||
453 | }; | ||
454 | |||
455 | static int speaker_event(struct snd_soc_dapm_widget *w, | ||
456 | struct snd_kcontrol *kcontrol, int event) | ||
457 | { | ||
458 | struct snd_soc_codec *codec = w->codec; | ||
459 | unsigned int reg = wm9081_read(codec, WM9081_POWER_MANAGEMENT); | ||
460 | |||
461 | switch (event) { | ||
462 | case SND_SOC_DAPM_POST_PMU: | ||
463 | reg |= WM9081_SPK_ENA; | ||
464 | break; | ||
465 | |||
466 | case SND_SOC_DAPM_PRE_PMD: | ||
467 | reg &= ~WM9081_SPK_ENA; | ||
468 | break; | ||
469 | } | ||
470 | |||
471 | wm9081_write(codec, WM9081_POWER_MANAGEMENT, reg); | ||
472 | |||
473 | return 0; | ||
474 | } | ||
475 | |||
476 | struct _fll_div { | ||
477 | u16 fll_fratio; | ||
478 | u16 fll_outdiv; | ||
479 | u16 fll_clk_ref_div; | ||
480 | u16 n; | ||
481 | u16 k; | ||
482 | }; | ||
483 | |||
484 | /* The size in bits of the FLL divide multiplied by 10 | ||
485 | * to allow rounding later */ | ||
486 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | ||
487 | |||
488 | static struct { | ||
489 | unsigned int min; | ||
490 | unsigned int max; | ||
491 | u16 fll_fratio; | ||
492 | int ratio; | ||
493 | } fll_fratios[] = { | ||
494 | { 0, 64000, 4, 16 }, | ||
495 | { 64000, 128000, 3, 8 }, | ||
496 | { 128000, 256000, 2, 4 }, | ||
497 | { 256000, 1000000, 1, 2 }, | ||
498 | { 1000000, 13500000, 0, 1 }, | ||
499 | }; | ||
500 | |||
501 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | ||
502 | unsigned int Fout) | ||
503 | { | ||
504 | u64 Kpart; | ||
505 | unsigned int K, Ndiv, Nmod, target; | ||
506 | unsigned int div; | ||
507 | int i; | ||
508 | |||
509 | /* Fref must be <=13.5MHz */ | ||
510 | div = 1; | ||
511 | while ((Fref / div) > 13500000) { | ||
512 | div *= 2; | ||
513 | |||
514 | if (div > 8) { | ||
515 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | ||
516 | Fref); | ||
517 | return -EINVAL; | ||
518 | } | ||
519 | } | ||
520 | fll_div->fll_clk_ref_div = div / 2; | ||
521 | |||
522 | pr_debug("Fref=%u Fout=%u\n", Fref, Fout); | ||
523 | |||
524 | /* Apply the division for our remaining calculations */ | ||
525 | Fref /= div; | ||
526 | |||
527 | /* Fvco should be 90-100MHz; don't check the upper bound */ | ||
528 | div = 0; | ||
529 | target = Fout * 2; | ||
530 | while (target < 90000000) { | ||
531 | div++; | ||
532 | target *= 2; | ||
533 | if (div > 7) { | ||
534 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | ||
535 | Fout); | ||
536 | return -EINVAL; | ||
537 | } | ||
538 | } | ||
539 | fll_div->fll_outdiv = div; | ||
540 | |||
541 | pr_debug("Fvco=%dHz\n", target); | ||
542 | |||
543 | /* Find an appropraite FLL_FRATIO and factor it out of the target */ | ||
544 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { | ||
545 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | ||
546 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | ||
547 | target /= fll_fratios[i].ratio; | ||
548 | break; | ||
549 | } | ||
550 | } | ||
551 | if (i == ARRAY_SIZE(fll_fratios)) { | ||
552 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | ||
553 | return -EINVAL; | ||
554 | } | ||
555 | |||
556 | /* Now, calculate N.K */ | ||
557 | Ndiv = target / Fref; | ||
558 | |||
559 | fll_div->n = Ndiv; | ||
560 | Nmod = target % Fref; | ||
561 | pr_debug("Nmod=%d\n", Nmod); | ||
562 | |||
563 | /* Calculate fractional part - scale up so we can round. */ | ||
564 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | ||
565 | |||
566 | do_div(Kpart, Fref); | ||
567 | |||
568 | K = Kpart & 0xFFFFFFFF; | ||
569 | |||
570 | if ((K % 10) >= 5) | ||
571 | K += 5; | ||
572 | |||
573 | /* Move down to proper range now rounding is done */ | ||
574 | fll_div->k = K / 10; | ||
575 | |||
576 | pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", | ||
577 | fll_div->n, fll_div->k, | ||
578 | fll_div->fll_fratio, fll_div->fll_outdiv, | ||
579 | fll_div->fll_clk_ref_div); | ||
580 | |||
581 | return 0; | ||
582 | } | ||
583 | |||
584 | static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id, | ||
585 | unsigned int Fref, unsigned int Fout) | ||
586 | { | ||
587 | struct wm9081_priv *wm9081 = codec->private_data; | ||
588 | u16 reg1, reg4, reg5; | ||
589 | struct _fll_div fll_div; | ||
590 | int ret; | ||
591 | int clk_sys_reg; | ||
592 | |||
593 | /* Any change? */ | ||
594 | if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout) | ||
595 | return 0; | ||
596 | |||
597 | /* Disable the FLL */ | ||
598 | if (Fout == 0) { | ||
599 | dev_dbg(codec->dev, "FLL disabled\n"); | ||
600 | wm9081->fll_fref = 0; | ||
601 | wm9081->fll_fout = 0; | ||
602 | |||
603 | return 0; | ||
604 | } | ||
605 | |||
606 | ret = fll_factors(&fll_div, Fref, Fout); | ||
607 | if (ret != 0) | ||
608 | return ret; | ||
609 | |||
610 | reg5 = wm9081_read(codec, WM9081_FLL_CONTROL_5); | ||
611 | reg5 &= ~WM9081_FLL_CLK_SRC_MASK; | ||
612 | |||
613 | switch (fll_id) { | ||
614 | case WM9081_SYSCLK_FLL_MCLK: | ||
615 | reg5 |= 0x1; | ||
616 | break; | ||
617 | |||
618 | default: | ||
619 | dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); | ||
620 | return -EINVAL; | ||
621 | } | ||
622 | |||
623 | /* Disable CLK_SYS while we reconfigure */ | ||
624 | clk_sys_reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); | ||
625 | if (clk_sys_reg & WM9081_CLK_SYS_ENA) | ||
626 | wm9081_write(codec, WM9081_CLOCK_CONTROL_3, | ||
627 | clk_sys_reg & ~WM9081_CLK_SYS_ENA); | ||
628 | |||
629 | /* Any FLL configuration change requires that the FLL be | ||
630 | * disabled first. */ | ||
631 | reg1 = wm9081_read(codec, WM9081_FLL_CONTROL_1); | ||
632 | reg1 &= ~WM9081_FLL_ENA; | ||
633 | wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); | ||
634 | |||
635 | /* Apply the configuration */ | ||
636 | if (fll_div.k) | ||
637 | reg1 |= WM9081_FLL_FRAC_MASK; | ||
638 | else | ||
639 | reg1 &= ~WM9081_FLL_FRAC_MASK; | ||
640 | wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); | ||
641 | |||
642 | wm9081_write(codec, WM9081_FLL_CONTROL_2, | ||
643 | (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) | | ||
644 | (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT)); | ||
645 | wm9081_write(codec, WM9081_FLL_CONTROL_3, fll_div.k); | ||
646 | |||
647 | reg4 = wm9081_read(codec, WM9081_FLL_CONTROL_4); | ||
648 | reg4 &= ~WM9081_FLL_N_MASK; | ||
649 | reg4 |= fll_div.n << WM9081_FLL_N_SHIFT; | ||
650 | wm9081_write(codec, WM9081_FLL_CONTROL_4, reg4); | ||
651 | |||
652 | reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK; | ||
653 | reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; | ||
654 | wm9081_write(codec, WM9081_FLL_CONTROL_5, reg5); | ||
655 | |||
656 | /* Enable the FLL */ | ||
657 | wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); | ||
658 | |||
659 | /* Then bring CLK_SYS up again if it was disabled */ | ||
660 | if (clk_sys_reg & WM9081_CLK_SYS_ENA) | ||
661 | wm9081_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg); | ||
662 | |||
663 | dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); | ||
664 | |||
665 | wm9081->fll_fref = Fref; | ||
666 | wm9081->fll_fout = Fout; | ||
667 | |||
668 | return 0; | ||
669 | } | ||
670 | |||
671 | static int configure_clock(struct snd_soc_codec *codec) | ||
672 | { | ||
673 | struct wm9081_priv *wm9081 = codec->private_data; | ||
674 | int new_sysclk, i, target; | ||
675 | unsigned int reg; | ||
676 | int ret = 0; | ||
677 | int mclkdiv = 0; | ||
678 | int fll = 0; | ||
679 | |||
680 | switch (wm9081->sysclk_source) { | ||
681 | case WM9081_SYSCLK_MCLK: | ||
682 | if (wm9081->mclk_rate > 12225000) { | ||
683 | mclkdiv = 1; | ||
684 | wm9081->sysclk_rate = wm9081->mclk_rate / 2; | ||
685 | } else { | ||
686 | wm9081->sysclk_rate = wm9081->mclk_rate; | ||
687 | } | ||
688 | wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0); | ||
689 | break; | ||
690 | |||
691 | case WM9081_SYSCLK_FLL_MCLK: | ||
692 | /* If we have a sample rate calculate a CLK_SYS that | ||
693 | * gives us a suitable DAC configuration, plus BCLK. | ||
694 | * Ideally we would check to see if we can clock | ||
695 | * directly from MCLK and only use the FLL if this is | ||
696 | * not the case, though care must be taken with free | ||
697 | * running mode. | ||
698 | */ | ||
699 | if (wm9081->master && wm9081->bclk) { | ||
700 | /* Make sure we can generate CLK_SYS and BCLK | ||
701 | * and that we've got 3MHz for optimal | ||
702 | * performance. */ | ||
703 | for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { | ||
704 | target = wm9081->fs * clk_sys_rates[i].ratio; | ||
705 | if (target >= wm9081->bclk && | ||
706 | target > 3000000) | ||
707 | new_sysclk = target; | ||
708 | } | ||
709 | } else if (wm9081->fs) { | ||
710 | for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { | ||
711 | new_sysclk = clk_sys_rates[i].ratio | ||
712 | * wm9081->fs; | ||
713 | if (new_sysclk > 3000000) | ||
714 | break; | ||
715 | } | ||
716 | } else { | ||
717 | new_sysclk = 12288000; | ||
718 | } | ||
719 | |||
720 | ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, | ||
721 | wm9081->mclk_rate, new_sysclk); | ||
722 | if (ret == 0) { | ||
723 | wm9081->sysclk_rate = new_sysclk; | ||
724 | |||
725 | /* Switch SYSCLK over to FLL */ | ||
726 | fll = 1; | ||
727 | } else { | ||
728 | wm9081->sysclk_rate = wm9081->mclk_rate; | ||
729 | } | ||
730 | break; | ||
731 | |||
732 | default: | ||
733 | return -EINVAL; | ||
734 | } | ||
735 | |||
736 | reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_1); | ||
737 | if (mclkdiv) | ||
738 | reg |= WM9081_MCLKDIV2; | ||
739 | else | ||
740 | reg &= ~WM9081_MCLKDIV2; | ||
741 | wm9081_write(codec, WM9081_CLOCK_CONTROL_1, reg); | ||
742 | |||
743 | reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); | ||
744 | if (fll) | ||
745 | reg |= WM9081_CLK_SRC_SEL; | ||
746 | else | ||
747 | reg &= ~WM9081_CLK_SRC_SEL; | ||
748 | wm9081_write(codec, WM9081_CLOCK_CONTROL_3, reg); | ||
749 | |||
750 | dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate); | ||
751 | |||
752 | return ret; | ||
753 | } | ||
754 | |||
755 | static int clk_sys_event(struct snd_soc_dapm_widget *w, | ||
756 | struct snd_kcontrol *kcontrol, int event) | ||
757 | { | ||
758 | struct snd_soc_codec *codec = w->codec; | ||
759 | struct wm9081_priv *wm9081 = codec->private_data; | ||
760 | |||
761 | /* This should be done on init() for bypass paths */ | ||
762 | switch (wm9081->sysclk_source) { | ||
763 | case WM9081_SYSCLK_MCLK: | ||
764 | dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate); | ||
765 | break; | ||
766 | case WM9081_SYSCLK_FLL_MCLK: | ||
767 | dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n", | ||
768 | wm9081->mclk_rate); | ||
769 | break; | ||
770 | default: | ||
771 | dev_err(codec->dev, "System clock not configured\n"); | ||
772 | return -EINVAL; | ||
773 | } | ||
774 | |||
775 | switch (event) { | ||
776 | case SND_SOC_DAPM_PRE_PMU: | ||
777 | configure_clock(codec); | ||
778 | break; | ||
779 | |||
780 | case SND_SOC_DAPM_POST_PMD: | ||
781 | /* Disable the FLL if it's running */ | ||
782 | wm9081_set_fll(codec, 0, 0, 0); | ||
783 | break; | ||
784 | } | ||
785 | |||
786 | return 0; | ||
787 | } | ||
788 | |||
789 | static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = { | ||
790 | SND_SOC_DAPM_INPUT("IN1"), | ||
791 | SND_SOC_DAPM_INPUT("IN2"), | ||
792 | |||
793 | SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0), | ||
794 | |||
795 | SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0, | ||
796 | mixer, ARRAY_SIZE(mixer)), | ||
797 | |||
798 | SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0), | ||
799 | |||
800 | SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0, | ||
801 | speaker_event, | ||
802 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | ||
803 | |||
804 | SND_SOC_DAPM_OUTPUT("LINEOUT"), | ||
805 | SND_SOC_DAPM_OUTPUT("SPKN"), | ||
806 | SND_SOC_DAPM_OUTPUT("SPKP"), | ||
807 | |||
808 | SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event, | ||
809 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | ||
810 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0), | ||
811 | SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0), | ||
812 | }; | ||
813 | |||
814 | |||
815 | static const struct snd_soc_dapm_route audio_paths[] = { | ||
816 | { "DAC", NULL, "CLK_SYS" }, | ||
817 | { "DAC", NULL, "CLK_DSP" }, | ||
818 | |||
819 | { "Mixer", "IN1 Switch", "IN1" }, | ||
820 | { "Mixer", "IN2 Switch", "IN2" }, | ||
821 | { "Mixer", "Playback Switch", "DAC" }, | ||
822 | |||
823 | { "LINEOUT PGA", NULL, "Mixer" }, | ||
824 | { "LINEOUT PGA", NULL, "TOCLK" }, | ||
825 | { "LINEOUT PGA", NULL, "CLK_SYS" }, | ||
826 | |||
827 | { "LINEOUT", NULL, "LINEOUT PGA" }, | ||
828 | |||
829 | { "Speaker PGA", NULL, "Mixer" }, | ||
830 | { "Speaker PGA", NULL, "TOCLK" }, | ||
831 | { "Speaker PGA", NULL, "CLK_SYS" }, | ||
832 | |||
833 | { "SPKN", NULL, "Speaker PGA" }, | ||
834 | { "SPKP", NULL, "Speaker PGA" }, | ||
835 | }; | ||
836 | |||
837 | static int wm9081_set_bias_level(struct snd_soc_codec *codec, | ||
838 | enum snd_soc_bias_level level) | ||
839 | { | ||
840 | u16 reg; | ||
841 | |||
842 | switch (level) { | ||
843 | case SND_SOC_BIAS_ON: | ||
844 | break; | ||
845 | |||
846 | case SND_SOC_BIAS_PREPARE: | ||
847 | /* VMID=2*40k */ | ||
848 | reg = wm9081_read(codec, WM9081_VMID_CONTROL); | ||
849 | reg &= ~WM9081_VMID_SEL_MASK; | ||
850 | reg |= 0x2; | ||
851 | wm9081_write(codec, WM9081_VMID_CONTROL, reg); | ||
852 | |||
853 | /* Normal bias current */ | ||
854 | reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); | ||
855 | reg &= ~WM9081_STBY_BIAS_ENA; | ||
856 | wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); | ||
857 | break; | ||
858 | |||
859 | case SND_SOC_BIAS_STANDBY: | ||
860 | /* Initial cold start */ | ||
861 | if (codec->bias_level == SND_SOC_BIAS_OFF) { | ||
862 | /* Disable LINEOUT discharge */ | ||
863 | reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); | ||
864 | reg &= ~WM9081_LINEOUT_DISCH; | ||
865 | wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); | ||
866 | |||
867 | /* Select startup bias source */ | ||
868 | reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); | ||
869 | reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA; | ||
870 | wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); | ||
871 | |||
872 | /* VMID 2*4k; Soft VMID ramp enable */ | ||
873 | reg = wm9081_read(codec, WM9081_VMID_CONTROL); | ||
874 | reg |= WM9081_VMID_RAMP | 0x6; | ||
875 | wm9081_write(codec, WM9081_VMID_CONTROL, reg); | ||
876 | |||
877 | mdelay(100); | ||
878 | |||
879 | /* Normal bias enable & soft start off */ | ||
880 | reg |= WM9081_BIAS_ENA; | ||
881 | reg &= ~WM9081_VMID_RAMP; | ||
882 | wm9081_write(codec, WM9081_VMID_CONTROL, reg); | ||
883 | |||
884 | /* Standard bias source */ | ||
885 | reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); | ||
886 | reg &= ~WM9081_BIAS_SRC; | ||
887 | wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); | ||
888 | } | ||
889 | |||
890 | /* VMID 2*240k */ | ||
891 | reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); | ||
892 | reg &= ~WM9081_VMID_SEL_MASK; | ||
893 | reg |= 0x40; | ||
894 | wm9081_write(codec, WM9081_VMID_CONTROL, reg); | ||
895 | |||
896 | /* Standby bias current on */ | ||
897 | reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); | ||
898 | reg |= WM9081_STBY_BIAS_ENA; | ||
899 | wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); | ||
900 | break; | ||
901 | |||
902 | case SND_SOC_BIAS_OFF: | ||
903 | /* Startup bias source */ | ||
904 | reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); | ||
905 | reg |= WM9081_BIAS_SRC; | ||
906 | wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); | ||
907 | |||
908 | /* Disable VMID and biases with soft ramping */ | ||
909 | reg = wm9081_read(codec, WM9081_VMID_CONTROL); | ||
910 | reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA); | ||
911 | reg |= WM9081_VMID_RAMP; | ||
912 | wm9081_write(codec, WM9081_VMID_CONTROL, reg); | ||
913 | |||
914 | /* Actively discharge LINEOUT */ | ||
915 | reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); | ||
916 | reg |= WM9081_LINEOUT_DISCH; | ||
917 | wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); | ||
918 | break; | ||
919 | } | ||
920 | |||
921 | codec->bias_level = level; | ||
922 | |||
923 | return 0; | ||
924 | } | ||
925 | |||
926 | static int wm9081_set_dai_fmt(struct snd_soc_dai *dai, | ||
927 | unsigned int fmt) | ||
928 | { | ||
929 | struct snd_soc_codec *codec = dai->codec; | ||
930 | struct wm9081_priv *wm9081 = codec->private_data; | ||
931 | unsigned int aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); | ||
932 | |||
933 | aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV | | ||
934 | WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK); | ||
935 | |||
936 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | ||
937 | case SND_SOC_DAIFMT_CBS_CFS: | ||
938 | wm9081->master = 0; | ||
939 | break; | ||
940 | case SND_SOC_DAIFMT_CBS_CFM: | ||
941 | aif2 |= WM9081_LRCLK_DIR; | ||
942 | wm9081->master = 1; | ||
943 | break; | ||
944 | case SND_SOC_DAIFMT_CBM_CFS: | ||
945 | aif2 |= WM9081_BCLK_DIR; | ||
946 | wm9081->master = 1; | ||
947 | break; | ||
948 | case SND_SOC_DAIFMT_CBM_CFM: | ||
949 | aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR; | ||
950 | wm9081->master = 1; | ||
951 | break; | ||
952 | default: | ||
953 | return -EINVAL; | ||
954 | } | ||
955 | |||
956 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | ||
957 | case SND_SOC_DAIFMT_DSP_B: | ||
958 | aif2 |= WM9081_AIF_LRCLK_INV; | ||
959 | case SND_SOC_DAIFMT_DSP_A: | ||
960 | aif2 |= 0x3; | ||
961 | break; | ||
962 | case SND_SOC_DAIFMT_I2S: | ||
963 | aif2 |= 0x2; | ||
964 | break; | ||
965 | case SND_SOC_DAIFMT_RIGHT_J: | ||
966 | break; | ||
967 | case SND_SOC_DAIFMT_LEFT_J: | ||
968 | aif2 |= 0x1; | ||
969 | break; | ||
970 | default: | ||
971 | return -EINVAL; | ||
972 | } | ||
973 | |||
974 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | ||
975 | case SND_SOC_DAIFMT_DSP_A: | ||
976 | case SND_SOC_DAIFMT_DSP_B: | ||
977 | /* frame inversion not valid for DSP modes */ | ||
978 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | ||
979 | case SND_SOC_DAIFMT_NB_NF: | ||
980 | break; | ||
981 | case SND_SOC_DAIFMT_IB_NF: | ||
982 | aif2 |= WM9081_AIF_BCLK_INV; | ||
983 | break; | ||
984 | default: | ||
985 | return -EINVAL; | ||
986 | } | ||
987 | break; | ||
988 | |||
989 | case SND_SOC_DAIFMT_I2S: | ||
990 | case SND_SOC_DAIFMT_RIGHT_J: | ||
991 | case SND_SOC_DAIFMT_LEFT_J: | ||
992 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | ||
993 | case SND_SOC_DAIFMT_NB_NF: | ||
994 | break; | ||
995 | case SND_SOC_DAIFMT_IB_IF: | ||
996 | aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV; | ||
997 | break; | ||
998 | case SND_SOC_DAIFMT_IB_NF: | ||
999 | aif2 |= WM9081_AIF_BCLK_INV; | ||
1000 | break; | ||
1001 | case SND_SOC_DAIFMT_NB_IF: | ||
1002 | aif2 |= WM9081_AIF_LRCLK_INV; | ||
1003 | break; | ||
1004 | default: | ||
1005 | return -EINVAL; | ||
1006 | } | ||
1007 | break; | ||
1008 | default: | ||
1009 | return -EINVAL; | ||
1010 | } | ||
1011 | |||
1012 | wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); | ||
1013 | |||
1014 | return 0; | ||
1015 | } | ||
1016 | |||
1017 | static int wm9081_hw_params(struct snd_pcm_substream *substream, | ||
1018 | struct snd_pcm_hw_params *params, | ||
1019 | struct snd_soc_dai *dai) | ||
1020 | { | ||
1021 | struct snd_soc_codec *codec = dai->codec; | ||
1022 | struct wm9081_priv *wm9081 = codec->private_data; | ||
1023 | int ret, i, best, best_val, cur_val; | ||
1024 | unsigned int clk_ctrl2, aif1, aif2, aif3, aif4; | ||
1025 | |||
1026 | clk_ctrl2 = wm9081_read(codec, WM9081_CLOCK_CONTROL_2); | ||
1027 | clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK); | ||
1028 | |||
1029 | aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); | ||
1030 | |||
1031 | aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); | ||
1032 | aif2 &= ~WM9081_AIF_WL_MASK; | ||
1033 | |||
1034 | aif3 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_3); | ||
1035 | aif3 &= ~WM9081_BCLK_DIV_MASK; | ||
1036 | |||
1037 | aif4 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_4); | ||
1038 | aif4 &= ~WM9081_LRCLK_RATE_MASK; | ||
1039 | |||
1040 | /* What BCLK do we need? */ | ||
1041 | wm9081->fs = params_rate(params); | ||
1042 | wm9081->bclk = 2 * wm9081->fs; | ||
1043 | switch (params_format(params)) { | ||
1044 | case SNDRV_PCM_FORMAT_S16_LE: | ||
1045 | wm9081->bclk *= 16; | ||
1046 | break; | ||
1047 | case SNDRV_PCM_FORMAT_S20_3LE: | ||
1048 | wm9081->bclk *= 20; | ||
1049 | aif2 |= 0x4; | ||
1050 | break; | ||
1051 | case SNDRV_PCM_FORMAT_S24_LE: | ||
1052 | wm9081->bclk *= 24; | ||
1053 | aif2 |= 0x8; | ||
1054 | break; | ||
1055 | case SNDRV_PCM_FORMAT_S32_LE: | ||
1056 | wm9081->bclk *= 32; | ||
1057 | aif2 |= 0xc; | ||
1058 | break; | ||
1059 | default: | ||
1060 | return -EINVAL; | ||
1061 | } | ||
1062 | |||
1063 | if (aif1 & WM9081_AIFDAC_TDM_MODE_MASK) { | ||
1064 | int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >> | ||
1065 | WM9081_AIFDAC_TDM_MODE_SHIFT) + 1; | ||
1066 | wm9081->bclk *= slots; | ||
1067 | } | ||
1068 | |||
1069 | dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk); | ||
1070 | |||
1071 | ret = configure_clock(codec); | ||
1072 | if (ret != 0) | ||
1073 | return ret; | ||
1074 | |||
1075 | /* Select nearest CLK_SYS_RATE */ | ||
1076 | best = 0; | ||
1077 | best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio) | ||
1078 | - wm9081->fs); | ||
1079 | for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { | ||
1080 | cur_val = abs((wm9081->sysclk_rate / | ||
1081 | clk_sys_rates[i].ratio) - wm9081->fs);; | ||
1082 | if (cur_val < best_val) { | ||
1083 | best = i; | ||
1084 | best_val = cur_val; | ||
1085 | } | ||
1086 | } | ||
1087 | dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", | ||
1088 | clk_sys_rates[best].ratio); | ||
1089 | clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate | ||
1090 | << WM9081_CLK_SYS_RATE_SHIFT); | ||
1091 | |||
1092 | /* SAMPLE_RATE */ | ||
1093 | best = 0; | ||
1094 | best_val = abs(wm9081->fs - sample_rates[0].rate); | ||
1095 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | ||
1096 | /* Closest match */ | ||
1097 | cur_val = abs(wm9081->fs - sample_rates[i].rate); | ||
1098 | if (cur_val < best_val) { | ||
1099 | best = i; | ||
1100 | best_val = cur_val; | ||
1101 | } | ||
1102 | } | ||
1103 | dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", | ||
1104 | sample_rates[best].rate); | ||
1105 | clk_ctrl2 |= (sample_rates[i].sample_rate << WM9081_SAMPLE_RATE_SHIFT); | ||
1106 | |||
1107 | /* BCLK_DIV */ | ||
1108 | best = 0; | ||
1109 | best_val = INT_MAX; | ||
1110 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | ||
1111 | cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div) | ||
1112 | - wm9081->bclk; | ||
1113 | if (cur_val < 0) /* Table is sorted */ | ||
1114 | break; | ||
1115 | if (cur_val < best_val) { | ||
1116 | best = i; | ||
1117 | best_val = cur_val; | ||
1118 | } | ||
1119 | } | ||
1120 | wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div; | ||
1121 | dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", | ||
1122 | bclk_divs[best].div, wm9081->bclk); | ||
1123 | aif3 |= bclk_divs[best].bclk_div; | ||
1124 | |||
1125 | /* LRCLK is a simple fraction of BCLK */ | ||
1126 | dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs); | ||
1127 | aif4 |= wm9081->bclk / wm9081->fs; | ||
1128 | |||
1129 | /* Apply a ReTune Mobile configuration if it's in use */ | ||
1130 | if (wm9081->retune) { | ||
1131 | struct wm9081_retune_mobile_config *retune = wm9081->retune; | ||
1132 | struct wm9081_retune_mobile_setting *s; | ||
1133 | int eq1; | ||
1134 | |||
1135 | best = 0; | ||
1136 | best_val = abs(retune->configs[0].rate - wm9081->fs); | ||
1137 | for (i = 0; i < retune->num_configs; i++) { | ||
1138 | cur_val = abs(retune->configs[i].rate - wm9081->fs); | ||
1139 | if (cur_val < best_val) { | ||
1140 | best_val = cur_val; | ||
1141 | best = i; | ||
1142 | } | ||
1143 | } | ||
1144 | s = &retune->configs[best]; | ||
1145 | |||
1146 | dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n", | ||
1147 | s->name, s->rate); | ||
1148 | |||
1149 | /* If the EQ is enabled then disable it while we write out */ | ||
1150 | eq1 = wm9081_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA; | ||
1151 | if (eq1 & WM9081_EQ_ENA) | ||
1152 | wm9081_write(codec, WM9081_EQ_1, 0); | ||
1153 | |||
1154 | /* Write out the other values */ | ||
1155 | for (i = 1; i < ARRAY_SIZE(s->config); i++) | ||
1156 | wm9081_write(codec, WM9081_EQ_1 + i, s->config[i]); | ||
1157 | |||
1158 | eq1 |= (s->config[0] & ~WM9081_EQ_ENA); | ||
1159 | wm9081_write(codec, WM9081_EQ_1, eq1); | ||
1160 | } | ||
1161 | |||
1162 | wm9081_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2); | ||
1163 | wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); | ||
1164 | wm9081_write(codec, WM9081_AUDIO_INTERFACE_3, aif3); | ||
1165 | wm9081_write(codec, WM9081_AUDIO_INTERFACE_4, aif4); | ||
1166 | |||
1167 | return 0; | ||
1168 | } | ||
1169 | |||
1170 | static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute) | ||
1171 | { | ||
1172 | struct snd_soc_codec *codec = codec_dai->codec; | ||
1173 | unsigned int reg; | ||
1174 | |||
1175 | reg = wm9081_read(codec, WM9081_DAC_DIGITAL_2); | ||
1176 | |||
1177 | if (mute) | ||
1178 | reg |= WM9081_DAC_MUTE; | ||
1179 | else | ||
1180 | reg &= ~WM9081_DAC_MUTE; | ||
1181 | |||
1182 | wm9081_write(codec, WM9081_DAC_DIGITAL_2, reg); | ||
1183 | |||
1184 | return 0; | ||
1185 | } | ||
1186 | |||
1187 | static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai, | ||
1188 | int clk_id, unsigned int freq, int dir) | ||
1189 | { | ||
1190 | struct snd_soc_codec *codec = codec_dai->codec; | ||
1191 | struct wm9081_priv *wm9081 = codec->private_data; | ||
1192 | |||
1193 | switch (clk_id) { | ||
1194 | case WM9081_SYSCLK_MCLK: | ||
1195 | case WM9081_SYSCLK_FLL_MCLK: | ||
1196 | wm9081->sysclk_source = clk_id; | ||
1197 | wm9081->mclk_rate = freq; | ||
1198 | break; | ||
1199 | |||
1200 | default: | ||
1201 | return -EINVAL; | ||
1202 | } | ||
1203 | |||
1204 | return 0; | ||
1205 | } | ||
1206 | |||
1207 | static int wm9081_set_tdm_slot(struct snd_soc_dai *dai, | ||
1208 | unsigned int mask, int slots) | ||
1209 | { | ||
1210 | struct snd_soc_codec *codec = dai->codec; | ||
1211 | unsigned int aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); | ||
1212 | |||
1213 | aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK); | ||
1214 | |||
1215 | if (slots < 1 || slots > 4) | ||
1216 | return -EINVAL; | ||
1217 | |||
1218 | aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT; | ||
1219 | |||
1220 | switch (mask) { | ||
1221 | case 1: | ||
1222 | break; | ||
1223 | case 2: | ||
1224 | aif1 |= 0x10; | ||
1225 | break; | ||
1226 | case 4: | ||
1227 | aif1 |= 0x20; | ||
1228 | break; | ||
1229 | case 8: | ||
1230 | aif1 |= 0x30; | ||
1231 | break; | ||
1232 | default: | ||
1233 | return -EINVAL; | ||
1234 | } | ||
1235 | |||
1236 | wm9081_write(codec, WM9081_AUDIO_INTERFACE_1, aif1); | ||
1237 | |||
1238 | return 0; | ||
1239 | } | ||
1240 | |||
1241 | #define WM9081_RATES SNDRV_PCM_RATE_8000_96000 | ||
1242 | |||
1243 | #define WM9081_FORMATS \ | ||
1244 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | ||
1245 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | ||
1246 | |||
1247 | static struct snd_soc_dai_ops wm9081_dai_ops = { | ||
1248 | .hw_params = wm9081_hw_params, | ||
1249 | .set_sysclk = wm9081_set_sysclk, | ||
1250 | .set_fmt = wm9081_set_dai_fmt, | ||
1251 | .digital_mute = wm9081_digital_mute, | ||
1252 | .set_tdm_slot = wm9081_set_tdm_slot, | ||
1253 | }; | ||
1254 | |||
1255 | /* We report two channels because the CODEC processes a stereo signal, even | ||
1256 | * though it is only capable of handling a mono output. | ||
1257 | */ | ||
1258 | struct snd_soc_dai wm9081_dai = { | ||
1259 | .name = "WM9081", | ||
1260 | .playback = { | ||
1261 | .stream_name = "HiFi Playback", | ||
1262 | .channels_min = 1, | ||
1263 | .channels_max = 2, | ||
1264 | .rates = WM9081_RATES, | ||
1265 | .formats = WM9081_FORMATS, | ||
1266 | }, | ||
1267 | .ops = &wm9081_dai_ops, | ||
1268 | }; | ||
1269 | EXPORT_SYMBOL_GPL(wm9081_dai); | ||
1270 | |||
1271 | |||
1272 | static struct snd_soc_codec *wm9081_codec; | ||
1273 | |||
1274 | static int wm9081_probe(struct platform_device *pdev) | ||
1275 | { | ||
1276 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | ||
1277 | struct snd_soc_codec *codec; | ||
1278 | struct wm9081_priv *wm9081; | ||
1279 | int ret = 0; | ||
1280 | |||
1281 | if (wm9081_codec == NULL) { | ||
1282 | dev_err(&pdev->dev, "Codec device not registered\n"); | ||
1283 | return -ENODEV; | ||
1284 | } | ||
1285 | |||
1286 | socdev->card->codec = wm9081_codec; | ||
1287 | codec = wm9081_codec; | ||
1288 | wm9081 = codec->private_data; | ||
1289 | |||
1290 | /* register pcms */ | ||
1291 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | ||
1292 | if (ret < 0) { | ||
1293 | dev_err(codec->dev, "failed to create pcms: %d\n", ret); | ||
1294 | goto pcm_err; | ||
1295 | } | ||
1296 | |||
1297 | snd_soc_add_controls(codec, wm9081_snd_controls, | ||
1298 | ARRAY_SIZE(wm9081_snd_controls)); | ||
1299 | if (!wm9081->retune) { | ||
1300 | dev_dbg(codec->dev, | ||
1301 | "No ReTune Mobile data, using normal EQ\n"); | ||
1302 | snd_soc_add_controls(codec, wm9081_eq_controls, | ||
1303 | ARRAY_SIZE(wm9081_eq_controls)); | ||
1304 | } | ||
1305 | |||
1306 | snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets, | ||
1307 | ARRAY_SIZE(wm9081_dapm_widgets)); | ||
1308 | snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); | ||
1309 | snd_soc_dapm_new_widgets(codec); | ||
1310 | |||
1311 | ret = snd_soc_init_card(socdev); | ||
1312 | if (ret < 0) { | ||
1313 | dev_err(codec->dev, "failed to register card: %d\n", ret); | ||
1314 | goto card_err; | ||
1315 | } | ||
1316 | |||
1317 | return ret; | ||
1318 | |||
1319 | card_err: | ||
1320 | snd_soc_free_pcms(socdev); | ||
1321 | snd_soc_dapm_free(socdev); | ||
1322 | pcm_err: | ||
1323 | return ret; | ||
1324 | } | ||
1325 | |||
1326 | static int wm9081_remove(struct platform_device *pdev) | ||
1327 | { | ||
1328 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | ||
1329 | |||
1330 | snd_soc_free_pcms(socdev); | ||
1331 | snd_soc_dapm_free(socdev); | ||
1332 | |||
1333 | return 0; | ||
1334 | } | ||
1335 | |||
1336 | #ifdef CONFIG_PM | ||
1337 | static int wm9081_suspend(struct platform_device *pdev, pm_message_t state) | ||
1338 | { | ||
1339 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | ||
1340 | struct snd_soc_codec *codec = socdev->card->codec; | ||
1341 | |||
1342 | wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF); | ||
1343 | |||
1344 | return 0; | ||
1345 | } | ||
1346 | |||
1347 | static int wm9081_resume(struct platform_device *pdev) | ||
1348 | { | ||
1349 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | ||
1350 | struct snd_soc_codec *codec = socdev->card->codec; | ||
1351 | u16 *reg_cache = codec->reg_cache; | ||
1352 | int i; | ||
1353 | |||
1354 | for (i = 0; i < codec->reg_cache_size; i++) { | ||
1355 | if (i == WM9081_SOFTWARE_RESET) | ||
1356 | continue; | ||
1357 | |||
1358 | wm9081_write(codec, i, reg_cache[i]); | ||
1359 | } | ||
1360 | |||
1361 | wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | ||
1362 | |||
1363 | return 0; | ||
1364 | } | ||
1365 | #else | ||
1366 | #define wm9081_suspend NULL | ||
1367 | #define wm9081_resume NULL | ||
1368 | #endif | ||
1369 | |||
1370 | struct snd_soc_codec_device soc_codec_dev_wm9081 = { | ||
1371 | .probe = wm9081_probe, | ||
1372 | .remove = wm9081_remove, | ||
1373 | .suspend = wm9081_suspend, | ||
1374 | .resume = wm9081_resume, | ||
1375 | }; | ||
1376 | EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081); | ||
1377 | |||
1378 | static int wm9081_register(struct wm9081_priv *wm9081) | ||
1379 | { | ||
1380 | struct snd_soc_codec *codec = &wm9081->codec; | ||
1381 | int ret; | ||
1382 | u16 reg; | ||
1383 | |||
1384 | if (wm9081_codec) { | ||
1385 | dev_err(codec->dev, "Another WM9081 is registered\n"); | ||
1386 | ret = -EINVAL; | ||
1387 | goto err; | ||
1388 | } | ||
1389 | |||
1390 | mutex_init(&codec->mutex); | ||
1391 | INIT_LIST_HEAD(&codec->dapm_widgets); | ||
1392 | INIT_LIST_HEAD(&codec->dapm_paths); | ||
1393 | |||
1394 | codec->private_data = wm9081; | ||
1395 | codec->name = "WM9081"; | ||
1396 | codec->owner = THIS_MODULE; | ||
1397 | codec->read = wm9081_read; | ||
1398 | codec->write = wm9081_write; | ||
1399 | codec->dai = &wm9081_dai; | ||
1400 | codec->num_dai = 1; | ||
1401 | codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache); | ||
1402 | codec->reg_cache = &wm9081->reg_cache; | ||
1403 | codec->bias_level = SND_SOC_BIAS_OFF; | ||
1404 | codec->set_bias_level = wm9081_set_bias_level; | ||
1405 | |||
1406 | memcpy(codec->reg_cache, wm9081_reg_defaults, | ||
1407 | sizeof(wm9081_reg_defaults)); | ||
1408 | |||
1409 | reg = wm9081_read_hw(codec, WM9081_SOFTWARE_RESET); | ||
1410 | if (reg != 0x9081) { | ||
1411 | dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg); | ||
1412 | ret = -EINVAL; | ||
1413 | goto err; | ||
1414 | } | ||
1415 | |||
1416 | ret = wm9081_reset(codec); | ||
1417 | if (ret < 0) { | ||
1418 | dev_err(codec->dev, "Failed to issue reset\n"); | ||
1419 | return ret; | ||
1420 | } | ||
1421 | |||
1422 | wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | ||
1423 | |||
1424 | /* Enable zero cross by default */ | ||
1425 | reg = wm9081_read(codec, WM9081_ANALOGUE_LINEOUT); | ||
1426 | wm9081_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC); | ||
1427 | reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_PGA); | ||
1428 | wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_PGA, | ||
1429 | reg | WM9081_SPKPGAZC); | ||
1430 | |||
1431 | wm9081_dai.dev = codec->dev; | ||
1432 | |||
1433 | wm9081_codec = codec; | ||
1434 | |||
1435 | ret = snd_soc_register_codec(codec); | ||
1436 | if (ret != 0) { | ||
1437 | dev_err(codec->dev, "Failed to register codec: %d\n", ret); | ||
1438 | return ret; | ||
1439 | } | ||
1440 | |||
1441 | ret = snd_soc_register_dai(&wm9081_dai); | ||
1442 | if (ret != 0) { | ||
1443 | dev_err(codec->dev, "Failed to register DAI: %d\n", ret); | ||
1444 | snd_soc_unregister_codec(codec); | ||
1445 | return ret; | ||
1446 | } | ||
1447 | |||
1448 | return 0; | ||
1449 | |||
1450 | err: | ||
1451 | kfree(wm9081); | ||
1452 | return ret; | ||
1453 | } | ||
1454 | |||
1455 | static void wm9081_unregister(struct wm9081_priv *wm9081) | ||
1456 | { | ||
1457 | wm9081_set_bias_level(&wm9081->codec, SND_SOC_BIAS_OFF); | ||
1458 | snd_soc_unregister_dai(&wm9081_dai); | ||
1459 | snd_soc_unregister_codec(&wm9081->codec); | ||
1460 | kfree(wm9081); | ||
1461 | wm9081_codec = NULL; | ||
1462 | } | ||
1463 | |||
1464 | static __devinit int wm9081_i2c_probe(struct i2c_client *i2c, | ||
1465 | const struct i2c_device_id *id) | ||
1466 | { | ||
1467 | struct wm9081_priv *wm9081; | ||
1468 | struct snd_soc_codec *codec; | ||
1469 | |||
1470 | wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL); | ||
1471 | if (wm9081 == NULL) | ||
1472 | return -ENOMEM; | ||
1473 | |||
1474 | codec = &wm9081->codec; | ||
1475 | codec->hw_write = (hw_write_t)i2c_master_send; | ||
1476 | wm9081->retune = i2c->dev.platform_data; | ||
1477 | |||
1478 | i2c_set_clientdata(i2c, wm9081); | ||
1479 | codec->control_data = i2c; | ||
1480 | |||
1481 | codec->dev = &i2c->dev; | ||
1482 | |||
1483 | return wm9081_register(wm9081); | ||
1484 | } | ||
1485 | |||
1486 | static __devexit int wm9081_i2c_remove(struct i2c_client *client) | ||
1487 | { | ||
1488 | struct wm9081_priv *wm9081 = i2c_get_clientdata(client); | ||
1489 | wm9081_unregister(wm9081); | ||
1490 | return 0; | ||
1491 | } | ||
1492 | |||
1493 | static const struct i2c_device_id wm9081_i2c_id[] = { | ||
1494 | { "wm9081", 0 }, | ||
1495 | { } | ||
1496 | }; | ||
1497 | MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id); | ||
1498 | |||
1499 | static struct i2c_driver wm9081_i2c_driver = { | ||
1500 | .driver = { | ||
1501 | .name = "wm9081", | ||
1502 | .owner = THIS_MODULE, | ||
1503 | }, | ||
1504 | .probe = wm9081_i2c_probe, | ||
1505 | .remove = __devexit_p(wm9081_i2c_remove), | ||
1506 | .id_table = wm9081_i2c_id, | ||
1507 | }; | ||
1508 | |||
1509 | static int __init wm9081_modinit(void) | ||
1510 | { | ||
1511 | int ret; | ||
1512 | |||
1513 | ret = i2c_add_driver(&wm9081_i2c_driver); | ||
1514 | if (ret != 0) { | ||
1515 | printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n", | ||
1516 | ret); | ||
1517 | } | ||
1518 | |||
1519 | return ret; | ||
1520 | } | ||
1521 | module_init(wm9081_modinit); | ||
1522 | |||
1523 | static void __exit wm9081_exit(void) | ||
1524 | { | ||
1525 | i2c_del_driver(&wm9081_i2c_driver); | ||
1526 | } | ||
1527 | module_exit(wm9081_exit); | ||
1528 | |||
1529 | |||
1530 | MODULE_DESCRIPTION("ASoC WM9081 driver"); | ||
1531 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | ||
1532 | MODULE_LICENSE("GPL"); | ||