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authorMark Brown <broonie@opensource.wolfsonmicro.com>2012-06-11 07:10:50 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-06-25 04:55:02 -0400
commitec8ffe1868f45a72eb243f1c9797806be58276fd (patch)
tree6f7e407415aae35e15158c559fa59379a5b0b6dc /sound/soc/codecs/wm8996.c
parentd4b3d0fbb7617a65cb919ac86110b0790ae568c5 (diff)
ASoC: wm8996: Move register default configuration to I2C probe
This gets the registers set up as early as possible, mainly useful for the GPIOs to ensure that they're in the correct mode. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/wm8996.c')
-rw-r--r--sound/soc/codecs/wm8996.c331
1 files changed, 180 insertions, 151 deletions
diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
index 1579880ac05d..00f183dfa454 100644
--- a/sound/soc/codecs/wm8996.c
+++ b/sound/soc/codecs/wm8996.c
@@ -2619,7 +2619,7 @@ static int wm8996_probe(struct snd_soc_codec *codec)
2619 int ret; 2619 int ret;
2620 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2620 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2621 struct i2c_client *i2c = to_i2c_client(codec->dev); 2621 struct i2c_client *i2c = to_i2c_client(codec->dev);
2622 int i, irq_flags; 2622 int irq_flags;
2623 2623
2624 wm8996->codec = codec; 2624 wm8996->codec = codec;
2625 2625
@@ -2634,162 +2634,12 @@ static int wm8996_probe(struct snd_soc_codec *codec)
2634 goto err; 2634 goto err;
2635 } 2635 }
2636 2636
2637 /* Apply platform data settings */
2638 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2639 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2640 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2641 wm8996->pdata.inr_mode);
2642
2643 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2644 if (!wm8996->pdata.gpio_default[i])
2645 continue;
2646
2647 snd_soc_write(codec, WM8996_GPIO_1 + i,
2648 wm8996->pdata.gpio_default[i] & 0xffff);
2649 }
2650
2651 if (wm8996->pdata.spkmute_seq)
2652 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2653 WM8996_SPK_MUTE_ENDIAN |
2654 WM8996_SPK_MUTE_SEQ1_MASK,
2655 wm8996->pdata.spkmute_seq);
2656
2657 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2658 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2659 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2660
2661 /* Latch volume update bits */
2662 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2663 WM8996_IN1_VU, WM8996_IN1_VU);
2664 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2665 WM8996_IN1_VU, WM8996_IN1_VU);
2666
2667 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2668 WM8996_DAC1_VU, WM8996_DAC1_VU);
2669 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2670 WM8996_DAC1_VU, WM8996_DAC1_VU);
2671 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2672 WM8996_DAC2_VU, WM8996_DAC2_VU);
2673 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2674 WM8996_DAC2_VU, WM8996_DAC2_VU);
2675
2676 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2677 WM8996_DAC1_VU, WM8996_DAC1_VU);
2678 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2679 WM8996_DAC1_VU, WM8996_DAC1_VU);
2680 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2681 WM8996_DAC2_VU, WM8996_DAC2_VU);
2682 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2683 WM8996_DAC2_VU, WM8996_DAC2_VU);
2684
2685 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2686 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2687 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2688 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2689 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2690 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2691 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2692 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2693
2694 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2695 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2696 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2697 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2698 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2699 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2700 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2701 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2702
2703 /* No support currently for the underclocked TDM modes and
2704 * pick a default TDM layout with each channel pair working with
2705 * slots 0 and 1. */
2706 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2707 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2708 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2709 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2710 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2711 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2712 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2713 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2714 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2715 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2716 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2717 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2718 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2719 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2720 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2721 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2722 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2723 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2724 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2725 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2726 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2727 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2728 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2729 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2730
2731 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2732 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2733 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2734 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2735 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2736 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2737 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2738 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2739
2740 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2741 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2742 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2743 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2744 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2745 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2746 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2747 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2748 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2749 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2750 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2751 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2752 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2753 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2754 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2755 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2756 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2757 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2758 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2759 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2760 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2761 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2762 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2763 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2764
2765 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2766 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2767 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2768 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2769 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2770 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2771 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2772 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2773
2774 if (wm8996->pdata.num_retune_mobile_cfgs) 2637 if (wm8996->pdata.num_retune_mobile_cfgs)
2775 wm8996_retune_mobile_pdata(codec); 2638 wm8996_retune_mobile_pdata(codec);
2776 else 2639 else
2777 snd_soc_add_codec_controls(codec, wm8996_eq_controls, 2640 snd_soc_add_codec_controls(codec, wm8996_eq_controls,
2778 ARRAY_SIZE(wm8996_eq_controls)); 2641 ARRAY_SIZE(wm8996_eq_controls));
2779 2642
2780 /* If the TX LRCLK pins are not in LRCLK mode configure the
2781 * AIFs to source their clocks from the RX LRCLKs.
2782 */
2783 if ((snd_soc_read(codec, WM8996_GPIO_1)))
2784 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2785 WM8996_AIF1TX_LRCLK_MODE,
2786 WM8996_AIF1TX_LRCLK_MODE);
2787
2788 if ((snd_soc_read(codec, WM8996_GPIO_2)))
2789 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2790 WM8996_AIF2TX_LRCLK_MODE,
2791 WM8996_AIF2TX_LRCLK_MODE);
2792
2793 if (i2c->irq) { 2643 if (i2c->irq) {
2794 if (wm8996->pdata.irq_flags) 2644 if (wm8996->pdata.irq_flags)
2795 irq_flags = wm8996->pdata.irq_flags; 2645 irq_flags = wm8996->pdata.irq_flags;
@@ -3023,6 +2873,185 @@ static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
3023 2873
3024 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 2874 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3025 2875
2876 /* Apply platform data settings */
2877 regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL,
2878 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2879 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2880 wm8996->pdata.inr_mode);
2881
2882 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2883 if (!wm8996->pdata.gpio_default[i])
2884 continue;
2885
2886 regmap_write(wm8996->regmap, WM8996_GPIO_1 + i,
2887 wm8996->pdata.gpio_default[i] & 0xffff);
2888 }
2889
2890 if (wm8996->pdata.spkmute_seq)
2891 regmap_update_bits(wm8996->regmap,
2892 WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2893 WM8996_SPK_MUTE_ENDIAN |
2894 WM8996_SPK_MUTE_SEQ1_MASK,
2895 wm8996->pdata.spkmute_seq);
2896
2897 regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2,
2898 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2899 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2900
2901 /* Latch volume update bits */
2902 regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME,
2903 WM8996_IN1_VU, WM8996_IN1_VU);
2904 regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME,
2905 WM8996_IN1_VU, WM8996_IN1_VU);
2906
2907 regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME,
2908 WM8996_DAC1_VU, WM8996_DAC1_VU);
2909 regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME,
2910 WM8996_DAC1_VU, WM8996_DAC1_VU);
2911 regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME,
2912 WM8996_DAC2_VU, WM8996_DAC2_VU);
2913 regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME,
2914 WM8996_DAC2_VU, WM8996_DAC2_VU);
2915
2916 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME,
2917 WM8996_DAC1_VU, WM8996_DAC1_VU);
2918 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME,
2919 WM8996_DAC1_VU, WM8996_DAC1_VU);
2920 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME,
2921 WM8996_DAC2_VU, WM8996_DAC2_VU);
2922 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME,
2923 WM8996_DAC2_VU, WM8996_DAC2_VU);
2924
2925 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME,
2926 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2927 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME,
2928 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2929 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME,
2930 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2931 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME,
2932 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2933
2934 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME,
2935 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2936 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME,
2937 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2938 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME,
2939 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2940 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME,
2941 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2942
2943 /* No support currently for the underclocked TDM modes and
2944 * pick a default TDM layout with each channel pair working with
2945 * slots 0 and 1. */
2946 regmap_update_bits(wm8996->regmap,
2947 WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2948 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2949 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2950 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2951 regmap_update_bits(wm8996->regmap,
2952 WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2953 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2954 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2955 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2956 regmap_update_bits(wm8996->regmap,
2957 WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2958 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2959 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2960 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2961 regmap_update_bits(wm8996->regmap,
2962 WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2963 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2964 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2965 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2966 regmap_update_bits(wm8996->regmap,
2967 WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2968 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2969 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2970 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2971 regmap_update_bits(wm8996->regmap,
2972 WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2973 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2974 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2975 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2976
2977 regmap_update_bits(wm8996->regmap,
2978 WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2979 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2980 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2981 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2982 regmap_update_bits(wm8996->regmap,
2983 WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2984 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2985 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2986 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2987
2988 regmap_update_bits(wm8996->regmap,
2989 WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2990 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2991 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2992 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2993 regmap_update_bits(wm8996->regmap,
2994 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2995 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2996 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2997 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2998 regmap_update_bits(wm8996->regmap,
2999 WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
3000 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
3001 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3002 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
3003 regmap_update_bits(wm8996->regmap,
3004 WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
3005 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
3006 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3007 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
3008 regmap_update_bits(wm8996->regmap,
3009 WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
3010 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
3011 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3012 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
3013 regmap_update_bits(wm8996->regmap,
3014 WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
3015 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
3016 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3017 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
3018
3019 regmap_update_bits(wm8996->regmap,
3020 WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
3021 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
3022 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
3023 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
3024 regmap_update_bits(wm8996->regmap,
3025 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
3026 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
3027 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
3028 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
3029
3030 /* If the TX LRCLK pins are not in LRCLK mode configure the
3031 * AIFs to source their clocks from the RX LRCLKs.
3032 */
3033 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, &reg);
3034 if (ret != 0) {
3035 dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret);
3036 goto err_regmap;
3037 }
3038
3039 if (reg & WM8996_GP1_FN_MASK)
3040 regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2,
3041 WM8996_AIF1TX_LRCLK_MODE,
3042 WM8996_AIF1TX_LRCLK_MODE);
3043
3044 ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, &reg);
3045 if (ret != 0) {
3046 dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret);
3047 goto err_regmap;
3048 }
3049
3050 if (reg & WM8996_GP2_FN_MASK)
3051 regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2,
3052 WM8996_AIF2TX_LRCLK_MODE,
3053 WM8996_AIF2TX_LRCLK_MODE);
3054
3026 wm8996_init_gpio(wm8996); 3055 wm8996_init_gpio(wm8996);
3027 3056
3028 ret = snd_soc_register_codec(&i2c->dev, 3057 ret = snd_soc_register_codec(&i2c->dev,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 09:47:49 -0500