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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-01-29 12:47:12 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-02-01 13:37:01 -0500
commit9e6e96a197a03752d39a63e4f83e0b707ccedad7 (patch)
tree3ccd7e51d3e37a33fb14d75472b3336c5202abc8 /sound/soc/codecs/wm8994.c
parentbe587ef4f20cb5a0e42264909fa702a24081a160 (diff)
ASoC: Add WM8994 CODEC driver
The WM8994 is a highly integrated ultra-low power hi-fi audio subsystem designed for smartphones and other portable devices rich in multimedia features. It provides advanced digital mixing facilities enabling low power high quality interconnection of CPU, baseband and other audio sources through flexible digital and analogue routing, and integrates a class W headphone driver and stereo class D speaker drivers. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/wm8994.c')
-rw-r--r--sound/soc/codecs/wm8994.c3870
1 files changed, 3870 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
new file mode 100644
index 000000000000..5dd4b299f69e
--- /dev/null
+++ b/sound/soc/codecs/wm8994.c
@@ -0,0 +1,3870 @@
1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include <linux/mfd/wm8994/core.h>
31#include <linux/mfd/wm8994/registers.h>
32#include <linux/mfd/wm8994/pdata.h>
33#include <linux/mfd/wm8994/gpio.h>
34
35#include "wm8994.h"
36#include "wm_hubs.h"
37
38static struct snd_soc_codec *wm8994_codec;
39struct snd_soc_codec_device soc_codec_dev_wm8994;
40
41struct fll_config {
42 int src;
43 int in;
44 int out;
45};
46
47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
50static int wm8994_drc_base[] = {
51 WM8994_AIF1_DRC1_1,
52 WM8994_AIF1_DRC2_1,
53 WM8994_AIF2_DRC_1,
54};
55
56static int wm8994_retune_mobile_base[] = {
57 WM8994_AIF1_DAC1_EQ_GAINS_1,
58 WM8994_AIF1_DAC2_EQ_GAINS_1,
59 WM8994_AIF2_EQ_GAINS_1,
60};
61
62#define WM8994_REG_CACHE_SIZE 0x621
63
64/* codec private data */
65struct wm8994_priv {
66 struct wm_hubs_data hubs;
67 struct snd_soc_codec codec;
68 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
69 int sysclk[2];
70 int sysclk_rate[2];
71 int mclk[2];
72 int aifclk[2];
73 struct fll_config fll[2], fll_suspend[2];
74
75 int dac_rates[2];
76 int lrclk_shared[2];
77
78 /* Platform dependant DRC configuration */
79 const char **drc_texts;
80 int drc_cfg[WM8994_NUM_DRC];
81 struct soc_enum drc_enum;
82
83 /* Platform dependant ReTune mobile configuration */
84 int num_retune_mobile_texts;
85 const char **retune_mobile_texts;
86 int retune_mobile_cfg[WM8994_NUM_EQ];
87 struct soc_enum retune_mobile_enum;
88
89 struct wm8994_pdata *pdata;
90};
91
92static struct {
93 unsigned short readable; /* Mask of readable bits */
94 unsigned short writable; /* Mask of writable bits */
95 unsigned short vol; /* Mask of volatile bits */
96} access_masks[] = {
97 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Software Reset */
98 { 0x3B37, 0x3B37, 0x0000 }, /* R1 - Power Management (1) */
99 { 0x6BF0, 0x6BF0, 0x0000 }, /* R2 - Power Management (2) */
100 { 0x3FF0, 0x3FF0, 0x0000 }, /* R3 - Power Management (3) */
101 { 0x3F3F, 0x3F3F, 0x0000 }, /* R4 - Power Management (4) */
102 { 0x3F0F, 0x3F0F, 0x0000 }, /* R5 - Power Management (5) */
103 { 0x003F, 0x003F, 0x0000 }, /* R6 - Power Management (6) */
104 { 0x0000, 0x0000, 0x0000 }, /* R7 */
105 { 0x0000, 0x0000, 0x0000 }, /* R8 */
106 { 0x0000, 0x0000, 0x0000 }, /* R9 */
107 { 0x0000, 0x0000, 0x0000 }, /* R10 */
108 { 0x0000, 0x0000, 0x0000 }, /* R11 */
109 { 0x0000, 0x0000, 0x0000 }, /* R12 */
110 { 0x0000, 0x0000, 0x0000 }, /* R13 */
111 { 0x0000, 0x0000, 0x0000 }, /* R14 */
112 { 0x0000, 0x0000, 0x0000 }, /* R15 */
113 { 0x0000, 0x0000, 0x0000 }, /* R16 */
114 { 0x0000, 0x0000, 0x0000 }, /* R17 */
115 { 0x0000, 0x0000, 0x0000 }, /* R18 */
116 { 0x0000, 0x0000, 0x0000 }, /* R19 */
117 { 0x0000, 0x0000, 0x0000 }, /* R20 */
118 { 0x01C0, 0x01C0, 0x0000 }, /* R21 - Input Mixer (1) */
119 { 0x0000, 0x0000, 0x0000 }, /* R22 */
120 { 0x0000, 0x0000, 0x0000 }, /* R23 */
121 { 0x00DF, 0x01DF, 0x0000 }, /* R24 - Left Line Input 1&2 Volume */
122 { 0x00DF, 0x01DF, 0x0000 }, /* R25 - Left Line Input 3&4 Volume */
123 { 0x00DF, 0x01DF, 0x0000 }, /* R26 - Right Line Input 1&2 Volume */
124 { 0x00DF, 0x01DF, 0x0000 }, /* R27 - Right Line Input 3&4 Volume */
125 { 0x00FF, 0x01FF, 0x0000 }, /* R28 - Left Output Volume */
126 { 0x00FF, 0x01FF, 0x0000 }, /* R29 - Right Output Volume */
127 { 0x0077, 0x0077, 0x0000 }, /* R30 - Line Outputs Volume */
128 { 0x0030, 0x0030, 0x0000 }, /* R31 - HPOUT2 Volume */
129 { 0x00FF, 0x01FF, 0x0000 }, /* R32 - Left OPGA Volume */
130 { 0x00FF, 0x01FF, 0x0000 }, /* R33 - Right OPGA Volume */
131 { 0x007F, 0x007F, 0x0000 }, /* R34 - SPKMIXL Attenuation */
132 { 0x017F, 0x017F, 0x0000 }, /* R35 - SPKMIXR Attenuation */
133 { 0x003F, 0x003F, 0x0000 }, /* R36 - SPKOUT Mixers */
134 { 0x003F, 0x003F, 0x0000 }, /* R37 - ClassD */
135 { 0x00FF, 0x01FF, 0x0000 }, /* R38 - Speaker Volume Left */
136 { 0x00FF, 0x01FF, 0x0000 }, /* R39 - Speaker Volume Right */
137 { 0x00FF, 0x00FF, 0x0000 }, /* R40 - Input Mixer (2) */
138 { 0x01B7, 0x01B7, 0x0000 }, /* R41 - Input Mixer (3) */
139 { 0x01B7, 0x01B7, 0x0000 }, /* R42 - Input Mixer (4) */
140 { 0x01C7, 0x01C7, 0x0000 }, /* R43 - Input Mixer (5) */
141 { 0x01C7, 0x01C7, 0x0000 }, /* R44 - Input Mixer (6) */
142 { 0x01FF, 0x01FF, 0x0000 }, /* R45 - Output Mixer (1) */
143 { 0x01FF, 0x01FF, 0x0000 }, /* R46 - Output Mixer (2) */
144 { 0x0FFF, 0x0FFF, 0x0000 }, /* R47 - Output Mixer (3) */
145 { 0x0FFF, 0x0FFF, 0x0000 }, /* R48 - Output Mixer (4) */
146 { 0x0FFF, 0x0FFF, 0x0000 }, /* R49 - Output Mixer (5) */
147 { 0x0FFF, 0x0FFF, 0x0000 }, /* R50 - Output Mixer (6) */
148 { 0x0038, 0x0038, 0x0000 }, /* R51 - HPOUT2 Mixer */
149 { 0x0077, 0x0077, 0x0000 }, /* R52 - Line Mixer (1) */
150 { 0x0077, 0x0077, 0x0000 }, /* R53 - Line Mixer (2) */
151 { 0x03FF, 0x03FF, 0x0000 }, /* R54 - Speaker Mixer */
152 { 0x00C1, 0x00C1, 0x0000 }, /* R55 - Additional Control */
153 { 0x00F0, 0x00F0, 0x0000 }, /* R56 - AntiPOP (1) */
154 { 0x01EF, 0x01EF, 0x0000 }, /* R57 - AntiPOP (2) */
155 { 0x00FF, 0x00FF, 0x0000 }, /* R58 - MICBIAS */
156 { 0x000F, 0x000F, 0x0000 }, /* R59 - LDO 1 */
157 { 0x0007, 0x0007, 0x0000 }, /* R60 - LDO 2 */
158 { 0x0000, 0x0000, 0x0000 }, /* R61 */
159 { 0x0000, 0x0000, 0x0000 }, /* R62 */
160 { 0x0000, 0x0000, 0x0000 }, /* R63 */
161 { 0x0000, 0x0000, 0x0000 }, /* R64 */
162 { 0x0000, 0x0000, 0x0000 }, /* R65 */
163 { 0x0000, 0x0000, 0x0000 }, /* R66 */
164 { 0x0000, 0x0000, 0x0000 }, /* R67 */
165 { 0x0000, 0x0000, 0x0000 }, /* R68 */
166 { 0x0000, 0x0000, 0x0000 }, /* R69 */
167 { 0x0000, 0x0000, 0x0000 }, /* R70 */
168 { 0x0000, 0x0000, 0x0000 }, /* R71 */
169 { 0x0000, 0x0000, 0x0000 }, /* R72 */
170 { 0x0000, 0x0000, 0x0000 }, /* R73 */
171 { 0x0000, 0x0000, 0x0000 }, /* R74 */
172 { 0x0000, 0x0000, 0x0000 }, /* R75 */
173 { 0x8000, 0x8000, 0x0000 }, /* R76 - Charge Pump (1) */
174 { 0x0000, 0x0000, 0x0000 }, /* R77 */
175 { 0x0000, 0x0000, 0x0000 }, /* R78 */
176 { 0x0000, 0x0000, 0x0000 }, /* R79 */
177 { 0x0000, 0x0000, 0x0000 }, /* R80 */
178 { 0x0301, 0x0301, 0x0000 }, /* R81 - Class W (1) */
179 { 0x0000, 0x0000, 0x0000 }, /* R82 */
180 { 0x0000, 0x0000, 0x0000 }, /* R83 */
181 { 0x333F, 0x333F, 0x0000 }, /* R84 - DC Servo (1) */
182 { 0x0FEF, 0x0FEF, 0x0000 }, /* R85 - DC Servo (2) */
183 { 0x0000, 0x0000, 0x0000 }, /* R86 */
184 { 0xFFFF, 0xFFFF, 0x0000 }, /* R87 - DC Servo (4) */
185 { 0x0333, 0x0000, 0x0000 }, /* R88 - DC Servo Readback */
186 { 0x0000, 0x0000, 0x0000 }, /* R89 */
187 { 0x0000, 0x0000, 0x0000 }, /* R90 */
188 { 0x0000, 0x0000, 0x0000 }, /* R91 */
189 { 0x0000, 0x0000, 0x0000 }, /* R92 */
190 { 0x0000, 0x0000, 0x0000 }, /* R93 */
191 { 0x0000, 0x0000, 0x0000 }, /* R94 */
192 { 0x0000, 0x0000, 0x0000 }, /* R95 */
193 { 0x00EE, 0x00EE, 0x0000 }, /* R96 - Analogue HP (1) */
194 { 0x0000, 0x0000, 0x0000 }, /* R97 */
195 { 0x0000, 0x0000, 0x0000 }, /* R98 */
196 { 0x0000, 0x0000, 0x0000 }, /* R99 */
197 { 0x0000, 0x0000, 0x0000 }, /* R100 */
198 { 0x0000, 0x0000, 0x0000 }, /* R101 */
199 { 0x0000, 0x0000, 0x0000 }, /* R102 */
200 { 0x0000, 0x0000, 0x0000 }, /* R103 */
201 { 0x0000, 0x0000, 0x0000 }, /* R104 */
202 { 0x0000, 0x0000, 0x0000 }, /* R105 */
203 { 0x0000, 0x0000, 0x0000 }, /* R106 */
204 { 0x0000, 0x0000, 0x0000 }, /* R107 */
205 { 0x0000, 0x0000, 0x0000 }, /* R108 */
206 { 0x0000, 0x0000, 0x0000 }, /* R109 */
207 { 0x0000, 0x0000, 0x0000 }, /* R110 */
208 { 0x0000, 0x0000, 0x0000 }, /* R111 */
209 { 0x0000, 0x0000, 0x0000 }, /* R112 */
210 { 0x0000, 0x0000, 0x0000 }, /* R113 */
211 { 0x0000, 0x0000, 0x0000 }, /* R114 */
212 { 0x0000, 0x0000, 0x0000 }, /* R115 */
213 { 0x0000, 0x0000, 0x0000 }, /* R116 */
214 { 0x0000, 0x0000, 0x0000 }, /* R117 */
215 { 0x0000, 0x0000, 0x0000 }, /* R118 */
216 { 0x0000, 0x0000, 0x0000 }, /* R119 */
217 { 0x0000, 0x0000, 0x0000 }, /* R120 */
218 { 0x0000, 0x0000, 0x0000 }, /* R121 */
219 { 0x0000, 0x0000, 0x0000 }, /* R122 */
220 { 0x0000, 0x0000, 0x0000 }, /* R123 */
221 { 0x0000, 0x0000, 0x0000 }, /* R124 */
222 { 0x0000, 0x0000, 0x0000 }, /* R125 */
223 { 0x0000, 0x0000, 0x0000 }, /* R126 */
224 { 0x0000, 0x0000, 0x0000 }, /* R127 */
225 { 0x0000, 0x0000, 0x0000 }, /* R128 */
226 { 0x0000, 0x0000, 0x0000 }, /* R129 */
227 { 0x0000, 0x0000, 0x0000 }, /* R130 */
228 { 0x0000, 0x0000, 0x0000 }, /* R131 */
229 { 0x0000, 0x0000, 0x0000 }, /* R132 */
230 { 0x0000, 0x0000, 0x0000 }, /* R133 */
231 { 0x0000, 0x0000, 0x0000 }, /* R134 */
232 { 0x0000, 0x0000, 0x0000 }, /* R135 */
233 { 0x0000, 0x0000, 0x0000 }, /* R136 */
234 { 0x0000, 0x0000, 0x0000 }, /* R137 */
235 { 0x0000, 0x0000, 0x0000 }, /* R138 */
236 { 0x0000, 0x0000, 0x0000 }, /* R139 */
237 { 0x0000, 0x0000, 0x0000 }, /* R140 */
238 { 0x0000, 0x0000, 0x0000 }, /* R141 */
239 { 0x0000, 0x0000, 0x0000 }, /* R142 */
240 { 0x0000, 0x0000, 0x0000 }, /* R143 */
241 { 0x0000, 0x0000, 0x0000 }, /* R144 */
242 { 0x0000, 0x0000, 0x0000 }, /* R145 */
243 { 0x0000, 0x0000, 0x0000 }, /* R146 */
244 { 0x0000, 0x0000, 0x0000 }, /* R147 */
245 { 0x0000, 0x0000, 0x0000 }, /* R148 */
246 { 0x0000, 0x0000, 0x0000 }, /* R149 */
247 { 0x0000, 0x0000, 0x0000 }, /* R150 */
248 { 0x0000, 0x0000, 0x0000 }, /* R151 */
249 { 0x0000, 0x0000, 0x0000 }, /* R152 */
250 { 0x0000, 0x0000, 0x0000 }, /* R153 */
251 { 0x0000, 0x0000, 0x0000 }, /* R154 */
252 { 0x0000, 0x0000, 0x0000 }, /* R155 */
253 { 0x0000, 0x0000, 0x0000 }, /* R156 */
254 { 0x0000, 0x0000, 0x0000 }, /* R157 */
255 { 0x0000, 0x0000, 0x0000 }, /* R158 */
256 { 0x0000, 0x0000, 0x0000 }, /* R159 */
257 { 0x0000, 0x0000, 0x0000 }, /* R160 */
258 { 0x0000, 0x0000, 0x0000 }, /* R161 */
259 { 0x0000, 0x0000, 0x0000 }, /* R162 */
260 { 0x0000, 0x0000, 0x0000 }, /* R163 */
261 { 0x0000, 0x0000, 0x0000 }, /* R164 */
262 { 0x0000, 0x0000, 0x0000 }, /* R165 */
263 { 0x0000, 0x0000, 0x0000 }, /* R166 */
264 { 0x0000, 0x0000, 0x0000 }, /* R167 */
265 { 0x0000, 0x0000, 0x0000 }, /* R168 */
266 { 0x0000, 0x0000, 0x0000 }, /* R169 */
267 { 0x0000, 0x0000, 0x0000 }, /* R170 */
268 { 0x0000, 0x0000, 0x0000 }, /* R171 */
269 { 0x0000, 0x0000, 0x0000 }, /* R172 */
270 { 0x0000, 0x0000, 0x0000 }, /* R173 */
271 { 0x0000, 0x0000, 0x0000 }, /* R174 */
272 { 0x0000, 0x0000, 0x0000 }, /* R175 */
273 { 0x0000, 0x0000, 0x0000 }, /* R176 */
274 { 0x0000, 0x0000, 0x0000 }, /* R177 */
275 { 0x0000, 0x0000, 0x0000 }, /* R178 */
276 { 0x0000, 0x0000, 0x0000 }, /* R179 */
277 { 0x0000, 0x0000, 0x0000 }, /* R180 */
278 { 0x0000, 0x0000, 0x0000 }, /* R181 */
279 { 0x0000, 0x0000, 0x0000 }, /* R182 */
280 { 0x0000, 0x0000, 0x0000 }, /* R183 */
281 { 0x0000, 0x0000, 0x0000 }, /* R184 */
282 { 0x0000, 0x0000, 0x0000 }, /* R185 */
283 { 0x0000, 0x0000, 0x0000 }, /* R186 */
284 { 0x0000, 0x0000, 0x0000 }, /* R187 */
285 { 0x0000, 0x0000, 0x0000 }, /* R188 */
286 { 0x0000, 0x0000, 0x0000 }, /* R189 */
287 { 0x0000, 0x0000, 0x0000 }, /* R190 */
288 { 0x0000, 0x0000, 0x0000 }, /* R191 */
289 { 0x0000, 0x0000, 0x0000 }, /* R192 */
290 { 0x0000, 0x0000, 0x0000 }, /* R193 */
291 { 0x0000, 0x0000, 0x0000 }, /* R194 */
292 { 0x0000, 0x0000, 0x0000 }, /* R195 */
293 { 0x0000, 0x0000, 0x0000 }, /* R196 */
294 { 0x0000, 0x0000, 0x0000 }, /* R197 */
295 { 0x0000, 0x0000, 0x0000 }, /* R198 */
296 { 0x0000, 0x0000, 0x0000 }, /* R199 */
297 { 0x0000, 0x0000, 0x0000 }, /* R200 */
298 { 0x0000, 0x0000, 0x0000 }, /* R201 */
299 { 0x0000, 0x0000, 0x0000 }, /* R202 */
300 { 0x0000, 0x0000, 0x0000 }, /* R203 */
301 { 0x0000, 0x0000, 0x0000 }, /* R204 */
302 { 0x0000, 0x0000, 0x0000 }, /* R205 */
303 { 0x0000, 0x0000, 0x0000 }, /* R206 */
304 { 0x0000, 0x0000, 0x0000 }, /* R207 */
305 { 0x0000, 0x0000, 0x0000 }, /* R208 */
306 { 0x0000, 0x0000, 0x0000 }, /* R209 */
307 { 0x0000, 0x0000, 0x0000 }, /* R210 */
308 { 0x0000, 0x0000, 0x0000 }, /* R211 */
309 { 0x0000, 0x0000, 0x0000 }, /* R212 */
310 { 0x0000, 0x0000, 0x0000 }, /* R213 */
311 { 0x0000, 0x0000, 0x0000 }, /* R214 */
312 { 0x0000, 0x0000, 0x0000 }, /* R215 */
313 { 0x0000, 0x0000, 0x0000 }, /* R216 */
314 { 0x0000, 0x0000, 0x0000 }, /* R217 */
315 { 0x0000, 0x0000, 0x0000 }, /* R218 */
316 { 0x0000, 0x0000, 0x0000 }, /* R219 */
317 { 0x0000, 0x0000, 0x0000 }, /* R220 */
318 { 0x0000, 0x0000, 0x0000 }, /* R221 */
319 { 0x0000, 0x0000, 0x0000 }, /* R222 */
320 { 0x0000, 0x0000, 0x0000 }, /* R223 */
321 { 0x0000, 0x0000, 0x0000 }, /* R224 */
322 { 0x0000, 0x0000, 0x0000 }, /* R225 */
323 { 0x0000, 0x0000, 0x0000 }, /* R226 */
324 { 0x0000, 0x0000, 0x0000 }, /* R227 */
325 { 0x0000, 0x0000, 0x0000 }, /* R228 */
326 { 0x0000, 0x0000, 0x0000 }, /* R229 */
327 { 0x0000, 0x0000, 0x0000 }, /* R230 */
328 { 0x0000, 0x0000, 0x0000 }, /* R231 */
329 { 0x0000, 0x0000, 0x0000 }, /* R232 */
330 { 0x0000, 0x0000, 0x0000 }, /* R233 */
331 { 0x0000, 0x0000, 0x0000 }, /* R234 */
332 { 0x0000, 0x0000, 0x0000 }, /* R235 */
333 { 0x0000, 0x0000, 0x0000 }, /* R236 */
334 { 0x0000, 0x0000, 0x0000 }, /* R237 */
335 { 0x0000, 0x0000, 0x0000 }, /* R238 */
336 { 0x0000, 0x0000, 0x0000 }, /* R239 */
337 { 0x0000, 0x0000, 0x0000 }, /* R240 */
338 { 0x0000, 0x0000, 0x0000 }, /* R241 */
339 { 0x0000, 0x0000, 0x0000 }, /* R242 */
340 { 0x0000, 0x0000, 0x0000 }, /* R243 */
341 { 0x0000, 0x0000, 0x0000 }, /* R244 */
342 { 0x0000, 0x0000, 0x0000 }, /* R245 */
343 { 0x0000, 0x0000, 0x0000 }, /* R246 */
344 { 0x0000, 0x0000, 0x0000 }, /* R247 */
345 { 0x0000, 0x0000, 0x0000 }, /* R248 */
346 { 0x0000, 0x0000, 0x0000 }, /* R249 */
347 { 0x0000, 0x0000, 0x0000 }, /* R250 */
348 { 0x0000, 0x0000, 0x0000 }, /* R251 */
349 { 0x0000, 0x0000, 0x0000 }, /* R252 */
350 { 0x0000, 0x0000, 0x0000 }, /* R253 */
351 { 0x0000, 0x0000, 0x0000 }, /* R254 */
352 { 0x0000, 0x0000, 0x0000 }, /* R255 */
353 { 0x000F, 0x0000, 0x0000 }, /* R256 - Chip Revision */
354 { 0x0074, 0x0074, 0x0000 }, /* R257 - Control Interface */
355 { 0x0000, 0x0000, 0x0000 }, /* R258 */
356 { 0x0000, 0x0000, 0x0000 }, /* R259 */
357 { 0x0000, 0x0000, 0x0000 }, /* R260 */
358 { 0x0000, 0x0000, 0x0000 }, /* R261 */
359 { 0x0000, 0x0000, 0x0000 }, /* R262 */
360 { 0x0000, 0x0000, 0x0000 }, /* R263 */
361 { 0x0000, 0x0000, 0x0000 }, /* R264 */
362 { 0x0000, 0x0000, 0x0000 }, /* R265 */
363 { 0x0000, 0x0000, 0x0000 }, /* R266 */
364 { 0x0000, 0x0000, 0x0000 }, /* R267 */
365 { 0x0000, 0x0000, 0x0000 }, /* R268 */
366 { 0x0000, 0x0000, 0x0000 }, /* R269 */
367 { 0x0000, 0x0000, 0x0000 }, /* R270 */
368 { 0x0000, 0x0000, 0x0000 }, /* R271 */
369 { 0x807F, 0x837F, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
370 { 0x017F, 0x0000, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
371 { 0x0000, 0x0000, 0x0000 }, /* R274 */
372 { 0x0000, 0x0000, 0x0000 }, /* R275 */
373 { 0x0000, 0x0000, 0x0000 }, /* R276 */
374 { 0x0000, 0x0000, 0x0000 }, /* R277 */
375 { 0x0000, 0x0000, 0x0000 }, /* R278 */
376 { 0x0000, 0x0000, 0x0000 }, /* R279 */
377 { 0x0000, 0x0000, 0x0000 }, /* R280 */
378 { 0x0000, 0x0000, 0x0000 }, /* R281 */
379 { 0x0000, 0x0000, 0x0000 }, /* R282 */
380 { 0x0000, 0x0000, 0x0000 }, /* R283 */
381 { 0x0000, 0x0000, 0x0000 }, /* R284 */
382 { 0x0000, 0x0000, 0x0000 }, /* R285 */
383 { 0x0000, 0x0000, 0x0000 }, /* R286 */
384 { 0x0000, 0x0000, 0x0000 }, /* R287 */
385 { 0x0000, 0x0000, 0x0000 }, /* R288 */
386 { 0x0000, 0x0000, 0x0000 }, /* R289 */
387 { 0x0000, 0x0000, 0x0000 }, /* R290 */
388 { 0x0000, 0x0000, 0x0000 }, /* R291 */
389 { 0x0000, 0x0000, 0x0000 }, /* R292 */
390 { 0x0000, 0x0000, 0x0000 }, /* R293 */
391 { 0x0000, 0x0000, 0x0000 }, /* R294 */
392 { 0x0000, 0x0000, 0x0000 }, /* R295 */
393 { 0x0000, 0x0000, 0x0000 }, /* R296 */
394 { 0x0000, 0x0000, 0x0000 }, /* R297 */
395 { 0x0000, 0x0000, 0x0000 }, /* R298 */
396 { 0x0000, 0x0000, 0x0000 }, /* R299 */
397 { 0x0000, 0x0000, 0x0000 }, /* R300 */
398 { 0x0000, 0x0000, 0x0000 }, /* R301 */
399 { 0x0000, 0x0000, 0x0000 }, /* R302 */
400 { 0x0000, 0x0000, 0x0000 }, /* R303 */
401 { 0x0000, 0x0000, 0x0000 }, /* R304 */
402 { 0x0000, 0x0000, 0x0000 }, /* R305 */
403 { 0x0000, 0x0000, 0x0000 }, /* R306 */
404 { 0x0000, 0x0000, 0x0000 }, /* R307 */
405 { 0x0000, 0x0000, 0x0000 }, /* R308 */
406 { 0x0000, 0x0000, 0x0000 }, /* R309 */
407 { 0x0000, 0x0000, 0x0000 }, /* R310 */
408 { 0x0000, 0x0000, 0x0000 }, /* R311 */
409 { 0x0000, 0x0000, 0x0000 }, /* R312 */
410 { 0x0000, 0x0000, 0x0000 }, /* R313 */
411 { 0x0000, 0x0000, 0x0000 }, /* R314 */
412 { 0x0000, 0x0000, 0x0000 }, /* R315 */
413 { 0x0000, 0x0000, 0x0000 }, /* R316 */
414 { 0x0000, 0x0000, 0x0000 }, /* R317 */
415 { 0x0000, 0x0000, 0x0000 }, /* R318 */
416 { 0x0000, 0x0000, 0x0000 }, /* R319 */
417 { 0x0000, 0x0000, 0x0000 }, /* R320 */
418 { 0x0000, 0x0000, 0x0000 }, /* R321 */
419 { 0x0000, 0x0000, 0x0000 }, /* R322 */
420 { 0x0000, 0x0000, 0x0000 }, /* R323 */
421 { 0x0000, 0x0000, 0x0000 }, /* R324 */
422 { 0x0000, 0x0000, 0x0000 }, /* R325 */
423 { 0x0000, 0x0000, 0x0000 }, /* R326 */
424 { 0x0000, 0x0000, 0x0000 }, /* R327 */
425 { 0x0000, 0x0000, 0x0000 }, /* R328 */
426 { 0x0000, 0x0000, 0x0000 }, /* R329 */
427 { 0x0000, 0x0000, 0x0000 }, /* R330 */
428 { 0x0000, 0x0000, 0x0000 }, /* R331 */
429 { 0x0000, 0x0000, 0x0000 }, /* R332 */
430 { 0x0000, 0x0000, 0x0000 }, /* R333 */
431 { 0x0000, 0x0000, 0x0000 }, /* R334 */
432 { 0x0000, 0x0000, 0x0000 }, /* R335 */
433 { 0x0000, 0x0000, 0x0000 }, /* R336 */
434 { 0x0000, 0x0000, 0x0000 }, /* R337 */
435 { 0x0000, 0x0000, 0x0000 }, /* R338 */
436 { 0x0000, 0x0000, 0x0000 }, /* R339 */
437 { 0x0000, 0x0000, 0x0000 }, /* R340 */
438 { 0x0000, 0x0000, 0x0000 }, /* R341 */
439 { 0x0000, 0x0000, 0x0000 }, /* R342 */
440 { 0x0000, 0x0000, 0x0000 }, /* R343 */
441 { 0x0000, 0x0000, 0x0000 }, /* R344 */
442 { 0x0000, 0x0000, 0x0000 }, /* R345 */
443 { 0x0000, 0x0000, 0x0000 }, /* R346 */
444 { 0x0000, 0x0000, 0x0000 }, /* R347 */
445 { 0x0000, 0x0000, 0x0000 }, /* R348 */
446 { 0x0000, 0x0000, 0x0000 }, /* R349 */
447 { 0x0000, 0x0000, 0x0000 }, /* R350 */
448 { 0x0000, 0x0000, 0x0000 }, /* R351 */
449 { 0x0000, 0x0000, 0x0000 }, /* R352 */
450 { 0x0000, 0x0000, 0x0000 }, /* R353 */
451 { 0x0000, 0x0000, 0x0000 }, /* R354 */
452 { 0x0000, 0x0000, 0x0000 }, /* R355 */
453 { 0x0000, 0x0000, 0x0000 }, /* R356 */
454 { 0x0000, 0x0000, 0x0000 }, /* R357 */
455 { 0x0000, 0x0000, 0x0000 }, /* R358 */
456 { 0x0000, 0x0000, 0x0000 }, /* R359 */
457 { 0x0000, 0x0000, 0x0000 }, /* R360 */
458 { 0x0000, 0x0000, 0x0000 }, /* R361 */
459 { 0x0000, 0x0000, 0x0000 }, /* R362 */
460 { 0x0000, 0x0000, 0x0000 }, /* R363 */
461 { 0x0000, 0x0000, 0x0000 }, /* R364 */
462 { 0x0000, 0x0000, 0x0000 }, /* R365 */
463 { 0x0000, 0x0000, 0x0000 }, /* R366 */
464 { 0x0000, 0x0000, 0x0000 }, /* R367 */
465 { 0x0000, 0x0000, 0x0000 }, /* R368 */
466 { 0x0000, 0x0000, 0x0000 }, /* R369 */
467 { 0x0000, 0x0000, 0x0000 }, /* R370 */
468 { 0x0000, 0x0000, 0x0000 }, /* R371 */
469 { 0x0000, 0x0000, 0x0000 }, /* R372 */
470 { 0x0000, 0x0000, 0x0000 }, /* R373 */
471 { 0x0000, 0x0000, 0x0000 }, /* R374 */
472 { 0x0000, 0x0000, 0x0000 }, /* R375 */
473 { 0x0000, 0x0000, 0x0000 }, /* R376 */
474 { 0x0000, 0x0000, 0x0000 }, /* R377 */
475 { 0x0000, 0x0000, 0x0000 }, /* R378 */
476 { 0x0000, 0x0000, 0x0000 }, /* R379 */
477 { 0x0000, 0x0000, 0x0000 }, /* R380 */
478 { 0x0000, 0x0000, 0x0000 }, /* R381 */
479 { 0x0000, 0x0000, 0x0000 }, /* R382 */
480 { 0x0000, 0x0000, 0x0000 }, /* R383 */
481 { 0x0000, 0x0000, 0x0000 }, /* R384 */
482 { 0x0000, 0x0000, 0x0000 }, /* R385 */
483 { 0x0000, 0x0000, 0x0000 }, /* R386 */
484 { 0x0000, 0x0000, 0x0000 }, /* R387 */
485 { 0x0000, 0x0000, 0x0000 }, /* R388 */
486 { 0x0000, 0x0000, 0x0000 }, /* R389 */
487 { 0x0000, 0x0000, 0x0000 }, /* R390 */
488 { 0x0000, 0x0000, 0x0000 }, /* R391 */
489 { 0x0000, 0x0000, 0x0000 }, /* R392 */
490 { 0x0000, 0x0000, 0x0000 }, /* R393 */
491 { 0x0000, 0x0000, 0x0000 }, /* R394 */
492 { 0x0000, 0x0000, 0x0000 }, /* R395 */
493 { 0x0000, 0x0000, 0x0000 }, /* R396 */
494 { 0x0000, 0x0000, 0x0000 }, /* R397 */
495 { 0x0000, 0x0000, 0x0000 }, /* R398 */
496 { 0x0000, 0x0000, 0x0000 }, /* R399 */
497 { 0x0000, 0x0000, 0x0000 }, /* R400 */
498 { 0x0000, 0x0000, 0x0000 }, /* R401 */
499 { 0x0000, 0x0000, 0x0000 }, /* R402 */
500 { 0x0000, 0x0000, 0x0000 }, /* R403 */
501 { 0x0000, 0x0000, 0x0000 }, /* R404 */
502 { 0x0000, 0x0000, 0x0000 }, /* R405 */
503 { 0x0000, 0x0000, 0x0000 }, /* R406 */
504 { 0x0000, 0x0000, 0x0000 }, /* R407 */
505 { 0x0000, 0x0000, 0x0000 }, /* R408 */
506 { 0x0000, 0x0000, 0x0000 }, /* R409 */
507 { 0x0000, 0x0000, 0x0000 }, /* R410 */
508 { 0x0000, 0x0000, 0x0000 }, /* R411 */
509 { 0x0000, 0x0000, 0x0000 }, /* R412 */
510 { 0x0000, 0x0000, 0x0000 }, /* R413 */
511 { 0x0000, 0x0000, 0x0000 }, /* R414 */
512 { 0x0000, 0x0000, 0x0000 }, /* R415 */
513 { 0x0000, 0x0000, 0x0000 }, /* R416 */
514 { 0x0000, 0x0000, 0x0000 }, /* R417 */
515 { 0x0000, 0x0000, 0x0000 }, /* R418 */
516 { 0x0000, 0x0000, 0x0000 }, /* R419 */
517 { 0x0000, 0x0000, 0x0000 }, /* R420 */
518 { 0x0000, 0x0000, 0x0000 }, /* R421 */
519 { 0x0000, 0x0000, 0x0000 }, /* R422 */
520 { 0x0000, 0x0000, 0x0000 }, /* R423 */
521 { 0x0000, 0x0000, 0x0000 }, /* R424 */
522 { 0x0000, 0x0000, 0x0000 }, /* R425 */
523 { 0x0000, 0x0000, 0x0000 }, /* R426 */
524 { 0x0000, 0x0000, 0x0000 }, /* R427 */
525 { 0x0000, 0x0000, 0x0000 }, /* R428 */
526 { 0x0000, 0x0000, 0x0000 }, /* R429 */
527 { 0x0000, 0x0000, 0x0000 }, /* R430 */
528 { 0x0000, 0x0000, 0x0000 }, /* R431 */
529 { 0x0000, 0x0000, 0x0000 }, /* R432 */
530 { 0x0000, 0x0000, 0x0000 }, /* R433 */
531 { 0x0000, 0x0000, 0x0000 }, /* R434 */
532 { 0x0000, 0x0000, 0x0000 }, /* R435 */
533 { 0x0000, 0x0000, 0x0000 }, /* R436 */
534 { 0x0000, 0x0000, 0x0000 }, /* R437 */
535 { 0x0000, 0x0000, 0x0000 }, /* R438 */
536 { 0x0000, 0x0000, 0x0000 }, /* R439 */
537 { 0x0000, 0x0000, 0x0000 }, /* R440 */
538 { 0x0000, 0x0000, 0x0000 }, /* R441 */
539 { 0x0000, 0x0000, 0x0000 }, /* R442 */
540 { 0x0000, 0x0000, 0x0000 }, /* R443 */
541 { 0x0000, 0x0000, 0x0000 }, /* R444 */
542 { 0x0000, 0x0000, 0x0000 }, /* R445 */
543 { 0x0000, 0x0000, 0x0000 }, /* R446 */
544 { 0x0000, 0x0000, 0x0000 }, /* R447 */
545 { 0x0000, 0x0000, 0x0000 }, /* R448 */
546 { 0x0000, 0x0000, 0x0000 }, /* R449 */
547 { 0x0000, 0x0000, 0x0000 }, /* R450 */
548 { 0x0000, 0x0000, 0x0000 }, /* R451 */
549 { 0x0000, 0x0000, 0x0000 }, /* R452 */
550 { 0x0000, 0x0000, 0x0000 }, /* R453 */
551 { 0x0000, 0x0000, 0x0000 }, /* R454 */
552 { 0x0000, 0x0000, 0x0000 }, /* R455 */
553 { 0x0000, 0x0000, 0x0000 }, /* R456 */
554 { 0x0000, 0x0000, 0x0000 }, /* R457 */
555 { 0x0000, 0x0000, 0x0000 }, /* R458 */
556 { 0x0000, 0x0000, 0x0000 }, /* R459 */
557 { 0x0000, 0x0000, 0x0000 }, /* R460 */
558 { 0x0000, 0x0000, 0x0000 }, /* R461 */
559 { 0x0000, 0x0000, 0x0000 }, /* R462 */
560 { 0x0000, 0x0000, 0x0000 }, /* R463 */
561 { 0x0000, 0x0000, 0x0000 }, /* R464 */
562 { 0x0000, 0x0000, 0x0000 }, /* R465 */
563 { 0x0000, 0x0000, 0x0000 }, /* R466 */
564 { 0x0000, 0x0000, 0x0000 }, /* R467 */
565 { 0x0000, 0x0000, 0x0000 }, /* R468 */
566 { 0x0000, 0x0000, 0x0000 }, /* R469 */
567 { 0x0000, 0x0000, 0x0000 }, /* R470 */
568 { 0x0000, 0x0000, 0x0000 }, /* R471 */
569 { 0x0000, 0x0000, 0x0000 }, /* R472 */
570 { 0x0000, 0x0000, 0x0000 }, /* R473 */
571 { 0x0000, 0x0000, 0x0000 }, /* R474 */
572 { 0x0000, 0x0000, 0x0000 }, /* R475 */
573 { 0x0000, 0x0000, 0x0000 }, /* R476 */
574 { 0x0000, 0x0000, 0x0000 }, /* R477 */
575 { 0x0000, 0x0000, 0x0000 }, /* R478 */
576 { 0x0000, 0x0000, 0x0000 }, /* R479 */
577 { 0x0000, 0x0000, 0x0000 }, /* R480 */
578 { 0x0000, 0x0000, 0x0000 }, /* R481 */
579 { 0x0000, 0x0000, 0x0000 }, /* R482 */
580 { 0x0000, 0x0000, 0x0000 }, /* R483 */
581 { 0x0000, 0x0000, 0x0000 }, /* R484 */
582 { 0x0000, 0x0000, 0x0000 }, /* R485 */
583 { 0x0000, 0x0000, 0x0000 }, /* R486 */
584 { 0x0000, 0x0000, 0x0000 }, /* R487 */
585 { 0x0000, 0x0000, 0x0000 }, /* R488 */
586 { 0x0000, 0x0000, 0x0000 }, /* R489 */
587 { 0x0000, 0x0000, 0x0000 }, /* R490 */
588 { 0x0000, 0x0000, 0x0000 }, /* R491 */
589 { 0x0000, 0x0000, 0x0000 }, /* R492 */
590 { 0x0000, 0x0000, 0x0000 }, /* R493 */
591 { 0x0000, 0x0000, 0x0000 }, /* R494 */
592 { 0x0000, 0x0000, 0x0000 }, /* R495 */
593 { 0x0000, 0x0000, 0x0000 }, /* R496 */
594 { 0x0000, 0x0000, 0x0000 }, /* R497 */
595 { 0x0000, 0x0000, 0x0000 }, /* R498 */
596 { 0x0000, 0x0000, 0x0000 }, /* R499 */
597 { 0x0000, 0x0000, 0x0000 }, /* R500 */
598 { 0x0000, 0x0000, 0x0000 }, /* R501 */
599 { 0x0000, 0x0000, 0x0000 }, /* R502 */
600 { 0x0000, 0x0000, 0x0000 }, /* R503 */
601 { 0x0000, 0x0000, 0x0000 }, /* R504 */
602 { 0x0000, 0x0000, 0x0000 }, /* R505 */
603 { 0x0000, 0x0000, 0x0000 }, /* R506 */
604 { 0x0000, 0x0000, 0x0000 }, /* R507 */
605 { 0x0000, 0x0000, 0x0000 }, /* R508 */
606 { 0x0000, 0x0000, 0x0000 }, /* R509 */
607 { 0x0000, 0x0000, 0x0000 }, /* R510 */
608 { 0x0000, 0x0000, 0x0000 }, /* R511 */
609 { 0x001F, 0x001F, 0x0000 }, /* R512 - AIF1 Clocking (1) */
610 { 0x003F, 0x003F, 0x0000 }, /* R513 - AIF1 Clocking (2) */
611 { 0x0000, 0x0000, 0x0000 }, /* R514 */
612 { 0x0000, 0x0000, 0x0000 }, /* R515 */
613 { 0x001F, 0x001F, 0x0000 }, /* R516 - AIF2 Clocking (1) */
614 { 0x003F, 0x003F, 0x0000 }, /* R517 - AIF2 Clocking (2) */
615 { 0x0000, 0x0000, 0x0000 }, /* R518 */
616 { 0x0000, 0x0000, 0x0000 }, /* R519 */
617 { 0x001F, 0x001F, 0x0000 }, /* R520 - Clocking (1) */
618 { 0x0777, 0x0777, 0x0000 }, /* R521 - Clocking (2) */
619 { 0x0000, 0x0000, 0x0000 }, /* R522 */
620 { 0x0000, 0x0000, 0x0000 }, /* R523 */
621 { 0x0000, 0x0000, 0x0000 }, /* R524 */
622 { 0x0000, 0x0000, 0x0000 }, /* R525 */
623 { 0x0000, 0x0000, 0x0000 }, /* R526 */
624 { 0x0000, 0x0000, 0x0000 }, /* R527 */
625 { 0x00FF, 0x00FF, 0x0000 }, /* R528 - AIF1 Rate */
626 { 0x00FF, 0x00FF, 0x0000 }, /* R529 - AIF2 Rate */
627 { 0x000F, 0x0000, 0x0000 }, /* R530 - Rate Status */
628 { 0x0000, 0x0000, 0x0000 }, /* R531 */
629 { 0x0000, 0x0000, 0x0000 }, /* R532 */
630 { 0x0000, 0x0000, 0x0000 }, /* R533 */
631 { 0x0000, 0x0000, 0x0000 }, /* R534 */
632 { 0x0000, 0x0000, 0x0000 }, /* R535 */
633 { 0x0000, 0x0000, 0x0000 }, /* R536 */
634 { 0x0000, 0x0000, 0x0000 }, /* R537 */
635 { 0x0000, 0x0000, 0x0000 }, /* R538 */
636 { 0x0000, 0x0000, 0x0000 }, /* R539 */
637 { 0x0000, 0x0000, 0x0000 }, /* R540 */
638 { 0x0000, 0x0000, 0x0000 }, /* R541 */
639 { 0x0000, 0x0000, 0x0000 }, /* R542 */
640 { 0x0000, 0x0000, 0x0000 }, /* R543 */
641 { 0x0007, 0x0007, 0x0000 }, /* R544 - FLL1 Control (1) */
642 { 0x3F77, 0x3F77, 0x0000 }, /* R545 - FLL1 Control (2) */
643 { 0xFFFF, 0xFFFF, 0x0000 }, /* R546 - FLL1 Control (3) */
644 { 0x7FEF, 0x7FEF, 0x0000 }, /* R547 - FLL1 Control (4) */
645 { 0x1FDB, 0x1FDB, 0x0000 }, /* R548 - FLL1 Control (5) */
646 { 0x0000, 0x0000, 0x0000 }, /* R549 */
647 { 0x0000, 0x0000, 0x0000 }, /* R550 */
648 { 0x0000, 0x0000, 0x0000 }, /* R551 */
649 { 0x0000, 0x0000, 0x0000 }, /* R552 */
650 { 0x0000, 0x0000, 0x0000 }, /* R553 */
651 { 0x0000, 0x0000, 0x0000 }, /* R554 */
652 { 0x0000, 0x0000, 0x0000 }, /* R555 */
653 { 0x0000, 0x0000, 0x0000 }, /* R556 */
654 { 0x0000, 0x0000, 0x0000 }, /* R557 */
655 { 0x0000, 0x0000, 0x0000 }, /* R558 */
656 { 0x0000, 0x0000, 0x0000 }, /* R559 */
657 { 0x0000, 0x0000, 0x0000 }, /* R560 */
658 { 0x0000, 0x0000, 0x0000 }, /* R561 */
659 { 0x0000, 0x0000, 0x0000 }, /* R562 */
660 { 0x0000, 0x0000, 0x0000 }, /* R563 */
661 { 0x0000, 0x0000, 0x0000 }, /* R564 */
662 { 0x0000, 0x0000, 0x0000 }, /* R565 */
663 { 0x0000, 0x0000, 0x0000 }, /* R566 */
664 { 0x0000, 0x0000, 0x0000 }, /* R567 */
665 { 0x0000, 0x0000, 0x0000 }, /* R568 */
666 { 0x0000, 0x0000, 0x0000 }, /* R569 */
667 { 0x0000, 0x0000, 0x0000 }, /* R570 */
668 { 0x0000, 0x0000, 0x0000 }, /* R571 */
669 { 0x0000, 0x0000, 0x0000 }, /* R572 */
670 { 0x0000, 0x0000, 0x0000 }, /* R573 */
671 { 0x0000, 0x0000, 0x0000 }, /* R574 */
672 { 0x0000, 0x0000, 0x0000 }, /* R575 */
673 { 0x0007, 0x0007, 0x0000 }, /* R576 - FLL2 Control (1) */
674 { 0x3F77, 0x3F77, 0x0000 }, /* R577 - FLL2 Control (2) */
675 { 0xFFFF, 0xFFFF, 0x0000 }, /* R578 - FLL2 Control (3) */
676 { 0x7FEF, 0x7FEF, 0x0000 }, /* R579 - FLL2 Control (4) */
677 { 0x1FDB, 0x1FDB, 0x0000 }, /* R580 - FLL2 Control (5) */
678 { 0x0000, 0x0000, 0x0000 }, /* R581 */
679 { 0x0000, 0x0000, 0x0000 }, /* R582 */
680 { 0x0000, 0x0000, 0x0000 }, /* R583 */
681 { 0x0000, 0x0000, 0x0000 }, /* R584 */
682 { 0x0000, 0x0000, 0x0000 }, /* R585 */
683 { 0x0000, 0x0000, 0x0000 }, /* R586 */
684 { 0x0000, 0x0000, 0x0000 }, /* R587 */
685 { 0x0000, 0x0000, 0x0000 }, /* R588 */
686 { 0x0000, 0x0000, 0x0000 }, /* R589 */
687 { 0x0000, 0x0000, 0x0000 }, /* R590 */
688 { 0x0000, 0x0000, 0x0000 }, /* R591 */
689 { 0x0000, 0x0000, 0x0000 }, /* R592 */
690 { 0x0000, 0x0000, 0x0000 }, /* R593 */
691 { 0x0000, 0x0000, 0x0000 }, /* R594 */
692 { 0x0000, 0x0000, 0x0000 }, /* R595 */
693 { 0x0000, 0x0000, 0x0000 }, /* R596 */
694 { 0x0000, 0x0000, 0x0000 }, /* R597 */
695 { 0x0000, 0x0000, 0x0000 }, /* R598 */
696 { 0x0000, 0x0000, 0x0000 }, /* R599 */
697 { 0x0000, 0x0000, 0x0000 }, /* R600 */
698 { 0x0000, 0x0000, 0x0000 }, /* R601 */
699 { 0x0000, 0x0000, 0x0000 }, /* R602 */
700 { 0x0000, 0x0000, 0x0000 }, /* R603 */
701 { 0x0000, 0x0000, 0x0000 }, /* R604 */
702 { 0x0000, 0x0000, 0x0000 }, /* R605 */
703 { 0x0000, 0x0000, 0x0000 }, /* R606 */
704 { 0x0000, 0x0000, 0x0000 }, /* R607 */
705 { 0x0000, 0x0000, 0x0000 }, /* R608 */
706 { 0x0000, 0x0000, 0x0000 }, /* R609 */
707 { 0x0000, 0x0000, 0x0000 }, /* R610 */
708 { 0x0000, 0x0000, 0x0000 }, /* R611 */
709 { 0x0000, 0x0000, 0x0000 }, /* R612 */
710 { 0x0000, 0x0000, 0x0000 }, /* R613 */
711 { 0x0000, 0x0000, 0x0000 }, /* R614 */
712 { 0x0000, 0x0000, 0x0000 }, /* R615 */
713 { 0x0000, 0x0000, 0x0000 }, /* R616 */
714 { 0x0000, 0x0000, 0x0000 }, /* R617 */
715 { 0x0000, 0x0000, 0x0000 }, /* R618 */
716 { 0x0000, 0x0000, 0x0000 }, /* R619 */
717 { 0x0000, 0x0000, 0x0000 }, /* R620 */
718 { 0x0000, 0x0000, 0x0000 }, /* R621 */
719 { 0x0000, 0x0000, 0x0000 }, /* R622 */
720 { 0x0000, 0x0000, 0x0000 }, /* R623 */
721 { 0x0000, 0x0000, 0x0000 }, /* R624 */
722 { 0x0000, 0x0000, 0x0000 }, /* R625 */
723 { 0x0000, 0x0000, 0x0000 }, /* R626 */
724 { 0x0000, 0x0000, 0x0000 }, /* R627 */
725 { 0x0000, 0x0000, 0x0000 }, /* R628 */
726 { 0x0000, 0x0000, 0x0000 }, /* R629 */
727 { 0x0000, 0x0000, 0x0000 }, /* R630 */
728 { 0x0000, 0x0000, 0x0000 }, /* R631 */
729 { 0x0000, 0x0000, 0x0000 }, /* R632 */
730 { 0x0000, 0x0000, 0x0000 }, /* R633 */
731 { 0x0000, 0x0000, 0x0000 }, /* R634 */
732 { 0x0000, 0x0000, 0x0000 }, /* R635 */
733 { 0x0000, 0x0000, 0x0000 }, /* R636 */
734 { 0x0000, 0x0000, 0x0000 }, /* R637 */
735 { 0x0000, 0x0000, 0x0000 }, /* R638 */
736 { 0x0000, 0x0000, 0x0000 }, /* R639 */
737 { 0x0000, 0x0000, 0x0000 }, /* R640 */
738 { 0x0000, 0x0000, 0x0000 }, /* R641 */
739 { 0x0000, 0x0000, 0x0000 }, /* R642 */
740 { 0x0000, 0x0000, 0x0000 }, /* R643 */
741 { 0x0000, 0x0000, 0x0000 }, /* R644 */
742 { 0x0000, 0x0000, 0x0000 }, /* R645 */
743 { 0x0000, 0x0000, 0x0000 }, /* R646 */
744 { 0x0000, 0x0000, 0x0000 }, /* R647 */
745 { 0x0000, 0x0000, 0x0000 }, /* R648 */
746 { 0x0000, 0x0000, 0x0000 }, /* R649 */
747 { 0x0000, 0x0000, 0x0000 }, /* R650 */
748 { 0x0000, 0x0000, 0x0000 }, /* R651 */
749 { 0x0000, 0x0000, 0x0000 }, /* R652 */
750 { 0x0000, 0x0000, 0x0000 }, /* R653 */
751 { 0x0000, 0x0000, 0x0000 }, /* R654 */
752 { 0x0000, 0x0000, 0x0000 }, /* R655 */
753 { 0x0000, 0x0000, 0x0000 }, /* R656 */
754 { 0x0000, 0x0000, 0x0000 }, /* R657 */
755 { 0x0000, 0x0000, 0x0000 }, /* R658 */
756 { 0x0000, 0x0000, 0x0000 }, /* R659 */
757 { 0x0000, 0x0000, 0x0000 }, /* R660 */
758 { 0x0000, 0x0000, 0x0000 }, /* R661 */
759 { 0x0000, 0x0000, 0x0000 }, /* R662 */
760 { 0x0000, 0x0000, 0x0000 }, /* R663 */
761 { 0x0000, 0x0000, 0x0000 }, /* R664 */
762 { 0x0000, 0x0000, 0x0000 }, /* R665 */
763 { 0x0000, 0x0000, 0x0000 }, /* R666 */
764 { 0x0000, 0x0000, 0x0000 }, /* R667 */
765 { 0x0000, 0x0000, 0x0000 }, /* R668 */
766 { 0x0000, 0x0000, 0x0000 }, /* R669 */
767 { 0x0000, 0x0000, 0x0000 }, /* R670 */
768 { 0x0000, 0x0000, 0x0000 }, /* R671 */
769 { 0x0000, 0x0000, 0x0000 }, /* R672 */
770 { 0x0000, 0x0000, 0x0000 }, /* R673 */
771 { 0x0000, 0x0000, 0x0000 }, /* R674 */
772 { 0x0000, 0x0000, 0x0000 }, /* R675 */
773 { 0x0000, 0x0000, 0x0000 }, /* R676 */
774 { 0x0000, 0x0000, 0x0000 }, /* R677 */
775 { 0x0000, 0x0000, 0x0000 }, /* R678 */
776 { 0x0000, 0x0000, 0x0000 }, /* R679 */
777 { 0x0000, 0x0000, 0x0000 }, /* R680 */
778 { 0x0000, 0x0000, 0x0000 }, /* R681 */
779 { 0x0000, 0x0000, 0x0000 }, /* R682 */
780 { 0x0000, 0x0000, 0x0000 }, /* R683 */
781 { 0x0000, 0x0000, 0x0000 }, /* R684 */
782 { 0x0000, 0x0000, 0x0000 }, /* R685 */
783 { 0x0000, 0x0000, 0x0000 }, /* R686 */
784 { 0x0000, 0x0000, 0x0000 }, /* R687 */
785 { 0x0000, 0x0000, 0x0000 }, /* R688 */
786 { 0x0000, 0x0000, 0x0000 }, /* R689 */
787 { 0x0000, 0x0000, 0x0000 }, /* R690 */
788 { 0x0000, 0x0000, 0x0000 }, /* R691 */
789 { 0x0000, 0x0000, 0x0000 }, /* R692 */
790 { 0x0000, 0x0000, 0x0000 }, /* R693 */
791 { 0x0000, 0x0000, 0x0000 }, /* R694 */
792 { 0x0000, 0x0000, 0x0000 }, /* R695 */
793 { 0x0000, 0x0000, 0x0000 }, /* R696 */
794 { 0x0000, 0x0000, 0x0000 }, /* R697 */
795 { 0x0000, 0x0000, 0x0000 }, /* R698 */
796 { 0x0000, 0x0000, 0x0000 }, /* R699 */
797 { 0x0000, 0x0000, 0x0000 }, /* R700 */
798 { 0x0000, 0x0000, 0x0000 }, /* R701 */
799 { 0x0000, 0x0000, 0x0000 }, /* R702 */
800 { 0x0000, 0x0000, 0x0000 }, /* R703 */
801 { 0x0000, 0x0000, 0x0000 }, /* R704 */
802 { 0x0000, 0x0000, 0x0000 }, /* R705 */
803 { 0x0000, 0x0000, 0x0000 }, /* R706 */
804 { 0x0000, 0x0000, 0x0000 }, /* R707 */
805 { 0x0000, 0x0000, 0x0000 }, /* R708 */
806 { 0x0000, 0x0000, 0x0000 }, /* R709 */
807 { 0x0000, 0x0000, 0x0000 }, /* R710 */
808 { 0x0000, 0x0000, 0x0000 }, /* R711 */
809 { 0x0000, 0x0000, 0x0000 }, /* R712 */
810 { 0x0000, 0x0000, 0x0000 }, /* R713 */
811 { 0x0000, 0x0000, 0x0000 }, /* R714 */
812 { 0x0000, 0x0000, 0x0000 }, /* R715 */
813 { 0x0000, 0x0000, 0x0000 }, /* R716 */
814 { 0x0000, 0x0000, 0x0000 }, /* R717 */
815 { 0x0000, 0x0000, 0x0000 }, /* R718 */
816 { 0x0000, 0x0000, 0x0000 }, /* R719 */
817 { 0x0000, 0x0000, 0x0000 }, /* R720 */
818 { 0x0000, 0x0000, 0x0000 }, /* R721 */
819 { 0x0000, 0x0000, 0x0000 }, /* R722 */
820 { 0x0000, 0x0000, 0x0000 }, /* R723 */
821 { 0x0000, 0x0000, 0x0000 }, /* R724 */
822 { 0x0000, 0x0000, 0x0000 }, /* R725 */
823 { 0x0000, 0x0000, 0x0000 }, /* R726 */
824 { 0x0000, 0x0000, 0x0000 }, /* R727 */
825 { 0x0000, 0x0000, 0x0000 }, /* R728 */
826 { 0x0000, 0x0000, 0x0000 }, /* R729 */
827 { 0x0000, 0x0000, 0x0000 }, /* R730 */
828 { 0x0000, 0x0000, 0x0000 }, /* R731 */
829 { 0x0000, 0x0000, 0x0000 }, /* R732 */
830 { 0x0000, 0x0000, 0x0000 }, /* R733 */
831 { 0x0000, 0x0000, 0x0000 }, /* R734 */
832 { 0x0000, 0x0000, 0x0000 }, /* R735 */
833 { 0x0000, 0x0000, 0x0000 }, /* R736 */
834 { 0x0000, 0x0000, 0x0000 }, /* R737 */
835 { 0x0000, 0x0000, 0x0000 }, /* R738 */
836 { 0x0000, 0x0000, 0x0000 }, /* R739 */
837 { 0x0000, 0x0000, 0x0000 }, /* R740 */
838 { 0x0000, 0x0000, 0x0000 }, /* R741 */
839 { 0x0000, 0x0000, 0x0000 }, /* R742 */
840 { 0x0000, 0x0000, 0x0000 }, /* R743 */
841 { 0x0000, 0x0000, 0x0000 }, /* R744 */
842 { 0x0000, 0x0000, 0x0000 }, /* R745 */
843 { 0x0000, 0x0000, 0x0000 }, /* R746 */
844 { 0x0000, 0x0000, 0x0000 }, /* R747 */
845 { 0x0000, 0x0000, 0x0000 }, /* R748 */
846 { 0x0000, 0x0000, 0x0000 }, /* R749 */
847 { 0x0000, 0x0000, 0x0000 }, /* R750 */
848 { 0x0000, 0x0000, 0x0000 }, /* R751 */
849 { 0x0000, 0x0000, 0x0000 }, /* R752 */
850 { 0x0000, 0x0000, 0x0000 }, /* R753 */
851 { 0x0000, 0x0000, 0x0000 }, /* R754 */
852 { 0x0000, 0x0000, 0x0000 }, /* R755 */
853 { 0x0000, 0x0000, 0x0000 }, /* R756 */
854 { 0x0000, 0x0000, 0x0000 }, /* R757 */
855 { 0x0000, 0x0000, 0x0000 }, /* R758 */
856 { 0x0000, 0x0000, 0x0000 }, /* R759 */
857 { 0x0000, 0x0000, 0x0000 }, /* R760 */
858 { 0x0000, 0x0000, 0x0000 }, /* R761 */
859 { 0x0000, 0x0000, 0x0000 }, /* R762 */
860 { 0x0000, 0x0000, 0x0000 }, /* R763 */
861 { 0x0000, 0x0000, 0x0000 }, /* R764 */
862 { 0x0000, 0x0000, 0x0000 }, /* R765 */
863 { 0x0000, 0x0000, 0x0000 }, /* R766 */
864 { 0x0000, 0x0000, 0x0000 }, /* R767 */
865 { 0xE1F8, 0xE1F8, 0x0000 }, /* R768 - AIF1 Control (1) */
866 { 0xCD1F, 0xCD1F, 0x0000 }, /* R769 - AIF1 Control (2) */
867 { 0xF000, 0xF000, 0x0000 }, /* R770 - AIF1 Master/Slave */
868 { 0x01F0, 0x01F0, 0x0000 }, /* R771 - AIF1 BCLK */
869 { 0x0FFF, 0x0FFF, 0x0000 }, /* R772 - AIF1ADC LRCLK */
870 { 0x0FFF, 0x0FFF, 0x0000 }, /* R773 - AIF1DAC LRCLK */
871 { 0x0003, 0x0003, 0x0000 }, /* R774 - AIF1DAC Data */
872 { 0x0003, 0x0003, 0x0000 }, /* R775 - AIF1ADC Data */
873 { 0x0000, 0x0000, 0x0000 }, /* R776 */
874 { 0x0000, 0x0000, 0x0000 }, /* R777 */
875 { 0x0000, 0x0000, 0x0000 }, /* R778 */
876 { 0x0000, 0x0000, 0x0000 }, /* R779 */
877 { 0x0000, 0x0000, 0x0000 }, /* R780 */
878 { 0x0000, 0x0000, 0x0000 }, /* R781 */
879 { 0x0000, 0x0000, 0x0000 }, /* R782 */
880 { 0x0000, 0x0000, 0x0000 }, /* R783 */
881 { 0xF1F8, 0xF1F8, 0x0000 }, /* R784 - AIF2 Control (1) */
882 { 0xFD1F, 0xFD1F, 0x0000 }, /* R785 - AIF2 Control (2) */
883 { 0xF000, 0xF000, 0x0000 }, /* R786 - AIF2 Master/Slave */
884 { 0x01F0, 0x01F0, 0x0000 }, /* R787 - AIF2 BCLK */
885 { 0x0FFF, 0x0FFF, 0x0000 }, /* R788 - AIF2ADC LRCLK */
886 { 0x0FFF, 0x0FFF, 0x0000 }, /* R789 - AIF2DAC LRCLK */
887 { 0x0003, 0x0003, 0x0000 }, /* R790 - AIF2DAC Data */
888 { 0x0003, 0x0003, 0x0000 }, /* R791 - AIF2ADC Data */
889 { 0x0000, 0x0000, 0x0000 }, /* R792 */
890 { 0x0000, 0x0000, 0x0000 }, /* R793 */
891 { 0x0000, 0x0000, 0x0000 }, /* R794 */
892 { 0x0000, 0x0000, 0x0000 }, /* R795 */
893 { 0x0000, 0x0000, 0x0000 }, /* R796 */
894 { 0x0000, 0x0000, 0x0000 }, /* R797 */
895 { 0x0000, 0x0000, 0x0000 }, /* R798 */
896 { 0x0000, 0x0000, 0x0000 }, /* R799 */
897 { 0x0000, 0x0000, 0x0000 }, /* R800 */
898 { 0x0000, 0x0000, 0x0000 }, /* R801 */
899 { 0x0000, 0x0000, 0x0000 }, /* R802 */
900 { 0x0000, 0x0000, 0x0000 }, /* R803 */
901 { 0x0000, 0x0000, 0x0000 }, /* R804 */
902 { 0x0000, 0x0000, 0x0000 }, /* R805 */
903 { 0x0000, 0x0000, 0x0000 }, /* R806 */
904 { 0x0000, 0x0000, 0x0000 }, /* R807 */
905 { 0x0000, 0x0000, 0x0000 }, /* R808 */
906 { 0x0000, 0x0000, 0x0000 }, /* R809 */
907 { 0x0000, 0x0000, 0x0000 }, /* R810 */
908 { 0x0000, 0x0000, 0x0000 }, /* R811 */
909 { 0x0000, 0x0000, 0x0000 }, /* R812 */
910 { 0x0000, 0x0000, 0x0000 }, /* R813 */
911 { 0x0000, 0x0000, 0x0000 }, /* R814 */
912 { 0x0000, 0x0000, 0x0000 }, /* R815 */
913 { 0x0000, 0x0000, 0x0000 }, /* R816 */
914 { 0x0000, 0x0000, 0x0000 }, /* R817 */
915 { 0x0000, 0x0000, 0x0000 }, /* R818 */
916 { 0x0000, 0x0000, 0x0000 }, /* R819 */
917 { 0x0000, 0x0000, 0x0000 }, /* R820 */
918 { 0x0000, 0x0000, 0x0000 }, /* R821 */
919 { 0x0000, 0x0000, 0x0000 }, /* R822 */
920 { 0x0000, 0x0000, 0x0000 }, /* R823 */
921 { 0x0000, 0x0000, 0x0000 }, /* R824 */
922 { 0x0000, 0x0000, 0x0000 }, /* R825 */
923 { 0x0000, 0x0000, 0x0000 }, /* R826 */
924 { 0x0000, 0x0000, 0x0000 }, /* R827 */
925 { 0x0000, 0x0000, 0x0000 }, /* R828 */
926 { 0x0000, 0x0000, 0x0000 }, /* R829 */
927 { 0x0000, 0x0000, 0x0000 }, /* R830 */
928 { 0x0000, 0x0000, 0x0000 }, /* R831 */
929 { 0x0000, 0x0000, 0x0000 }, /* R832 */
930 { 0x0000, 0x0000, 0x0000 }, /* R833 */
931 { 0x0000, 0x0000, 0x0000 }, /* R834 */
932 { 0x0000, 0x0000, 0x0000 }, /* R835 */
933 { 0x0000, 0x0000, 0x0000 }, /* R836 */
934 { 0x0000, 0x0000, 0x0000 }, /* R837 */
935 { 0x0000, 0x0000, 0x0000 }, /* R838 */
936 { 0x0000, 0x0000, 0x0000 }, /* R839 */
937 { 0x0000, 0x0000, 0x0000 }, /* R840 */
938 { 0x0000, 0x0000, 0x0000 }, /* R841 */
939 { 0x0000, 0x0000, 0x0000 }, /* R842 */
940 { 0x0000, 0x0000, 0x0000 }, /* R843 */
941 { 0x0000, 0x0000, 0x0000 }, /* R844 */
942 { 0x0000, 0x0000, 0x0000 }, /* R845 */
943 { 0x0000, 0x0000, 0x0000 }, /* R846 */
944 { 0x0000, 0x0000, 0x0000 }, /* R847 */
945 { 0x0000, 0x0000, 0x0000 }, /* R848 */
946 { 0x0000, 0x0000, 0x0000 }, /* R849 */
947 { 0x0000, 0x0000, 0x0000 }, /* R850 */
948 { 0x0000, 0x0000, 0x0000 }, /* R851 */
949 { 0x0000, 0x0000, 0x0000 }, /* R852 */
950 { 0x0000, 0x0000, 0x0000 }, /* R853 */
951 { 0x0000, 0x0000, 0x0000 }, /* R854 */
952 { 0x0000, 0x0000, 0x0000 }, /* R855 */
953 { 0x0000, 0x0000, 0x0000 }, /* R856 */
954 { 0x0000, 0x0000, 0x0000 }, /* R857 */
955 { 0x0000, 0x0000, 0x0000 }, /* R858 */
956 { 0x0000, 0x0000, 0x0000 }, /* R859 */
957 { 0x0000, 0x0000, 0x0000 }, /* R860 */
958 { 0x0000, 0x0000, 0x0000 }, /* R861 */
959 { 0x0000, 0x0000, 0x0000 }, /* R862 */
960 { 0x0000, 0x0000, 0x0000 }, /* R863 */
961 { 0x0000, 0x0000, 0x0000 }, /* R864 */
962 { 0x0000, 0x0000, 0x0000 }, /* R865 */
963 { 0x0000, 0x0000, 0x0000 }, /* R866 */
964 { 0x0000, 0x0000, 0x0000 }, /* R867 */
965 { 0x0000, 0x0000, 0x0000 }, /* R868 */
966 { 0x0000, 0x0000, 0x0000 }, /* R869 */
967 { 0x0000, 0x0000, 0x0000 }, /* R870 */
968 { 0x0000, 0x0000, 0x0000 }, /* R871 */
969 { 0x0000, 0x0000, 0x0000 }, /* R872 */
970 { 0x0000, 0x0000, 0x0000 }, /* R873 */
971 { 0x0000, 0x0000, 0x0000 }, /* R874 */
972 { 0x0000, 0x0000, 0x0000 }, /* R875 */
973 { 0x0000, 0x0000, 0x0000 }, /* R876 */
974 { 0x0000, 0x0000, 0x0000 }, /* R877 */
975 { 0x0000, 0x0000, 0x0000 }, /* R878 */
976 { 0x0000, 0x0000, 0x0000 }, /* R879 */
977 { 0x0000, 0x0000, 0x0000 }, /* R880 */
978 { 0x0000, 0x0000, 0x0000 }, /* R881 */
979 { 0x0000, 0x0000, 0x0000 }, /* R882 */
980 { 0x0000, 0x0000, 0x0000 }, /* R883 */
981 { 0x0000, 0x0000, 0x0000 }, /* R884 */
982 { 0x0000, 0x0000, 0x0000 }, /* R885 */
983 { 0x0000, 0x0000, 0x0000 }, /* R886 */
984 { 0x0000, 0x0000, 0x0000 }, /* R887 */
985 { 0x0000, 0x0000, 0x0000 }, /* R888 */
986 { 0x0000, 0x0000, 0x0000 }, /* R889 */
987 { 0x0000, 0x0000, 0x0000 }, /* R890 */
988 { 0x0000, 0x0000, 0x0000 }, /* R891 */
989 { 0x0000, 0x0000, 0x0000 }, /* R892 */
990 { 0x0000, 0x0000, 0x0000 }, /* R893 */
991 { 0x0000, 0x0000, 0x0000 }, /* R894 */
992 { 0x0000, 0x0000, 0x0000 }, /* R895 */
993 { 0x0000, 0x0000, 0x0000 }, /* R896 */
994 { 0x0000, 0x0000, 0x0000 }, /* R897 */
995 { 0x0000, 0x0000, 0x0000 }, /* R898 */
996 { 0x0000, 0x0000, 0x0000 }, /* R899 */
997 { 0x0000, 0x0000, 0x0000 }, /* R900 */
998 { 0x0000, 0x0000, 0x0000 }, /* R901 */
999 { 0x0000, 0x0000, 0x0000 }, /* R902 */
1000 { 0x0000, 0x0000, 0x0000 }, /* R903 */
1001 { 0x0000, 0x0000, 0x0000 }, /* R904 */
1002 { 0x0000, 0x0000, 0x0000 }, /* R905 */
1003 { 0x0000, 0x0000, 0x0000 }, /* R906 */
1004 { 0x0000, 0x0000, 0x0000 }, /* R907 */
1005 { 0x0000, 0x0000, 0x0000 }, /* R908 */
1006 { 0x0000, 0x0000, 0x0000 }, /* R909 */
1007 { 0x0000, 0x0000, 0x0000 }, /* R910 */
1008 { 0x0000, 0x0000, 0x0000 }, /* R911 */
1009 { 0x0000, 0x0000, 0x0000 }, /* R912 */
1010 { 0x0000, 0x0000, 0x0000 }, /* R913 */
1011 { 0x0000, 0x0000, 0x0000 }, /* R914 */
1012 { 0x0000, 0x0000, 0x0000 }, /* R915 */
1013 { 0x0000, 0x0000, 0x0000 }, /* R916 */
1014 { 0x0000, 0x0000, 0x0000 }, /* R917 */
1015 { 0x0000, 0x0000, 0x0000 }, /* R918 */
1016 { 0x0000, 0x0000, 0x0000 }, /* R919 */
1017 { 0x0000, 0x0000, 0x0000 }, /* R920 */
1018 { 0x0000, 0x0000, 0x0000 }, /* R921 */
1019 { 0x0000, 0x0000, 0x0000 }, /* R922 */
1020 { 0x0000, 0x0000, 0x0000 }, /* R923 */
1021 { 0x0000, 0x0000, 0x0000 }, /* R924 */
1022 { 0x0000, 0x0000, 0x0000 }, /* R925 */
1023 { 0x0000, 0x0000, 0x0000 }, /* R926 */
1024 { 0x0000, 0x0000, 0x0000 }, /* R927 */
1025 { 0x0000, 0x0000, 0x0000 }, /* R928 */
1026 { 0x0000, 0x0000, 0x0000 }, /* R929 */
1027 { 0x0000, 0x0000, 0x0000 }, /* R930 */
1028 { 0x0000, 0x0000, 0x0000 }, /* R931 */
1029 { 0x0000, 0x0000, 0x0000 }, /* R932 */
1030 { 0x0000, 0x0000, 0x0000 }, /* R933 */
1031 { 0x0000, 0x0000, 0x0000 }, /* R934 */
1032 { 0x0000, 0x0000, 0x0000 }, /* R935 */
1033 { 0x0000, 0x0000, 0x0000 }, /* R936 */
1034 { 0x0000, 0x0000, 0x0000 }, /* R937 */
1035 { 0x0000, 0x0000, 0x0000 }, /* R938 */
1036 { 0x0000, 0x0000, 0x0000 }, /* R939 */
1037 { 0x0000, 0x0000, 0x0000 }, /* R940 */
1038 { 0x0000, 0x0000, 0x0000 }, /* R941 */
1039 { 0x0000, 0x0000, 0x0000 }, /* R942 */
1040 { 0x0000, 0x0000, 0x0000 }, /* R943 */
1041 { 0x0000, 0x0000, 0x0000 }, /* R944 */
1042 { 0x0000, 0x0000, 0x0000 }, /* R945 */
1043 { 0x0000, 0x0000, 0x0000 }, /* R946 */
1044 { 0x0000, 0x0000, 0x0000 }, /* R947 */
1045 { 0x0000, 0x0000, 0x0000 }, /* R948 */
1046 { 0x0000, 0x0000, 0x0000 }, /* R949 */
1047 { 0x0000, 0x0000, 0x0000 }, /* R950 */
1048 { 0x0000, 0x0000, 0x0000 }, /* R951 */
1049 { 0x0000, 0x0000, 0x0000 }, /* R952 */
1050 { 0x0000, 0x0000, 0x0000 }, /* R953 */
1051 { 0x0000, 0x0000, 0x0000 }, /* R954 */
1052 { 0x0000, 0x0000, 0x0000 }, /* R955 */
1053 { 0x0000, 0x0000, 0x0000 }, /* R956 */
1054 { 0x0000, 0x0000, 0x0000 }, /* R957 */
1055 { 0x0000, 0x0000, 0x0000 }, /* R958 */
1056 { 0x0000, 0x0000, 0x0000 }, /* R959 */
1057 { 0x0000, 0x0000, 0x0000 }, /* R960 */
1058 { 0x0000, 0x0000, 0x0000 }, /* R961 */
1059 { 0x0000, 0x0000, 0x0000 }, /* R962 */
1060 { 0x0000, 0x0000, 0x0000 }, /* R963 */
1061 { 0x0000, 0x0000, 0x0000 }, /* R964 */
1062 { 0x0000, 0x0000, 0x0000 }, /* R965 */
1063 { 0x0000, 0x0000, 0x0000 }, /* R966 */
1064 { 0x0000, 0x0000, 0x0000 }, /* R967 */
1065 { 0x0000, 0x0000, 0x0000 }, /* R968 */
1066 { 0x0000, 0x0000, 0x0000 }, /* R969 */
1067 { 0x0000, 0x0000, 0x0000 }, /* R970 */
1068 { 0x0000, 0x0000, 0x0000 }, /* R971 */
1069 { 0x0000, 0x0000, 0x0000 }, /* R972 */
1070 { 0x0000, 0x0000, 0x0000 }, /* R973 */
1071 { 0x0000, 0x0000, 0x0000 }, /* R974 */
1072 { 0x0000, 0x0000, 0x0000 }, /* R975 */
1073 { 0x0000, 0x0000, 0x0000 }, /* R976 */
1074 { 0x0000, 0x0000, 0x0000 }, /* R977 */
1075 { 0x0000, 0x0000, 0x0000 }, /* R978 */
1076 { 0x0000, 0x0000, 0x0000 }, /* R979 */
1077 { 0x0000, 0x0000, 0x0000 }, /* R980 */
1078 { 0x0000, 0x0000, 0x0000 }, /* R981 */
1079 { 0x0000, 0x0000, 0x0000 }, /* R982 */
1080 { 0x0000, 0x0000, 0x0000 }, /* R983 */
1081 { 0x0000, 0x0000, 0x0000 }, /* R984 */
1082 { 0x0000, 0x0000, 0x0000 }, /* R985 */
1083 { 0x0000, 0x0000, 0x0000 }, /* R986 */
1084 { 0x0000, 0x0000, 0x0000 }, /* R987 */
1085 { 0x0000, 0x0000, 0x0000 }, /* R988 */
1086 { 0x0000, 0x0000, 0x0000 }, /* R989 */
1087 { 0x0000, 0x0000, 0x0000 }, /* R990 */
1088 { 0x0000, 0x0000, 0x0000 }, /* R991 */
1089 { 0x0000, 0x0000, 0x0000 }, /* R992 */
1090 { 0x0000, 0x0000, 0x0000 }, /* R993 */
1091 { 0x0000, 0x0000, 0x0000 }, /* R994 */
1092 { 0x0000, 0x0000, 0x0000 }, /* R995 */
1093 { 0x0000, 0x0000, 0x0000 }, /* R996 */
1094 { 0x0000, 0x0000, 0x0000 }, /* R997 */
1095 { 0x0000, 0x0000, 0x0000 }, /* R998 */
1096 { 0x0000, 0x0000, 0x0000 }, /* R999 */
1097 { 0x0000, 0x0000, 0x0000 }, /* R1000 */
1098 { 0x0000, 0x0000, 0x0000 }, /* R1001 */
1099 { 0x0000, 0x0000, 0x0000 }, /* R1002 */
1100 { 0x0000, 0x0000, 0x0000 }, /* R1003 */
1101 { 0x0000, 0x0000, 0x0000 }, /* R1004 */
1102 { 0x0000, 0x0000, 0x0000 }, /* R1005 */
1103 { 0x0000, 0x0000, 0x0000 }, /* R1006 */
1104 { 0x0000, 0x0000, 0x0000 }, /* R1007 */
1105 { 0x0000, 0x0000, 0x0000 }, /* R1008 */
1106 { 0x0000, 0x0000, 0x0000 }, /* R1009 */
1107 { 0x0000, 0x0000, 0x0000 }, /* R1010 */
1108 { 0x0000, 0x0000, 0x0000 }, /* R1011 */
1109 { 0x0000, 0x0000, 0x0000 }, /* R1012 */
1110 { 0x0000, 0x0000, 0x0000 }, /* R1013 */
1111 { 0x0000, 0x0000, 0x0000 }, /* R1014 */
1112 { 0x0000, 0x0000, 0x0000 }, /* R1015 */
1113 { 0x0000, 0x0000, 0x0000 }, /* R1016 */
1114 { 0x0000, 0x0000, 0x0000 }, /* R1017 */
1115 { 0x0000, 0x0000, 0x0000 }, /* R1018 */
1116 { 0x0000, 0x0000, 0x0000 }, /* R1019 */
1117 { 0x0000, 0x0000, 0x0000 }, /* R1020 */
1118 { 0x0000, 0x0000, 0x0000 }, /* R1021 */
1119 { 0x0000, 0x0000, 0x0000 }, /* R1022 */
1120 { 0x0000, 0x0000, 0x0000 }, /* R1023 */
1121 { 0x00FF, 0x01FF, 0x0000 }, /* R1024 - AIF1 ADC1 Left Volume */
1122 { 0x00FF, 0x01FF, 0x0000 }, /* R1025 - AIF1 ADC1 Right Volume */
1123 { 0x00FF, 0x01FF, 0x0000 }, /* R1026 - AIF1 DAC1 Left Volume */
1124 { 0x00FF, 0x01FF, 0x0000 }, /* R1027 - AIF1 DAC1 Right Volume */
1125 { 0x00FF, 0x01FF, 0x0000 }, /* R1028 - AIF1 ADC2 Left Volume */
1126 { 0x00FF, 0x01FF, 0x0000 }, /* R1029 - AIF1 ADC2 Right Volume */
1127 { 0x00FF, 0x01FF, 0x0000 }, /* R1030 - AIF1 DAC2 Left Volume */
1128 { 0x00FF, 0x01FF, 0x0000 }, /* R1031 - AIF1 DAC2 Right Volume */
1129 { 0x0000, 0x0000, 0x0000 }, /* R1032 */
1130 { 0x0000, 0x0000, 0x0000 }, /* R1033 */
1131 { 0x0000, 0x0000, 0x0000 }, /* R1034 */
1132 { 0x0000, 0x0000, 0x0000 }, /* R1035 */
1133 { 0x0000, 0x0000, 0x0000 }, /* R1036 */
1134 { 0x0000, 0x0000, 0x0000 }, /* R1037 */
1135 { 0x0000, 0x0000, 0x0000 }, /* R1038 */
1136 { 0x0000, 0x0000, 0x0000 }, /* R1039 */
1137 { 0xF800, 0xF800, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
1138 { 0x7800, 0x7800, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
1139 { 0x0000, 0x0000, 0x0000 }, /* R1042 */
1140 { 0x0000, 0x0000, 0x0000 }, /* R1043 */
1141 { 0x0000, 0x0000, 0x0000 }, /* R1044 */
1142 { 0x0000, 0x0000, 0x0000 }, /* R1045 */
1143 { 0x0000, 0x0000, 0x0000 }, /* R1046 */
1144 { 0x0000, 0x0000, 0x0000 }, /* R1047 */
1145 { 0x0000, 0x0000, 0x0000 }, /* R1048 */
1146 { 0x0000, 0x0000, 0x0000 }, /* R1049 */
1147 { 0x0000, 0x0000, 0x0000 }, /* R1050 */
1148 { 0x0000, 0x0000, 0x0000 }, /* R1051 */
1149 { 0x0000, 0x0000, 0x0000 }, /* R1052 */
1150 { 0x0000, 0x0000, 0x0000 }, /* R1053 */
1151 { 0x0000, 0x0000, 0x0000 }, /* R1054 */
1152 { 0x0000, 0x0000, 0x0000 }, /* R1055 */
1153 { 0x02B6, 0x02B6, 0x0000 }, /* R1056 - AIF1 DAC1 Filters (1) */
1154 { 0x3F00, 0x3F00, 0x0000 }, /* R1057 - AIF1 DAC1 Filters (2) */
1155 { 0x02B6, 0x02B6, 0x0000 }, /* R1058 - AIF1 DAC2 Filters (1) */
1156 { 0x3F00, 0x3F00, 0x0000 }, /* R1059 - AIF1 DAC2 Filters (2) */
1157 { 0x0000, 0x0000, 0x0000 }, /* R1060 */
1158 { 0x0000, 0x0000, 0x0000 }, /* R1061 */
1159 { 0x0000, 0x0000, 0x0000 }, /* R1062 */
1160 { 0x0000, 0x0000, 0x0000 }, /* R1063 */
1161 { 0x0000, 0x0000, 0x0000 }, /* R1064 */
1162 { 0x0000, 0x0000, 0x0000 }, /* R1065 */
1163 { 0x0000, 0x0000, 0x0000 }, /* R1066 */
1164 { 0x0000, 0x0000, 0x0000 }, /* R1067 */
1165 { 0x0000, 0x0000, 0x0000 }, /* R1068 */
1166 { 0x0000, 0x0000, 0x0000 }, /* R1069 */
1167 { 0x0000, 0x0000, 0x0000 }, /* R1070 */
1168 { 0x0000, 0x0000, 0x0000 }, /* R1071 */
1169 { 0x0000, 0x0000, 0x0000 }, /* R1072 */
1170 { 0x0000, 0x0000, 0x0000 }, /* R1073 */
1171 { 0x0000, 0x0000, 0x0000 }, /* R1074 */
1172 { 0x0000, 0x0000, 0x0000 }, /* R1075 */
1173 { 0x0000, 0x0000, 0x0000 }, /* R1076 */
1174 { 0x0000, 0x0000, 0x0000 }, /* R1077 */
1175 { 0x0000, 0x0000, 0x0000 }, /* R1078 */
1176 { 0x0000, 0x0000, 0x0000 }, /* R1079 */
1177 { 0x0000, 0x0000, 0x0000 }, /* R1080 */
1178 { 0x0000, 0x0000, 0x0000 }, /* R1081 */
1179 { 0x0000, 0x0000, 0x0000 }, /* R1082 */
1180 { 0x0000, 0x0000, 0x0000 }, /* R1083 */
1181 { 0x0000, 0x0000, 0x0000 }, /* R1084 */
1182 { 0x0000, 0x0000, 0x0000 }, /* R1085 */
1183 { 0x0000, 0x0000, 0x0000 }, /* R1086 */
1184 { 0x0000, 0x0000, 0x0000 }, /* R1087 */
1185 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1088 - AIF1 DRC1 (1) */
1186 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1089 - AIF1 DRC1 (2) */
1187 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
1188 { 0x07FF, 0x07FF, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
1189 { 0x03FF, 0x03FF, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
1190 { 0x0000, 0x0000, 0x0000 }, /* R1093 */
1191 { 0x0000, 0x0000, 0x0000 }, /* R1094 */
1192 { 0x0000, 0x0000, 0x0000 }, /* R1095 */
1193 { 0x0000, 0x0000, 0x0000 }, /* R1096 */
1194 { 0x0000, 0x0000, 0x0000 }, /* R1097 */
1195 { 0x0000, 0x0000, 0x0000 }, /* R1098 */
1196 { 0x0000, 0x0000, 0x0000 }, /* R1099 */
1197 { 0x0000, 0x0000, 0x0000 }, /* R1100 */
1198 { 0x0000, 0x0000, 0x0000 }, /* R1101 */
1199 { 0x0000, 0x0000, 0x0000 }, /* R1102 */
1200 { 0x0000, 0x0000, 0x0000 }, /* R1103 */
1201 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1104 - AIF1 DRC2 (1) */
1202 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1105 - AIF1 DRC2 (2) */
1203 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
1204 { 0x07FF, 0x07FF, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
1205 { 0x03FF, 0x03FF, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
1206 { 0x0000, 0x0000, 0x0000 }, /* R1109 */
1207 { 0x0000, 0x0000, 0x0000 }, /* R1110 */
1208 { 0x0000, 0x0000, 0x0000 }, /* R1111 */
1209 { 0x0000, 0x0000, 0x0000 }, /* R1112 */
1210 { 0x0000, 0x0000, 0x0000 }, /* R1113 */
1211 { 0x0000, 0x0000, 0x0000 }, /* R1114 */
1212 { 0x0000, 0x0000, 0x0000 }, /* R1115 */
1213 { 0x0000, 0x0000, 0x0000 }, /* R1116 */
1214 { 0x0000, 0x0000, 0x0000 }, /* R1117 */
1215 { 0x0000, 0x0000, 0x0000 }, /* R1118 */
1216 { 0x0000, 0x0000, 0x0000 }, /* R1119 */
1217 { 0x0000, 0x0000, 0x0000 }, /* R1120 */
1218 { 0x0000, 0x0000, 0x0000 }, /* R1121 */
1219 { 0x0000, 0x0000, 0x0000 }, /* R1122 */
1220 { 0x0000, 0x0000, 0x0000 }, /* R1123 */
1221 { 0x0000, 0x0000, 0x0000 }, /* R1124 */
1222 { 0x0000, 0x0000, 0x0000 }, /* R1125 */
1223 { 0x0000, 0x0000, 0x0000 }, /* R1126 */
1224 { 0x0000, 0x0000, 0x0000 }, /* R1127 */
1225 { 0x0000, 0x0000, 0x0000 }, /* R1128 */
1226 { 0x0000, 0x0000, 0x0000 }, /* R1129 */
1227 { 0x0000, 0x0000, 0x0000 }, /* R1130 */
1228 { 0x0000, 0x0000, 0x0000 }, /* R1131 */
1229 { 0x0000, 0x0000, 0x0000 }, /* R1132 */
1230 { 0x0000, 0x0000, 0x0000 }, /* R1133 */
1231 { 0x0000, 0x0000, 0x0000 }, /* R1134 */
1232 { 0x0000, 0x0000, 0x0000 }, /* R1135 */
1233 { 0x0000, 0x0000, 0x0000 }, /* R1136 */
1234 { 0x0000, 0x0000, 0x0000 }, /* R1137 */
1235 { 0x0000, 0x0000, 0x0000 }, /* R1138 */
1236 { 0x0000, 0x0000, 0x0000 }, /* R1139 */
1237 { 0x0000, 0x0000, 0x0000 }, /* R1140 */
1238 { 0x0000, 0x0000, 0x0000 }, /* R1141 */
1239 { 0x0000, 0x0000, 0x0000 }, /* R1142 */
1240 { 0x0000, 0x0000, 0x0000 }, /* R1143 */
1241 { 0x0000, 0x0000, 0x0000 }, /* R1144 */
1242 { 0x0000, 0x0000, 0x0000 }, /* R1145 */
1243 { 0x0000, 0x0000, 0x0000 }, /* R1146 */
1244 { 0x0000, 0x0000, 0x0000 }, /* R1147 */
1245 { 0x0000, 0x0000, 0x0000 }, /* R1148 */
1246 { 0x0000, 0x0000, 0x0000 }, /* R1149 */
1247 { 0x0000, 0x0000, 0x0000 }, /* R1150 */
1248 { 0x0000, 0x0000, 0x0000 }, /* R1151 */
1249 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
1250 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
1251 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
1252 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
1253 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
1254 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
1255 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
1256 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
1257 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
1258 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
1259 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
1260 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
1261 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
1262 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
1263 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
1264 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
1265 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
1266 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
1267 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
1268 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
1269 { 0x0000, 0x0000, 0x0000 }, /* R1172 */
1270 { 0x0000, 0x0000, 0x0000 }, /* R1173 */
1271 { 0x0000, 0x0000, 0x0000 }, /* R1174 */
1272 { 0x0000, 0x0000, 0x0000 }, /* R1175 */
1273 { 0x0000, 0x0000, 0x0000 }, /* R1176 */
1274 { 0x0000, 0x0000, 0x0000 }, /* R1177 */
1275 { 0x0000, 0x0000, 0x0000 }, /* R1178 */
1276 { 0x0000, 0x0000, 0x0000 }, /* R1179 */
1277 { 0x0000, 0x0000, 0x0000 }, /* R1180 */
1278 { 0x0000, 0x0000, 0x0000 }, /* R1181 */
1279 { 0x0000, 0x0000, 0x0000 }, /* R1182 */
1280 { 0x0000, 0x0000, 0x0000 }, /* R1183 */
1281 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
1282 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
1283 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
1284 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
1285 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
1286 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
1287 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
1288 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
1289 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
1290 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
1291 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
1292 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
1293 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
1294 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
1295 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
1296 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
1297 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
1298 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
1299 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
1300 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
1301 { 0x0000, 0x0000, 0x0000 }, /* R1204 */
1302 { 0x0000, 0x0000, 0x0000 }, /* R1205 */
1303 { 0x0000, 0x0000, 0x0000 }, /* R1206 */
1304 { 0x0000, 0x0000, 0x0000 }, /* R1207 */
1305 { 0x0000, 0x0000, 0x0000 }, /* R1208 */
1306 { 0x0000, 0x0000, 0x0000 }, /* R1209 */
1307 { 0x0000, 0x0000, 0x0000 }, /* R1210 */
1308 { 0x0000, 0x0000, 0x0000 }, /* R1211 */
1309 { 0x0000, 0x0000, 0x0000 }, /* R1212 */
1310 { 0x0000, 0x0000, 0x0000 }, /* R1213 */
1311 { 0x0000, 0x0000, 0x0000 }, /* R1214 */
1312 { 0x0000, 0x0000, 0x0000 }, /* R1215 */
1313 { 0x0000, 0x0000, 0x0000 }, /* R1216 */
1314 { 0x0000, 0x0000, 0x0000 }, /* R1217 */
1315 { 0x0000, 0x0000, 0x0000 }, /* R1218 */
1316 { 0x0000, 0x0000, 0x0000 }, /* R1219 */
1317 { 0x0000, 0x0000, 0x0000 }, /* R1220 */
1318 { 0x0000, 0x0000, 0x0000 }, /* R1221 */
1319 { 0x0000, 0x0000, 0x0000 }, /* R1222 */
1320 { 0x0000, 0x0000, 0x0000 }, /* R1223 */
1321 { 0x0000, 0x0000, 0x0000 }, /* R1224 */
1322 { 0x0000, 0x0000, 0x0000 }, /* R1225 */
1323 { 0x0000, 0x0000, 0x0000 }, /* R1226 */
1324 { 0x0000, 0x0000, 0x0000 }, /* R1227 */
1325 { 0x0000, 0x0000, 0x0000 }, /* R1228 */
1326 { 0x0000, 0x0000, 0x0000 }, /* R1229 */
1327 { 0x0000, 0x0000, 0x0000 }, /* R1230 */
1328 { 0x0000, 0x0000, 0x0000 }, /* R1231 */
1329 { 0x0000, 0x0000, 0x0000 }, /* R1232 */
1330 { 0x0000, 0x0000, 0x0000 }, /* R1233 */
1331 { 0x0000, 0x0000, 0x0000 }, /* R1234 */
1332 { 0x0000, 0x0000, 0x0000 }, /* R1235 */
1333 { 0x0000, 0x0000, 0x0000 }, /* R1236 */
1334 { 0x0000, 0x0000, 0x0000 }, /* R1237 */
1335 { 0x0000, 0x0000, 0x0000 }, /* R1238 */
1336 { 0x0000, 0x0000, 0x0000 }, /* R1239 */
1337 { 0x0000, 0x0000, 0x0000 }, /* R1240 */
1338 { 0x0000, 0x0000, 0x0000 }, /* R1241 */
1339 { 0x0000, 0x0000, 0x0000 }, /* R1242 */
1340 { 0x0000, 0x0000, 0x0000 }, /* R1243 */
1341 { 0x0000, 0x0000, 0x0000 }, /* R1244 */
1342 { 0x0000, 0x0000, 0x0000 }, /* R1245 */
1343 { 0x0000, 0x0000, 0x0000 }, /* R1246 */
1344 { 0x0000, 0x0000, 0x0000 }, /* R1247 */
1345 { 0x0000, 0x0000, 0x0000 }, /* R1248 */
1346 { 0x0000, 0x0000, 0x0000 }, /* R1249 */
1347 { 0x0000, 0x0000, 0x0000 }, /* R1250 */
1348 { 0x0000, 0x0000, 0x0000 }, /* R1251 */
1349 { 0x0000, 0x0000, 0x0000 }, /* R1252 */
1350 { 0x0000, 0x0000, 0x0000 }, /* R1253 */
1351 { 0x0000, 0x0000, 0x0000 }, /* R1254 */
1352 { 0x0000, 0x0000, 0x0000 }, /* R1255 */
1353 { 0x0000, 0x0000, 0x0000 }, /* R1256 */
1354 { 0x0000, 0x0000, 0x0000 }, /* R1257 */
1355 { 0x0000, 0x0000, 0x0000 }, /* R1258 */
1356 { 0x0000, 0x0000, 0x0000 }, /* R1259 */
1357 { 0x0000, 0x0000, 0x0000 }, /* R1260 */
1358 { 0x0000, 0x0000, 0x0000 }, /* R1261 */
1359 { 0x0000, 0x0000, 0x0000 }, /* R1262 */
1360 { 0x0000, 0x0000, 0x0000 }, /* R1263 */
1361 { 0x0000, 0x0000, 0x0000 }, /* R1264 */
1362 { 0x0000, 0x0000, 0x0000 }, /* R1265 */
1363 { 0x0000, 0x0000, 0x0000 }, /* R1266 */
1364 { 0x0000, 0x0000, 0x0000 }, /* R1267 */
1365 { 0x0000, 0x0000, 0x0000 }, /* R1268 */
1366 { 0x0000, 0x0000, 0x0000 }, /* R1269 */
1367 { 0x0000, 0x0000, 0x0000 }, /* R1270 */
1368 { 0x0000, 0x0000, 0x0000 }, /* R1271 */
1369 { 0x0000, 0x0000, 0x0000 }, /* R1272 */
1370 { 0x0000, 0x0000, 0x0000 }, /* R1273 */
1371 { 0x0000, 0x0000, 0x0000 }, /* R1274 */
1372 { 0x0000, 0x0000, 0x0000 }, /* R1275 */
1373 { 0x0000, 0x0000, 0x0000 }, /* R1276 */
1374 { 0x0000, 0x0000, 0x0000 }, /* R1277 */
1375 { 0x0000, 0x0000, 0x0000 }, /* R1278 */
1376 { 0x0000, 0x0000, 0x0000 }, /* R1279 */
1377 { 0x00FF, 0x01FF, 0x0000 }, /* R1280 - AIF2 ADC Left Volume */
1378 { 0x00FF, 0x01FF, 0x0000 }, /* R1281 - AIF2 ADC Right Volume */
1379 { 0x00FF, 0x01FF, 0x0000 }, /* R1282 - AIF2 DAC Left Volume */
1380 { 0x00FF, 0x01FF, 0x0000 }, /* R1283 - AIF2 DAC Right Volume */
1381 { 0x0000, 0x0000, 0x0000 }, /* R1284 */
1382 { 0x0000, 0x0000, 0x0000 }, /* R1285 */
1383 { 0x0000, 0x0000, 0x0000 }, /* R1286 */
1384 { 0x0000, 0x0000, 0x0000 }, /* R1287 */
1385 { 0x0000, 0x0000, 0x0000 }, /* R1288 */
1386 { 0x0000, 0x0000, 0x0000 }, /* R1289 */
1387 { 0x0000, 0x0000, 0x0000 }, /* R1290 */
1388 { 0x0000, 0x0000, 0x0000 }, /* R1291 */
1389 { 0x0000, 0x0000, 0x0000 }, /* R1292 */
1390 { 0x0000, 0x0000, 0x0000 }, /* R1293 */
1391 { 0x0000, 0x0000, 0x0000 }, /* R1294 */
1392 { 0x0000, 0x0000, 0x0000 }, /* R1295 */
1393 { 0xF800, 0xF800, 0x0000 }, /* R1296 - AIF2 ADC Filters */
1394 { 0x0000, 0x0000, 0x0000 }, /* R1297 */
1395 { 0x0000, 0x0000, 0x0000 }, /* R1298 */
1396 { 0x0000, 0x0000, 0x0000 }, /* R1299 */
1397 { 0x0000, 0x0000, 0x0000 }, /* R1300 */
1398 { 0x0000, 0x0000, 0x0000 }, /* R1301 */
1399 { 0x0000, 0x0000, 0x0000 }, /* R1302 */
1400 { 0x0000, 0x0000, 0x0000 }, /* R1303 */
1401 { 0x0000, 0x0000, 0x0000 }, /* R1304 */
1402 { 0x0000, 0x0000, 0x0000 }, /* R1305 */
1403 { 0x0000, 0x0000, 0x0000 }, /* R1306 */
1404 { 0x0000, 0x0000, 0x0000 }, /* R1307 */
1405 { 0x0000, 0x0000, 0x0000 }, /* R1308 */
1406 { 0x0000, 0x0000, 0x0000 }, /* R1309 */
1407 { 0x0000, 0x0000, 0x0000 }, /* R1310 */
1408 { 0x0000, 0x0000, 0x0000 }, /* R1311 */
1409 { 0x02B6, 0x02B6, 0x0000 }, /* R1312 - AIF2 DAC Filters (1) */
1410 { 0x3F00, 0x3F00, 0x0000 }, /* R1313 - AIF2 DAC Filters (2) */
1411 { 0x0000, 0x0000, 0x0000 }, /* R1314 */
1412 { 0x0000, 0x0000, 0x0000 }, /* R1315 */
1413 { 0x0000, 0x0000, 0x0000 }, /* R1316 */
1414 { 0x0000, 0x0000, 0x0000 }, /* R1317 */
1415 { 0x0000, 0x0000, 0x0000 }, /* R1318 */
1416 { 0x0000, 0x0000, 0x0000 }, /* R1319 */
1417 { 0x0000, 0x0000, 0x0000 }, /* R1320 */
1418 { 0x0000, 0x0000, 0x0000 }, /* R1321 */
1419 { 0x0000, 0x0000, 0x0000 }, /* R1322 */
1420 { 0x0000, 0x0000, 0x0000 }, /* R1323 */
1421 { 0x0000, 0x0000, 0x0000 }, /* R1324 */
1422 { 0x0000, 0x0000, 0x0000 }, /* R1325 */
1423 { 0x0000, 0x0000, 0x0000 }, /* R1326 */
1424 { 0x0000, 0x0000, 0x0000 }, /* R1327 */
1425 { 0x0000, 0x0000, 0x0000 }, /* R1328 */
1426 { 0x0000, 0x0000, 0x0000 }, /* R1329 */
1427 { 0x0000, 0x0000, 0x0000 }, /* R1330 */
1428 { 0x0000, 0x0000, 0x0000 }, /* R1331 */
1429 { 0x0000, 0x0000, 0x0000 }, /* R1332 */
1430 { 0x0000, 0x0000, 0x0000 }, /* R1333 */
1431 { 0x0000, 0x0000, 0x0000 }, /* R1334 */
1432 { 0x0000, 0x0000, 0x0000 }, /* R1335 */
1433 { 0x0000, 0x0000, 0x0000 }, /* R1336 */
1434 { 0x0000, 0x0000, 0x0000 }, /* R1337 */
1435 { 0x0000, 0x0000, 0x0000 }, /* R1338 */
1436 { 0x0000, 0x0000, 0x0000 }, /* R1339 */
1437 { 0x0000, 0x0000, 0x0000 }, /* R1340 */
1438 { 0x0000, 0x0000, 0x0000 }, /* R1341 */
1439 { 0x0000, 0x0000, 0x0000 }, /* R1342 */
1440 { 0x0000, 0x0000, 0x0000 }, /* R1343 */
1441 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1344 - AIF2 DRC (1) */
1442 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1345 - AIF2 DRC (2) */
1443 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1346 - AIF2 DRC (3) */
1444 { 0x07FF, 0x07FF, 0x0000 }, /* R1347 - AIF2 DRC (4) */
1445 { 0x03FF, 0x03FF, 0x0000 }, /* R1348 - AIF2 DRC (5) */
1446 { 0x0000, 0x0000, 0x0000 }, /* R1349 */
1447 { 0x0000, 0x0000, 0x0000 }, /* R1350 */
1448 { 0x0000, 0x0000, 0x0000 }, /* R1351 */
1449 { 0x0000, 0x0000, 0x0000 }, /* R1352 */
1450 { 0x0000, 0x0000, 0x0000 }, /* R1353 */
1451 { 0x0000, 0x0000, 0x0000 }, /* R1354 */
1452 { 0x0000, 0x0000, 0x0000 }, /* R1355 */
1453 { 0x0000, 0x0000, 0x0000 }, /* R1356 */
1454 { 0x0000, 0x0000, 0x0000 }, /* R1357 */
1455 { 0x0000, 0x0000, 0x0000 }, /* R1358 */
1456 { 0x0000, 0x0000, 0x0000 }, /* R1359 */
1457 { 0x0000, 0x0000, 0x0000 }, /* R1360 */
1458 { 0x0000, 0x0000, 0x0000 }, /* R1361 */
1459 { 0x0000, 0x0000, 0x0000 }, /* R1362 */
1460 { 0x0000, 0x0000, 0x0000 }, /* R1363 */
1461 { 0x0000, 0x0000, 0x0000 }, /* R1364 */
1462 { 0x0000, 0x0000, 0x0000 }, /* R1365 */
1463 { 0x0000, 0x0000, 0x0000 }, /* R1366 */
1464 { 0x0000, 0x0000, 0x0000 }, /* R1367 */
1465 { 0x0000, 0x0000, 0x0000 }, /* R1368 */
1466 { 0x0000, 0x0000, 0x0000 }, /* R1369 */
1467 { 0x0000, 0x0000, 0x0000 }, /* R1370 */
1468 { 0x0000, 0x0000, 0x0000 }, /* R1371 */
1469 { 0x0000, 0x0000, 0x0000 }, /* R1372 */
1470 { 0x0000, 0x0000, 0x0000 }, /* R1373 */
1471 { 0x0000, 0x0000, 0x0000 }, /* R1374 */
1472 { 0x0000, 0x0000, 0x0000 }, /* R1375 */
1473 { 0x0000, 0x0000, 0x0000 }, /* R1376 */
1474 { 0x0000, 0x0000, 0x0000 }, /* R1377 */
1475 { 0x0000, 0x0000, 0x0000 }, /* R1378 */
1476 { 0x0000, 0x0000, 0x0000 }, /* R1379 */
1477 { 0x0000, 0x0000, 0x0000 }, /* R1380 */
1478 { 0x0000, 0x0000, 0x0000 }, /* R1381 */
1479 { 0x0000, 0x0000, 0x0000 }, /* R1382 */
1480 { 0x0000, 0x0000, 0x0000 }, /* R1383 */
1481 { 0x0000, 0x0000, 0x0000 }, /* R1384 */
1482 { 0x0000, 0x0000, 0x0000 }, /* R1385 */
1483 { 0x0000, 0x0000, 0x0000 }, /* R1386 */
1484 { 0x0000, 0x0000, 0x0000 }, /* R1387 */
1485 { 0x0000, 0x0000, 0x0000 }, /* R1388 */
1486 { 0x0000, 0x0000, 0x0000 }, /* R1389 */
1487 { 0x0000, 0x0000, 0x0000 }, /* R1390 */
1488 { 0x0000, 0x0000, 0x0000 }, /* R1391 */
1489 { 0x0000, 0x0000, 0x0000 }, /* R1392 */
1490 { 0x0000, 0x0000, 0x0000 }, /* R1393 */
1491 { 0x0000, 0x0000, 0x0000 }, /* R1394 */
1492 { 0x0000, 0x0000, 0x0000 }, /* R1395 */
1493 { 0x0000, 0x0000, 0x0000 }, /* R1396 */
1494 { 0x0000, 0x0000, 0x0000 }, /* R1397 */
1495 { 0x0000, 0x0000, 0x0000 }, /* R1398 */
1496 { 0x0000, 0x0000, 0x0000 }, /* R1399 */
1497 { 0x0000, 0x0000, 0x0000 }, /* R1400 */
1498 { 0x0000, 0x0000, 0x0000 }, /* R1401 */
1499 { 0x0000, 0x0000, 0x0000 }, /* R1402 */
1500 { 0x0000, 0x0000, 0x0000 }, /* R1403 */
1501 { 0x0000, 0x0000, 0x0000 }, /* R1404 */
1502 { 0x0000, 0x0000, 0x0000 }, /* R1405 */
1503 { 0x0000, 0x0000, 0x0000 }, /* R1406 */
1504 { 0x0000, 0x0000, 0x0000 }, /* R1407 */
1505 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1408 - AIF2 EQ Gains (1) */
1506 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1409 - AIF2 EQ Gains (2) */
1507 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1410 - AIF2 EQ Band 1 A */
1508 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1411 - AIF2 EQ Band 1 B */
1509 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1412 - AIF2 EQ Band 1 PG */
1510 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1413 - AIF2 EQ Band 2 A */
1511 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1414 - AIF2 EQ Band 2 B */
1512 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1415 - AIF2 EQ Band 2 C */
1513 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1416 - AIF2 EQ Band 2 PG */
1514 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1417 - AIF2 EQ Band 3 A */
1515 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1418 - AIF2 EQ Band 3 B */
1516 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1419 - AIF2 EQ Band 3 C */
1517 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1420 - AIF2 EQ Band 3 PG */
1518 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1421 - AIF2 EQ Band 4 A */
1519 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1422 - AIF2 EQ Band 4 B */
1520 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1423 - AIF2 EQ Band 4 C */
1521 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1424 - AIF2 EQ Band 4 PG */
1522 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1425 - AIF2 EQ Band 5 A */
1523 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1426 - AIF2 EQ Band 5 B */
1524 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1427 - AIF2 EQ Band 5 PG */
1525 { 0x0000, 0x0000, 0x0000 }, /* R1428 */
1526 { 0x0000, 0x0000, 0x0000 }, /* R1429 */
1527 { 0x0000, 0x0000, 0x0000 }, /* R1430 */
1528 { 0x0000, 0x0000, 0x0000 }, /* R1431 */
1529 { 0x0000, 0x0000, 0x0000 }, /* R1432 */
1530 { 0x0000, 0x0000, 0x0000 }, /* R1433 */
1531 { 0x0000, 0x0000, 0x0000 }, /* R1434 */
1532 { 0x0000, 0x0000, 0x0000 }, /* R1435 */
1533 { 0x0000, 0x0000, 0x0000 }, /* R1436 */
1534 { 0x0000, 0x0000, 0x0000 }, /* R1437 */
1535 { 0x0000, 0x0000, 0x0000 }, /* R1438 */
1536 { 0x0000, 0x0000, 0x0000 }, /* R1439 */
1537 { 0x0000, 0x0000, 0x0000 }, /* R1440 */
1538 { 0x0000, 0x0000, 0x0000 }, /* R1441 */
1539 { 0x0000, 0x0000, 0x0000 }, /* R1442 */
1540 { 0x0000, 0x0000, 0x0000 }, /* R1443 */
1541 { 0x0000, 0x0000, 0x0000 }, /* R1444 */
1542 { 0x0000, 0x0000, 0x0000 }, /* R1445 */
1543 { 0x0000, 0x0000, 0x0000 }, /* R1446 */
1544 { 0x0000, 0x0000, 0x0000 }, /* R1447 */
1545 { 0x0000, 0x0000, 0x0000 }, /* R1448 */
1546 { 0x0000, 0x0000, 0x0000 }, /* R1449 */
1547 { 0x0000, 0x0000, 0x0000 }, /* R1450 */
1548 { 0x0000, 0x0000, 0x0000 }, /* R1451 */
1549 { 0x0000, 0x0000, 0x0000 }, /* R1452 */
1550 { 0x0000, 0x0000, 0x0000 }, /* R1453 */
1551 { 0x0000, 0x0000, 0x0000 }, /* R1454 */
1552 { 0x0000, 0x0000, 0x0000 }, /* R1455 */
1553 { 0x0000, 0x0000, 0x0000 }, /* R1456 */
1554 { 0x0000, 0x0000, 0x0000 }, /* R1457 */
1555 { 0x0000, 0x0000, 0x0000 }, /* R1458 */
1556 { 0x0000, 0x0000, 0x0000 }, /* R1459 */
1557 { 0x0000, 0x0000, 0x0000 }, /* R1460 */
1558 { 0x0000, 0x0000, 0x0000 }, /* R1461 */
1559 { 0x0000, 0x0000, 0x0000 }, /* R1462 */
1560 { 0x0000, 0x0000, 0x0000 }, /* R1463 */
1561 { 0x0000, 0x0000, 0x0000 }, /* R1464 */
1562 { 0x0000, 0x0000, 0x0000 }, /* R1465 */
1563 { 0x0000, 0x0000, 0x0000 }, /* R1466 */
1564 { 0x0000, 0x0000, 0x0000 }, /* R1467 */
1565 { 0x0000, 0x0000, 0x0000 }, /* R1468 */
1566 { 0x0000, 0x0000, 0x0000 }, /* R1469 */
1567 { 0x0000, 0x0000, 0x0000 }, /* R1470 */
1568 { 0x0000, 0x0000, 0x0000 }, /* R1471 */
1569 { 0x0000, 0x0000, 0x0000 }, /* R1472 */
1570 { 0x0000, 0x0000, 0x0000 }, /* R1473 */
1571 { 0x0000, 0x0000, 0x0000 }, /* R1474 */
1572 { 0x0000, 0x0000, 0x0000 }, /* R1475 */
1573 { 0x0000, 0x0000, 0x0000 }, /* R1476 */
1574 { 0x0000, 0x0000, 0x0000 }, /* R1477 */
1575 { 0x0000, 0x0000, 0x0000 }, /* R1478 */
1576 { 0x0000, 0x0000, 0x0000 }, /* R1479 */
1577 { 0x0000, 0x0000, 0x0000 }, /* R1480 */
1578 { 0x0000, 0x0000, 0x0000 }, /* R1481 */
1579 { 0x0000, 0x0000, 0x0000 }, /* R1482 */
1580 { 0x0000, 0x0000, 0x0000 }, /* R1483 */
1581 { 0x0000, 0x0000, 0x0000 }, /* R1484 */
1582 { 0x0000, 0x0000, 0x0000 }, /* R1485 */
1583 { 0x0000, 0x0000, 0x0000 }, /* R1486 */
1584 { 0x0000, 0x0000, 0x0000 }, /* R1487 */
1585 { 0x0000, 0x0000, 0x0000 }, /* R1488 */
1586 { 0x0000, 0x0000, 0x0000 }, /* R1489 */
1587 { 0x0000, 0x0000, 0x0000 }, /* R1490 */
1588 { 0x0000, 0x0000, 0x0000 }, /* R1491 */
1589 { 0x0000, 0x0000, 0x0000 }, /* R1492 */
1590 { 0x0000, 0x0000, 0x0000 }, /* R1493 */
1591 { 0x0000, 0x0000, 0x0000 }, /* R1494 */
1592 { 0x0000, 0x0000, 0x0000 }, /* R1495 */
1593 { 0x0000, 0x0000, 0x0000 }, /* R1496 */
1594 { 0x0000, 0x0000, 0x0000 }, /* R1497 */
1595 { 0x0000, 0x0000, 0x0000 }, /* R1498 */
1596 { 0x0000, 0x0000, 0x0000 }, /* R1499 */
1597 { 0x0000, 0x0000, 0x0000 }, /* R1500 */
1598 { 0x0000, 0x0000, 0x0000 }, /* R1501 */
1599 { 0x0000, 0x0000, 0x0000 }, /* R1502 */
1600 { 0x0000, 0x0000, 0x0000 }, /* R1503 */
1601 { 0x0000, 0x0000, 0x0000 }, /* R1504 */
1602 { 0x0000, 0x0000, 0x0000 }, /* R1505 */
1603 { 0x0000, 0x0000, 0x0000 }, /* R1506 */
1604 { 0x0000, 0x0000, 0x0000 }, /* R1507 */
1605 { 0x0000, 0x0000, 0x0000 }, /* R1508 */
1606 { 0x0000, 0x0000, 0x0000 }, /* R1509 */
1607 { 0x0000, 0x0000, 0x0000 }, /* R1510 */
1608 { 0x0000, 0x0000, 0x0000 }, /* R1511 */
1609 { 0x0000, 0x0000, 0x0000 }, /* R1512 */
1610 { 0x0000, 0x0000, 0x0000 }, /* R1513 */
1611 { 0x0000, 0x0000, 0x0000 }, /* R1514 */
1612 { 0x0000, 0x0000, 0x0000 }, /* R1515 */
1613 { 0x0000, 0x0000, 0x0000 }, /* R1516 */
1614 { 0x0000, 0x0000, 0x0000 }, /* R1517 */
1615 { 0x0000, 0x0000, 0x0000 }, /* R1518 */
1616 { 0x0000, 0x0000, 0x0000 }, /* R1519 */
1617 { 0x0000, 0x0000, 0x0000 }, /* R1520 */
1618 { 0x0000, 0x0000, 0x0000 }, /* R1521 */
1619 { 0x0000, 0x0000, 0x0000 }, /* R1522 */
1620 { 0x0000, 0x0000, 0x0000 }, /* R1523 */
1621 { 0x0000, 0x0000, 0x0000 }, /* R1524 */
1622 { 0x0000, 0x0000, 0x0000 }, /* R1525 */
1623 { 0x0000, 0x0000, 0x0000 }, /* R1526 */
1624 { 0x0000, 0x0000, 0x0000 }, /* R1527 */
1625 { 0x0000, 0x0000, 0x0000 }, /* R1528 */
1626 { 0x0000, 0x0000, 0x0000 }, /* R1529 */
1627 { 0x0000, 0x0000, 0x0000 }, /* R1530 */
1628 { 0x0000, 0x0000, 0x0000 }, /* R1531 */
1629 { 0x0000, 0x0000, 0x0000 }, /* R1532 */
1630 { 0x0000, 0x0000, 0x0000 }, /* R1533 */
1631 { 0x0000, 0x0000, 0x0000 }, /* R1534 */
1632 { 0x0000, 0x0000, 0x0000 }, /* R1535 */
1633 { 0x01EF, 0x01EF, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
1634 { 0x0037, 0x0037, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
1635 { 0x0037, 0x0037, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
1636 { 0x01EF, 0x01EF, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
1637 { 0x0037, 0x0037, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
1638 { 0x0037, 0x0037, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
1639 { 0x0003, 0x0003, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
1640 { 0x0003, 0x0003, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
1641 { 0x0003, 0x0003, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
1642 { 0x0003, 0x0003, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
1643 { 0x0000, 0x0000, 0x0000 }, /* R1546 */
1644 { 0x0000, 0x0000, 0x0000 }, /* R1547 */
1645 { 0x0000, 0x0000, 0x0000 }, /* R1548 */
1646 { 0x0000, 0x0000, 0x0000 }, /* R1549 */
1647 { 0x0000, 0x0000, 0x0000 }, /* R1550 */
1648 { 0x0000, 0x0000, 0x0000 }, /* R1551 */
1649 { 0x02FF, 0x03FF, 0x0000 }, /* R1552 - DAC1 Left Volume */
1650 { 0x02FF, 0x03FF, 0x0000 }, /* R1553 - DAC1 Right Volume */
1651 { 0x02FF, 0x03FF, 0x0000 }, /* R1554 - DAC2 Left Volume */
1652 { 0x02FF, 0x03FF, 0x0000 }, /* R1555 - DAC2 Right Volume */
1653 { 0x0003, 0x0003, 0x0000 }, /* R1556 - DAC Softmute */
1654 { 0x0000, 0x0000, 0x0000 }, /* R1557 */
1655 { 0x0000, 0x0000, 0x0000 }, /* R1558 */
1656 { 0x0000, 0x0000, 0x0000 }, /* R1559 */
1657 { 0x0000, 0x0000, 0x0000 }, /* R1560 */
1658 { 0x0000, 0x0000, 0x0000 }, /* R1561 */
1659 { 0x0000, 0x0000, 0x0000 }, /* R1562 */
1660 { 0x0000, 0x0000, 0x0000 }, /* R1563 */
1661 { 0x0000, 0x0000, 0x0000 }, /* R1564 */
1662 { 0x0000, 0x0000, 0x0000 }, /* R1565 */
1663 { 0x0000, 0x0000, 0x0000 }, /* R1566 */
1664 { 0x0000, 0x0000, 0x0000 }, /* R1567 */
1665 { 0x0003, 0x0003, 0x0000 }, /* R1568 - Oversampling */
1666 { 0x03C3, 0x03C3, 0x0000 }, /* R1569 - Sidetone */
1667};
1668
1669static int wm8994_readable(unsigned int reg)
1670{
1671 if (reg >= ARRAY_SIZE(access_masks))
1672 return 0;
1673 return access_masks[reg].readable != 0;
1674}
1675
1676static int wm8994_volatile(unsigned int reg)
1677{
1678 if (reg >= WM8994_REG_CACHE_SIZE)
1679 return 1;
1680
1681 switch (reg) {
1682 case WM8994_SOFTWARE_RESET:
1683 case WM8994_CHIP_REVISION:
1684 case WM8994_DC_SERVO_1:
1685 case WM8994_DC_SERVO_READBACK:
1686 case WM8994_RATE_STATUS:
1687 case WM8994_LDO_1:
1688 case WM8994_LDO_2:
1689 return 1;
1690 default:
1691 return 0;
1692 }
1693}
1694
1695static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
1696 unsigned int value)
1697{
1698 struct wm8994_priv *wm8994 = codec->private_data;
1699
1700 BUG_ON(reg > WM8994_MAX_REGISTER);
1701
1702 if (!wm8994_volatile(reg))
1703 wm8994->reg_cache[reg] = value;
1704
1705 return wm8994_reg_write(codec->control_data, reg, value);
1706}
1707
1708static unsigned int wm8994_read(struct snd_soc_codec *codec,
1709 unsigned int reg)
1710{
1711 u16 *reg_cache = codec->reg_cache;
1712
1713 BUG_ON(reg > WM8994_MAX_REGISTER);
1714
1715 if (wm8994_volatile(reg))
1716 return wm8994_reg_read(codec->control_data, reg);
1717 else
1718 return reg_cache[reg];
1719}
1720
1721static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
1722{
1723 struct wm8994_priv *wm8994 = codec->private_data;
1724 int rate;
1725 int reg1 = 0;
1726 int offset;
1727
1728 if (aif)
1729 offset = 4;
1730 else
1731 offset = 0;
1732
1733 switch (wm8994->sysclk[aif]) {
1734 case WM8994_SYSCLK_MCLK1:
1735 rate = wm8994->mclk[0];
1736 break;
1737
1738 case WM8994_SYSCLK_MCLK2:
1739 reg1 |= 0x8;
1740 rate = wm8994->mclk[1];
1741 break;
1742
1743 case WM8994_SYSCLK_FLL1:
1744 reg1 |= 0x10;
1745 rate = wm8994->fll[0].out;
1746 break;
1747
1748 case WM8994_SYSCLK_FLL2:
1749 reg1 |= 0x18;
1750 rate = wm8994->fll[1].out;
1751 break;
1752
1753 default:
1754 return -EINVAL;
1755 }
1756
1757 if (rate >= 13500000) {
1758 rate /= 2;
1759 reg1 |= WM8994_AIF1CLK_DIV;
1760
1761 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
1762 aif + 1, rate);
1763 }
1764 wm8994->aifclk[aif] = rate;
1765
1766 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
1767 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
1768 reg1);
1769
1770 return 0;
1771}
1772
1773static int configure_clock(struct snd_soc_codec *codec)
1774{
1775 struct wm8994_priv *wm8994 = codec->private_data;
1776 int old, new;
1777
1778 /* Bring up the AIF clocks first */
1779 configure_aif_clock(codec, 0);
1780 configure_aif_clock(codec, 1);
1781
1782 /* Then switch CLK_SYS over to the higher of them; a change
1783 * can only happen as a result of a clocking change which can
1784 * only be made outside of DAPM so we can safely redo the
1785 * clocking.
1786 */
1787
1788 /* If they're equal it doesn't matter which is used */
1789 if (wm8994->aifclk[0] == wm8994->aifclk[1])
1790 return 0;
1791
1792 if (wm8994->aifclk[0] < wm8994->aifclk[1])
1793 new = WM8994_SYSCLK_SRC;
1794 else
1795 new = 0;
1796
1797 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
1798
1799 /* If there's no change then we're done. */
1800 if (old == new)
1801 return 0;
1802
1803 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
1804
1805 snd_soc_dapm_sync(codec);
1806
1807 return 0;
1808}
1809
1810static int check_clk_sys(struct snd_soc_dapm_widget *source,
1811 struct snd_soc_dapm_widget *sink)
1812{
1813 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
1814 const char *clk;
1815
1816 /* Check what we're currently using for CLK_SYS */
1817 if (reg & WM8994_SYSCLK_SRC)
1818 clk = "AIF2CLK";
1819 else
1820 clk = "AIF1CLK";
1821
1822 return strcmp(source->name, clk) == 0;
1823}
1824
1825static const char *sidetone_hpf_text[] = {
1826 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
1827};
1828
1829static const struct soc_enum sidetone_hpf =
1830 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
1831
1832static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
1833static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1834static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1835static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
1836static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1837
1838#define WM8994_DRC_SWITCH(xname, reg, shift) \
1839{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1840 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
1841 .put = wm8994_put_drc_sw, \
1842 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
1843
1844static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
1845 struct snd_ctl_elem_value *ucontrol)
1846{
1847 struct soc_mixer_control *mc =
1848 (struct soc_mixer_control *)kcontrol->private_value;
1849 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1850 int mask, ret;
1851
1852 /* Can't enable both ADC and DAC paths simultaneously */
1853 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
1854 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
1855 WM8994_AIF1ADC1R_DRC_ENA_MASK;
1856 else
1857 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
1858
1859 ret = snd_soc_read(codec, mc->reg);
1860 if (ret < 0)
1861 return ret;
1862 if (ret & mask)
1863 return -EINVAL;
1864
1865 return snd_soc_put_volsw(kcontrol, ucontrol);
1866}
1867
1868
1869
1870static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
1871{
1872 struct wm8994_priv *wm8994 = codec->private_data;
1873 struct wm8994_pdata *pdata = wm8994->pdata;
1874 int base = wm8994_drc_base[drc];
1875 int cfg = wm8994->drc_cfg[drc];
1876 int save, i;
1877
1878 /* Save any enables; the configuration should clear them. */
1879 save = snd_soc_read(codec, base);
1880 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
1881 WM8994_AIF1ADC1R_DRC_ENA;
1882
1883 for (i = 0; i < WM8994_DRC_REGS; i++)
1884 snd_soc_update_bits(codec, base + i, 0xffff,
1885 pdata->drc_cfgs[cfg].regs[i]);
1886
1887 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
1888 WM8994_AIF1ADC1L_DRC_ENA |
1889 WM8994_AIF1ADC1R_DRC_ENA, save);
1890}
1891
1892/* Icky as hell but saves code duplication */
1893static int wm8994_get_drc(const char *name)
1894{
1895 if (strcmp(name, "AIF1DRC1 Mode") == 0)
1896 return 0;
1897 if (strcmp(name, "AIF1DRC2 Mode") == 0)
1898 return 1;
1899 if (strcmp(name, "AIF2DRC Mode") == 0)
1900 return 2;
1901 return -EINVAL;
1902}
1903
1904static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
1905 struct snd_ctl_elem_value *ucontrol)
1906{
1907 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1908 struct wm8994_priv *wm8994 = codec->private_data;
1909 struct wm8994_pdata *pdata = wm8994->pdata;
1910 int drc = wm8994_get_drc(kcontrol->id.name);
1911 int value = ucontrol->value.integer.value[0];
1912
1913 if (drc < 0)
1914 return drc;
1915
1916 if (value >= pdata->num_drc_cfgs)
1917 return -EINVAL;
1918
1919 wm8994->drc_cfg[drc] = value;
1920
1921 wm8994_set_drc(codec, drc);
1922
1923 return 0;
1924}
1925
1926static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
1927 struct snd_ctl_elem_value *ucontrol)
1928{
1929 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1930 struct wm8994_priv *wm8994 = codec->private_data;
1931 int drc = wm8994_get_drc(kcontrol->id.name);
1932
1933 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
1934
1935 return 0;
1936}
1937
1938static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
1939{
1940 struct wm8994_priv *wm8994 = codec->private_data;
1941 struct wm8994_pdata *pdata = wm8994->pdata;
1942 int base = wm8994_retune_mobile_base[block];
1943 int iface, best, best_val, save, i, cfg;
1944
1945 if (!pdata || !wm8994->num_retune_mobile_texts)
1946 return;
1947
1948 switch (block) {
1949 case 0:
1950 case 1:
1951 iface = 0;
1952 break;
1953 case 2:
1954 iface = 1;
1955 break;
1956 default:
1957 return;
1958 }
1959
1960 /* Find the version of the currently selected configuration
1961 * with the nearest sample rate. */
1962 cfg = wm8994->retune_mobile_cfg[block];
1963 best = 0;
1964 best_val = INT_MAX;
1965 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
1966 if (strcmp(pdata->retune_mobile_cfgs[i].name,
1967 wm8994->retune_mobile_texts[cfg]) == 0 &&
1968 abs(pdata->retune_mobile_cfgs[i].rate
1969 - wm8994->dac_rates[iface]) < best_val) {
1970 best = i;
1971 best_val = abs(pdata->retune_mobile_cfgs[i].rate
1972 - wm8994->dac_rates[iface]);
1973 }
1974 }
1975
1976 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
1977 block,
1978 pdata->retune_mobile_cfgs[best].name,
1979 pdata->retune_mobile_cfgs[best].rate,
1980 wm8994->dac_rates[iface]);
1981
1982 /* The EQ will be disabled while reconfiguring it, remember the
1983 * current configuration.
1984 */
1985 save = snd_soc_read(codec, base);
1986 save &= WM8994_AIF1DAC1_EQ_ENA;
1987
1988 for (i = 0; i < WM8994_EQ_REGS; i++)
1989 snd_soc_update_bits(codec, base + i, 0xffff,
1990 pdata->retune_mobile_cfgs[best].regs[i]);
1991
1992 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
1993}
1994
1995/* Icky as hell but saves code duplication */
1996static int wm8994_get_retune_mobile_block(const char *name)
1997{
1998 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
1999 return 0;
2000 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
2001 return 1;
2002 if (strcmp(name, "AIF2 EQ Mode") == 0)
2003 return 2;
2004 return -EINVAL;
2005}
2006
2007static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
2008 struct snd_ctl_elem_value *ucontrol)
2009{
2010 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2011 struct wm8994_priv *wm8994 = codec->private_data;
2012 struct wm8994_pdata *pdata = wm8994->pdata;
2013 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
2014 int value = ucontrol->value.integer.value[0];
2015
2016 if (block < 0)
2017 return block;
2018
2019 if (value >= pdata->num_retune_mobile_cfgs)
2020 return -EINVAL;
2021
2022 wm8994->retune_mobile_cfg[block] = value;
2023
2024 wm8994_set_retune_mobile(codec, block);
2025
2026 return 0;
2027}
2028
2029static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
2030 struct snd_ctl_elem_value *ucontrol)
2031{
2032 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2033 struct wm8994_priv *wm8994 = codec->private_data;
2034 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
2035
2036 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
2037
2038 return 0;
2039}
2040
2041static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2042SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
2043 WM8994_AIF1_ADC1_RIGHT_VOLUME,
2044 1, 119, 0, digital_tlv),
2045SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
2046 WM8994_AIF1_ADC2_RIGHT_VOLUME,
2047 1, 119, 0, digital_tlv),
2048SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
2049 WM8994_AIF2_ADC_RIGHT_VOLUME,
2050 1, 119, 0, digital_tlv),
2051
2052SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
2053 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2054SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
2055 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2056SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
2057 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2058
2059SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
2060SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
2061
2062SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
2063SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
2064SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
2065
2066WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
2067WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
2068WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
2069
2070WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
2071WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
2072WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
2073
2074WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
2075WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
2076WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
2077
2078SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
2079 5, 12, 0, st_tlv),
2080SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
2081 0, 12, 0, st_tlv),
2082SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
2083 5, 12, 0, st_tlv),
2084SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
2085 0, 12, 0, st_tlv),
2086SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
2087SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
2088
2089SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
2090 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2091SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
2092 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
2093
2094SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
2095 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2096SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
2097 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
2098
2099SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
2100 6, 1, 1, wm_hubs_spkmix_tlv),
2101SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
2102 2, 1, 1, wm_hubs_spkmix_tlv),
2103
2104SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
2105 6, 1, 1, wm_hubs_spkmix_tlv),
2106SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
2107 2, 1, 1, wm_hubs_spkmix_tlv),
2108
2109SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
2110 10, 15, 0, wm8994_3d_tlv),
2111SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2112 8, 1, 0),
2113SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
2114 10, 15, 0, wm8994_3d_tlv),
2115SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2116 8, 1, 0),
2117SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
2118 10, 15, 0, wm8994_3d_tlv),
2119SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2120 8, 1, 0),
2121};
2122
2123static const struct snd_kcontrol_new wm8994_eq_controls[] = {
2124SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
2125 eq_tlv),
2126SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
2127 eq_tlv),
2128SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
2129 eq_tlv),
2130SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
2131 eq_tlv),
2132SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
2133 eq_tlv),
2134
2135SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
2136 eq_tlv),
2137SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
2138 eq_tlv),
2139SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
2140 eq_tlv),
2141SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
2142 eq_tlv),
2143SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
2144 eq_tlv),
2145
2146SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
2147 eq_tlv),
2148SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
2149 eq_tlv),
2150SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
2151 eq_tlv),
2152SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
2153 eq_tlv),
2154SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
2155 eq_tlv),
2156};
2157
2158static int clk_sys_event(struct snd_soc_dapm_widget *w,
2159 struct snd_kcontrol *kcontrol, int event)
2160{
2161 struct snd_soc_codec *codec = w->codec;
2162
2163 switch (event) {
2164 case SND_SOC_DAPM_PRE_PMU:
2165 return configure_clock(codec);
2166
2167 case SND_SOC_DAPM_POST_PMD:
2168 configure_clock(codec);
2169 break;
2170 }
2171
2172 return 0;
2173}
2174
2175static void wm8994_update_class_w(struct snd_soc_codec *codec)
2176{
2177 int enable = 1;
2178 int source = 0; /* GCC flow analysis can't track enable */
2179 int reg, reg_r;
2180
2181 /* Only support direct DAC->headphone paths */
2182 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
2183 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
2184 dev_dbg(codec->dev, "HPL connected to output mixer\n");
2185 enable = 0;
2186 }
2187
2188 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
2189 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
2190 dev_dbg(codec->dev, "HPR connected to output mixer\n");
2191 enable = 0;
2192 }
2193
2194 /* We also need the same setting for L/R and only one path */
2195 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
2196 switch (reg) {
2197 case WM8994_AIF2DACL_TO_DAC1L:
2198 dev_dbg(codec->dev, "Class W source AIF2DAC\n");
2199 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
2200 break;
2201 case WM8994_AIF1DAC2L_TO_DAC1L:
2202 dev_dbg(codec->dev, "Class W source AIF1DAC2\n");
2203 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
2204 break;
2205 case WM8994_AIF1DAC1L_TO_DAC1L:
2206 dev_dbg(codec->dev, "Class W source AIF1DAC1\n");
2207 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
2208 break;
2209 default:
2210 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg);
2211 enable = 0;
2212 break;
2213 }
2214
2215 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
2216 if (reg_r != reg) {
2217 dev_dbg(codec->dev, "Left and right DAC mixers different\n");
2218 enable = 0;
2219 }
2220
2221 if (enable) {
2222 dev_dbg(codec->dev, "Class W enabled\n");
2223 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
2224 WM8994_CP_DYN_PWR |
2225 WM8994_CP_DYN_SRC_SEL_MASK,
2226 source | WM8994_CP_DYN_PWR);
2227
2228 } else {
2229 dev_dbg(codec->dev, "Class W disabled\n");
2230 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
2231 WM8994_CP_DYN_PWR, 0);
2232 }
2233}
2234
2235static const char *hp_mux_text[] = {
2236 "Mixer",
2237 "DAC",
2238};
2239
2240#define WM8994_HP_ENUM(xname, xenum) \
2241{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2242 .info = snd_soc_info_enum_double, \
2243 .get = snd_soc_dapm_get_enum_double, \
2244 .put = wm8994_put_hp_enum, \
2245 .private_value = (unsigned long)&xenum }
2246
2247static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
2248 struct snd_ctl_elem_value *ucontrol)
2249{
2250 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
2251 struct snd_soc_codec *codec = w->codec;
2252 int ret;
2253
2254 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
2255
2256 wm8994_update_class_w(codec);
2257
2258 return ret;
2259}
2260
2261static const struct soc_enum hpl_enum =
2262 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
2263
2264static const struct snd_kcontrol_new hpl_mux =
2265 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
2266
2267static const struct soc_enum hpr_enum =
2268 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
2269
2270static const struct snd_kcontrol_new hpr_mux =
2271 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
2272
2273static const char *adc_mux_text[] = {
2274 "ADC",
2275 "DMIC",
2276};
2277
2278static const struct soc_enum adc_enum =
2279 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
2280
2281static const struct snd_kcontrol_new adcl_mux =
2282 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
2283
2284static const struct snd_kcontrol_new adcr_mux =
2285 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
2286
2287static const struct snd_kcontrol_new left_speaker_mixer[] = {
2288SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
2289SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
2290SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
2291SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
2292SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
2293};
2294
2295static const struct snd_kcontrol_new right_speaker_mixer[] = {
2296SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
2297SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
2298SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
2299SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
2300SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
2301};
2302
2303/* Debugging; dump chip status after DAPM transitions */
2304static int post_ev(struct snd_soc_dapm_widget *w,
2305 struct snd_kcontrol *kcontrol, int event)
2306{
2307 struct snd_soc_codec *codec = w->codec;
2308 dev_dbg(codec->dev, "SRC status: %x\n",
2309 snd_soc_read(codec,
2310 WM8994_RATE_STATUS));
2311 return 0;
2312}
2313
2314static const struct snd_kcontrol_new aif1adc1l_mix[] = {
2315SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
2316 1, 1, 0),
2317SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
2318 0, 1, 0),
2319};
2320
2321static const struct snd_kcontrol_new aif1adc1r_mix[] = {
2322SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
2323 1, 1, 0),
2324SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
2325 0, 1, 0),
2326};
2327
2328static const struct snd_kcontrol_new aif2dac2l_mix[] = {
2329SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2330 5, 1, 0),
2331SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2332 4, 1, 0),
2333SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2334 2, 1, 0),
2335SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2336 1, 1, 0),
2337SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2338 0, 1, 0),
2339};
2340
2341static const struct snd_kcontrol_new aif2dac2r_mix[] = {
2342SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2343 5, 1, 0),
2344SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2345 4, 1, 0),
2346SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2347 2, 1, 0),
2348SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2349 1, 1, 0),
2350SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2351 0, 1, 0),
2352};
2353
2354#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
2355{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2356 .info = snd_soc_info_volsw, \
2357 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
2358 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
2359
2360static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
2361 struct snd_ctl_elem_value *ucontrol)
2362{
2363 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
2364 struct snd_soc_codec *codec = w->codec;
2365 int ret;
2366
2367 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
2368
2369 wm8994_update_class_w(codec);
2370
2371 return ret;
2372}
2373
2374static const struct snd_kcontrol_new dac1l_mix[] = {
2375WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2376 5, 1, 0),
2377WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2378 4, 1, 0),
2379WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2380 2, 1, 0),
2381WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2382 1, 1, 0),
2383WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2384 0, 1, 0),
2385};
2386
2387static const struct snd_kcontrol_new dac1r_mix[] = {
2388WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2389 5, 1, 0),
2390WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2391 4, 1, 0),
2392WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2393 2, 1, 0),
2394WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2395 1, 1, 0),
2396WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2397 0, 1, 0),
2398};
2399
2400static const char *sidetone_text[] = {
2401 "ADC/DMIC1", "DMIC2",
2402};
2403
2404static const struct soc_enum sidetone1_enum =
2405 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
2406
2407static const struct snd_kcontrol_new sidetone1_mux =
2408 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
2409
2410static const struct soc_enum sidetone2_enum =
2411 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
2412
2413static const struct snd_kcontrol_new sidetone2_mux =
2414 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
2415
2416static const char *aif1dac_text[] = {
2417 "AIF1DACDAT", "AIF3DACDAT",
2418};
2419
2420static const struct soc_enum aif1dac_enum =
2421 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
2422
2423static const struct snd_kcontrol_new aif1dac_mux =
2424 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
2425
2426static const char *aif2dac_text[] = {
2427 "AIF2DACDAT", "AIF3DACDAT",
2428};
2429
2430static const struct soc_enum aif2dac_enum =
2431 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
2432
2433static const struct snd_kcontrol_new aif2dac_mux =
2434 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
2435
2436static const char *aif2adc_text[] = {
2437 "AIF2ADCDAT", "AIF3DACDAT",
2438};
2439
2440static const struct soc_enum aif2adc_enum =
2441 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
2442
2443static const struct snd_kcontrol_new aif2adc_mux =
2444 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
2445
2446static const char *aif3adc_text[] = {
2447 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT",
2448};
2449
2450static const struct soc_enum aif3adc_enum =
2451 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
2452
2453static const struct snd_kcontrol_new aif3adc_mux =
2454 SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum);
2455
2456static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
2457SND_SOC_DAPM_INPUT("DMIC1DAT"),
2458SND_SOC_DAPM_INPUT("DMIC2DAT"),
2459
2460SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
2461 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2462
2463SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
2464SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
2465SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
2466
2467SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
2468SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
2469
2470SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
2471 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
2472SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
2473 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
2474SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0,
2475 WM8994_POWER_MANAGEMENT_5, 9, 0),
2476SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0,
2477 WM8994_POWER_MANAGEMENT_5, 8, 0),
2478
2479SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
2480 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
2481SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
2482 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
2483SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0,
2484 WM8994_POWER_MANAGEMENT_5, 11, 0),
2485SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0,
2486 WM8994_POWER_MANAGEMENT_5, 10, 0),
2487
2488SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
2489 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
2490SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
2491 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
2492
2493SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
2494 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
2495SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
2496 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
2497
2498SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
2499SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
2500
2501SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
2502 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
2503SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
2504 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
2505
2506SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
2507 WM8994_POWER_MANAGEMENT_4, 13, 0),
2508SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
2509 WM8994_POWER_MANAGEMENT_4, 12, 0),
2510SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0,
2511 WM8994_POWER_MANAGEMENT_5, 13, 0),
2512SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0,
2513 WM8994_POWER_MANAGEMENT_5, 12, 0),
2514
2515SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2516SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2517SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2518
2519SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
2520SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
2521SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
2522SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
2523
2524SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2525SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2526
2527SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
2528
2529SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
2530SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
2531SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
2532SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
2533
2534/* Power is done with the muxes since the ADC power also controls the
2535 * downsampling chain, the chip will automatically manage the analogue
2536 * specific portions.
2537 */
2538SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
2539SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
2540
2541SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
2542SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
2543
2544SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
2545SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
2546SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
2547SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
2548
2549SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
2550SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
2551
2552SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
2553 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
2554SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
2555 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
2556
2557SND_SOC_DAPM_POST("Debug log", post_ev),
2558};
2559
2560static const struct snd_soc_dapm_route intercon[] = {
2561
2562 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
2563 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
2564
2565 { "DSP1CLK", NULL, "CLK_SYS" },
2566 { "DSP2CLK", NULL, "CLK_SYS" },
2567 { "DSPINTCLK", NULL, "CLK_SYS" },
2568
2569 { "AIF1ADC1L", NULL, "AIF1CLK" },
2570 { "AIF1ADC1L", NULL, "DSP1CLK" },
2571 { "AIF1ADC1R", NULL, "AIF1CLK" },
2572 { "AIF1ADC1R", NULL, "DSP1CLK" },
2573 { "AIF1ADC1R", NULL, "DSPINTCLK" },
2574
2575 { "AIF1DAC1L", NULL, "AIF1CLK" },
2576 { "AIF1DAC1L", NULL, "DSP1CLK" },
2577 { "AIF1DAC1R", NULL, "AIF1CLK" },
2578 { "AIF1DAC1R", NULL, "DSP1CLK" },
2579 { "AIF1DAC1R", NULL, "DSPINTCLK" },
2580
2581 { "AIF1ADC2L", NULL, "AIF1CLK" },
2582 { "AIF1ADC2L", NULL, "DSP1CLK" },
2583 { "AIF1ADC2R", NULL, "AIF1CLK" },
2584 { "AIF1ADC2R", NULL, "DSP1CLK" },
2585 { "AIF1ADC2R", NULL, "DSPINTCLK" },
2586
2587 { "AIF1DAC2L", NULL, "AIF1CLK" },
2588 { "AIF1DAC2L", NULL, "DSP1CLK" },
2589 { "AIF1DAC2R", NULL, "AIF1CLK" },
2590 { "AIF1DAC2R", NULL, "DSP1CLK" },
2591 { "AIF1DAC2R", NULL, "DSPINTCLK" },
2592
2593 { "AIF2ADCL", NULL, "AIF2CLK" },
2594 { "AIF2ADCL", NULL, "DSP2CLK" },
2595 { "AIF2ADCR", NULL, "AIF2CLK" },
2596 { "AIF2ADCR", NULL, "DSP2CLK" },
2597 { "AIF2ADCR", NULL, "DSPINTCLK" },
2598
2599 { "AIF2DACL", NULL, "AIF2CLK" },
2600 { "AIF2DACL", NULL, "DSP2CLK" },
2601 { "AIF2DACR", NULL, "AIF2CLK" },
2602 { "AIF2DACR", NULL, "DSP2CLK" },
2603 { "AIF2DACR", NULL, "DSPINTCLK" },
2604
2605 { "DMIC1L", NULL, "DMIC1DAT" },
2606 { "DMIC1L", NULL, "CLK_SYS" },
2607 { "DMIC1R", NULL, "DMIC1DAT" },
2608 { "DMIC1R", NULL, "CLK_SYS" },
2609 { "DMIC2L", NULL, "DMIC2DAT" },
2610 { "DMIC2L", NULL, "CLK_SYS" },
2611 { "DMIC2R", NULL, "DMIC2DAT" },
2612 { "DMIC2R", NULL, "CLK_SYS" },
2613
2614 { "ADCL", NULL, "AIF1CLK" },
2615 { "ADCL", NULL, "DSP1CLK" },
2616 { "ADCL", NULL, "DSPINTCLK" },
2617
2618 { "ADCR", NULL, "AIF1CLK" },
2619 { "ADCR", NULL, "DSP1CLK" },
2620 { "ADCR", NULL, "DSPINTCLK" },
2621
2622 { "ADCL Mux", "ADC", "ADCL" },
2623 { "ADCL Mux", "DMIC", "DMIC1L" },
2624 { "ADCR Mux", "ADC", "ADCR" },
2625 { "ADCR Mux", "DMIC", "DMIC1R" },
2626
2627 { "DAC1L", NULL, "AIF1CLK" },
2628 { "DAC1L", NULL, "DSP1CLK" },
2629 { "DAC1L", NULL, "DSPINTCLK" },
2630
2631 { "DAC1R", NULL, "AIF1CLK" },
2632 { "DAC1R", NULL, "DSP1CLK" },
2633 { "DAC1R", NULL, "DSPINTCLK" },
2634
2635 { "DAC2L", NULL, "AIF2CLK" },
2636 { "DAC2L", NULL, "DSP2CLK" },
2637 { "DAC2L", NULL, "DSPINTCLK" },
2638
2639 { "DAC2R", NULL, "AIF2DACR" },
2640 { "DAC2R", NULL, "AIF2CLK" },
2641 { "DAC2R", NULL, "DSP2CLK" },
2642 { "DAC2R", NULL, "DSPINTCLK" },
2643
2644 { "TOCLK", NULL, "CLK_SYS" },
2645
2646 /* AIF1 outputs */
2647 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
2648 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
2649 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
2650
2651 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
2652 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
2653 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
2654
2655 /* Pin level routing for AIF3 */
2656 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
2657 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
2658 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
2659 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
2660
2661 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2662 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2663
2664 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
2665 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
2666 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
2667 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
2668 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
2669 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
2670 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
2671
2672 /* DAC1 inputs */
2673 { "DAC1L", NULL, "DAC1L Mixer" },
2674 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
2675 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
2676 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
2677 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
2678 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
2679
2680 { "DAC1R", NULL, "DAC1R Mixer" },
2681 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
2682 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
2683 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
2684 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
2685 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
2686
2687 /* DAC2/AIF2 outputs */
2688 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
2689 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
2690 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
2691 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
2692 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
2693 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
2694 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
2695
2696 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
2697 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
2698 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
2699 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
2700 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
2701 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
2702 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
2703
2704 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
2705
2706 /* AIF3 output */
2707 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
2708 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
2709 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
2710 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
2711 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
2712 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
2713 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
2714 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
2715
2716 /* Sidetone */
2717 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
2718 { "Left Sidetone", "DMIC2", "DMIC2L" },
2719 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
2720 { "Right Sidetone", "DMIC2", "DMIC2R" },
2721
2722 /* Output stages */
2723 { "Left Output Mixer", "DAC Switch", "DAC1L" },
2724 { "Right Output Mixer", "DAC Switch", "DAC1R" },
2725
2726 { "SPKL", "DAC1 Switch", "DAC1L" },
2727 { "SPKL", "DAC2 Switch", "DAC2L" },
2728
2729 { "SPKR", "DAC1 Switch", "DAC1R" },
2730 { "SPKR", "DAC2 Switch", "DAC2R" },
2731
2732 { "Left Headphone Mux", "DAC", "DAC1L" },
2733 { "Right Headphone Mux", "DAC", "DAC1R" },
2734};
2735
2736/* The size in bits of the FLL divide multiplied by 10
2737 * to allow rounding later */
2738#define FIXED_FLL_SIZE ((1 << 16) * 10)
2739
2740struct fll_div {
2741 u16 outdiv;
2742 u16 n;
2743 u16 k;
2744 u16 clk_ref_div;
2745 u16 fll_fratio;
2746};
2747
2748static int wm8994_get_fll_config(struct fll_div *fll,
2749 int freq_in, int freq_out)
2750{
2751 u64 Kpart;
2752 unsigned int K, Ndiv, Nmod;
2753
2754 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2755
2756 /* Scale the input frequency down to <= 13.5MHz */
2757 fll->clk_ref_div = 0;
2758 while (freq_in > 13500000) {
2759 fll->clk_ref_div++;
2760 freq_in /= 2;
2761
2762 if (fll->clk_ref_div > 3)
2763 return -EINVAL;
2764 }
2765 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2766
2767 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2768 fll->outdiv = 3;
2769 while (freq_out * (fll->outdiv + 1) < 90000000) {
2770 fll->outdiv++;
2771 if (fll->outdiv > 63)
2772 return -EINVAL;
2773 }
2774 freq_out *= fll->outdiv + 1;
2775 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2776
2777 if (freq_in > 1000000) {
2778 fll->fll_fratio = 0;
2779 } else {
2780 fll->fll_fratio = 3;
2781 freq_in *= 8;
2782 }
2783 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2784
2785 /* Now, calculate N.K */
2786 Ndiv = freq_out / freq_in;
2787
2788 fll->n = Ndiv;
2789 Nmod = freq_out % freq_in;
2790 pr_debug("Nmod=%d\n", Nmod);
2791
2792 /* Calculate fractional part - scale up so we can round. */
2793 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2794
2795 do_div(Kpart, freq_in);
2796
2797 K = Kpart & 0xFFFFFFFF;
2798
2799 if ((K % 10) >= 5)
2800 K += 5;
2801
2802 /* Move down to proper range now rounding is done */
2803 fll->k = K / 10;
2804
2805 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2806
2807 return 0;
2808}
2809
2810static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2811 unsigned int freq_in, unsigned int freq_out)
2812{
2813 struct snd_soc_codec *codec = dai->codec;
2814 struct wm8994_priv *wm8994 = codec->private_data;
2815 int reg_offset, ret;
2816 struct fll_div fll;
2817 u16 reg, aif1, aif2;
2818
2819 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
2820 & WM8994_AIF1CLK_ENA;
2821
2822 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
2823 & WM8994_AIF2CLK_ENA;
2824
2825 switch (id) {
2826 case WM8994_FLL1:
2827 reg_offset = 0;
2828 id = 0;
2829 break;
2830 case WM8994_FLL2:
2831 reg_offset = 0x20;
2832 id = 1;
2833 break;
2834 default:
2835 return -EINVAL;
2836 }
2837
2838 /* Are we changing anything? */
2839 if (wm8994->fll[id].src == src &&
2840 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2841 return 0;
2842
2843 /* If we're stopping the FLL redo the old config - no
2844 * registers will actually be written but we avoid GCC flow
2845 * analysis bugs spewing warnings.
2846 */
2847 if (freq_out)
2848 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2849 else
2850 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2851 wm8994->fll[id].out);
2852 if (ret < 0)
2853 return ret;
2854
2855 /* Gate the AIF clocks while we reclock */
2856 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2857 WM8994_AIF1CLK_ENA, 0);
2858 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2859 WM8994_AIF2CLK_ENA, 0);
2860
2861 /* We always need to disable the FLL while reconfiguring */
2862 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2863 WM8994_FLL1_ENA, 0);
2864
2865 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2866 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2867 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2868 WM8994_FLL1_OUTDIV_MASK |
2869 WM8994_FLL1_FRATIO_MASK, reg);
2870
2871 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
2872
2873 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2874 WM8994_FLL1_N_MASK,
2875 fll.n << WM8994_FLL1_N_SHIFT);
2876
2877 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2878 WM8994_FLL1_REFCLK_DIV_MASK,
2879 fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT);
2880
2881 /* Enable (with fractional mode if required) */
2882 if (freq_out) {
2883 if (fll.k)
2884 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2885 else
2886 reg = WM8994_FLL1_ENA;
2887 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2888 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2889 reg);
2890 }
2891
2892 wm8994->fll[id].in = freq_in;
2893 wm8994->fll[id].out = freq_out;
2894
2895 /* Enable any gated AIF clocks */
2896 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2897 WM8994_AIF1CLK_ENA, aif1);
2898 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2899 WM8994_AIF2CLK_ENA, aif2);
2900
2901 configure_clock(codec);
2902
2903 return 0;
2904}
2905
2906static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2907 int clk_id, unsigned int freq, int dir)
2908{
2909 struct snd_soc_codec *codec = dai->codec;
2910 struct wm8994_priv *wm8994 = codec->private_data;
2911
2912 switch (dai->id) {
2913 case 1:
2914 case 2:
2915 break;
2916
2917 default:
2918 /* AIF3 shares clocking with AIF1/2 */
2919 return -EINVAL;
2920 }
2921
2922 switch (clk_id) {
2923 case WM8994_SYSCLK_MCLK1:
2924 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2925 wm8994->mclk[0] = freq;
2926 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2927 dai->id, freq);
2928 break;
2929
2930 case WM8994_SYSCLK_MCLK2:
2931 /* TODO: Set GPIO AF */
2932 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2933 wm8994->mclk[1] = freq;
2934 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2935 dai->id, freq);
2936 break;
2937
2938 case WM8994_SYSCLK_FLL1:
2939 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2940 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2941 break;
2942
2943 case WM8994_SYSCLK_FLL2:
2944 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2945 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2946 break;
2947
2948 default:
2949 return -EINVAL;
2950 }
2951
2952 configure_clock(codec);
2953
2954 return 0;
2955}
2956
2957static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2958 enum snd_soc_bias_level level)
2959{
2960 switch (level) {
2961 case SND_SOC_BIAS_ON:
2962 break;
2963
2964 case SND_SOC_BIAS_PREPARE:
2965 /* VMID=2x40k */
2966 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2967 WM8994_VMID_SEL_MASK, 0x2);
2968 break;
2969
2970 case SND_SOC_BIAS_STANDBY:
2971 if (codec->bias_level == SND_SOC_BIAS_OFF) {
2972 /* Tweak DC servo configuration for improved
2973 * performance. */
2974 snd_soc_write(codec, 0x102, 0x3);
2975 snd_soc_write(codec, 0x56, 0x3);
2976 snd_soc_write(codec, 0x102, 0);
2977
2978 /* Discharge LINEOUT1 & 2 */
2979 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2980 WM8994_LINEOUT1_DISCH |
2981 WM8994_LINEOUT2_DISCH,
2982 WM8994_LINEOUT1_DISCH |
2983 WM8994_LINEOUT2_DISCH);
2984
2985 /* Startup bias, VMID ramp & buffer */
2986 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2987 WM8994_STARTUP_BIAS_ENA |
2988 WM8994_VMID_BUF_ENA |
2989 WM8994_VMID_RAMP_MASK,
2990 WM8994_STARTUP_BIAS_ENA |
2991 WM8994_VMID_BUF_ENA |
2992 (0x11 << WM8994_VMID_RAMP_SHIFT));
2993
2994 /* Main bias enable, VMID=2x40k */
2995 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2996 WM8994_BIAS_ENA |
2997 WM8994_VMID_SEL_MASK,
2998 WM8994_BIAS_ENA | 0x2);
2999
3000 msleep(20);
3001 }
3002
3003 /* VMID=2x500k */
3004 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
3005 WM8994_VMID_SEL_MASK, 0x4);
3006
3007 break;
3008
3009 case SND_SOC_BIAS_OFF:
3010 /* Switch over to startup biases */
3011 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3012 WM8994_BIAS_SRC | WM8994_STARTUP_BIAS_ENA |
3013 WM8994_VMID_BUF_ENA |
3014 WM8994_VMID_RAMP_MASK,
3015 WM8994_BIAS_SRC | WM8994_STARTUP_BIAS_ENA |
3016 WM8994_VMID_BUF_ENA |
3017 (1 << WM8994_VMID_RAMP_SHIFT));
3018
3019 /* Disable main biases */
3020 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
3021 WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
3022
3023 /* Discharge line */
3024 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
3025 WM8994_LINEOUT1_DISCH |
3026 WM8994_LINEOUT2_DISCH,
3027 WM8994_LINEOUT1_DISCH |
3028 WM8994_LINEOUT2_DISCH);
3029
3030 msleep(5);
3031
3032 /* Switch off startup biases */
3033 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3034 WM8994_BIAS_SRC | WM8994_STARTUP_BIAS_ENA |
3035 WM8994_VMID_BUF_ENA |
3036 WM8994_VMID_RAMP_MASK, 0);
3037
3038 break;
3039 }
3040 codec->bias_level = level;
3041 return 0;
3042}
3043
3044static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3045{
3046 struct snd_soc_codec *codec = dai->codec;
3047 int ms_reg;
3048 int aif1_reg;
3049 int ms = 0;
3050 int aif1 = 0;
3051
3052 switch (dai->id) {
3053 case 1:
3054 ms_reg = WM8994_AIF1_MASTER_SLAVE;
3055 aif1_reg = WM8994_AIF1_CONTROL_1;
3056 break;
3057 case 2:
3058 ms_reg = WM8994_AIF2_MASTER_SLAVE;
3059 aif1_reg = WM8994_AIF2_CONTROL_1;
3060 break;
3061 default:
3062 return -EINVAL;
3063 }
3064
3065 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3066 case SND_SOC_DAIFMT_CBS_CFS:
3067 break;
3068 case SND_SOC_DAIFMT_CBM_CFM:
3069 ms = WM8994_AIF1_MSTR;
3070 break;
3071 default:
3072 return -EINVAL;
3073 }
3074
3075 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3076 case SND_SOC_DAIFMT_DSP_B:
3077 aif1 |= WM8994_AIF1_LRCLK_INV;
3078 case SND_SOC_DAIFMT_DSP_A:
3079 aif1 |= 0x18;
3080 break;
3081 case SND_SOC_DAIFMT_I2S:
3082 aif1 |= 0x10;
3083 break;
3084 case SND_SOC_DAIFMT_RIGHT_J:
3085 break;
3086 case SND_SOC_DAIFMT_LEFT_J:
3087 aif1 |= 0x8;
3088 break;
3089 default:
3090 return -EINVAL;
3091 }
3092
3093 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3094 case SND_SOC_DAIFMT_DSP_A:
3095 case SND_SOC_DAIFMT_DSP_B:
3096 /* frame inversion not valid for DSP modes */
3097 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3098 case SND_SOC_DAIFMT_NB_NF:
3099 break;
3100 case SND_SOC_DAIFMT_IB_NF:
3101 aif1 |= WM8994_AIF1_BCLK_INV;
3102 break;
3103 default:
3104 return -EINVAL;
3105 }
3106 break;
3107
3108 case SND_SOC_DAIFMT_I2S:
3109 case SND_SOC_DAIFMT_RIGHT_J:
3110 case SND_SOC_DAIFMT_LEFT_J:
3111 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3112 case SND_SOC_DAIFMT_NB_NF:
3113 break;
3114 case SND_SOC_DAIFMT_IB_IF:
3115 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
3116 break;
3117 case SND_SOC_DAIFMT_IB_NF:
3118 aif1 |= WM8994_AIF1_BCLK_INV;
3119 break;
3120 case SND_SOC_DAIFMT_NB_IF:
3121 aif1 |= WM8994_AIF1_LRCLK_INV;
3122 break;
3123 default:
3124 return -EINVAL;
3125 }
3126 break;
3127 default:
3128 return -EINVAL;
3129 }
3130
3131 snd_soc_update_bits(codec, aif1_reg,
3132 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
3133 WM8994_AIF1_FMT_MASK,
3134 aif1);
3135 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
3136 ms);
3137
3138 return 0;
3139}
3140
3141static struct {
3142 int val, rate;
3143} srs[] = {
3144 { 0, 8000 },
3145 { 1, 11025 },
3146 { 2, 12000 },
3147 { 3, 16000 },
3148 { 4, 22050 },
3149 { 5, 24000 },
3150 { 6, 32000 },
3151 { 7, 44100 },
3152 { 8, 48000 },
3153 { 9, 88200 },
3154 { 10, 96000 },
3155};
3156
3157static int fs_ratios[] = {
3158 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
3159};
3160
3161static int bclk_divs[] = {
3162 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
3163 640, 880, 960, 1280, 1760, 1920
3164};
3165
3166static int wm8994_hw_params(struct snd_pcm_substream *substream,
3167 struct snd_pcm_hw_params *params,
3168 struct snd_soc_dai *dai)
3169{
3170 struct snd_soc_codec *codec = dai->codec;
3171 struct wm8994_priv *wm8994 = codec->private_data;
3172 int aif1_reg;
3173 int bclk_reg;
3174 int lrclk_reg;
3175 int rate_reg;
3176 int aif1 = 0;
3177 int bclk = 0;
3178 int lrclk = 0;
3179 int rate_val = 0;
3180 int id = dai->id - 1;
3181
3182 int i, cur_val, best_val, bclk_rate, best;
3183
3184 switch (dai->id) {
3185 case 1:
3186 aif1_reg = WM8994_AIF1_CONTROL_1;
3187 bclk_reg = WM8994_AIF1_BCLK;
3188 rate_reg = WM8994_AIF1_RATE;
3189 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
3190 wm8994->lrclk_shared[0])
3191 lrclk_reg = WM8994_AIF1DAC_LRCLK;
3192 else
3193 lrclk_reg = WM8994_AIF1ADC_LRCLK;
3194 break;
3195 case 2:
3196 aif1_reg = WM8994_AIF2_CONTROL_1;
3197 bclk_reg = WM8994_AIF2_BCLK;
3198 rate_reg = WM8994_AIF2_RATE;
3199 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
3200 wm8994->lrclk_shared[1])
3201 lrclk_reg = WM8994_AIF2DAC_LRCLK;
3202 else
3203 lrclk_reg = WM8994_AIF2ADC_LRCLK;
3204 break;
3205 default:
3206 return -EINVAL;
3207 }
3208
3209 bclk_rate = params_rate(params) * 2;
3210 switch (params_format(params)) {
3211 case SNDRV_PCM_FORMAT_S16_LE:
3212 bclk_rate *= 16;
3213 break;
3214 case SNDRV_PCM_FORMAT_S20_3LE:
3215 bclk_rate *= 20;
3216 aif1 |= 0x20;
3217 break;
3218 case SNDRV_PCM_FORMAT_S24_LE:
3219 bclk_rate *= 24;
3220 aif1 |= 0x40;
3221 break;
3222 case SNDRV_PCM_FORMAT_S32_LE:
3223 bclk_rate *= 32;
3224 aif1 |= 0x60;
3225 break;
3226 default:
3227 return -EINVAL;
3228 }
3229
3230 /* Try to find an appropriate sample rate; look for an exact match. */
3231 for (i = 0; i < ARRAY_SIZE(srs); i++)
3232 if (srs[i].rate == params_rate(params))
3233 break;
3234 if (i == ARRAY_SIZE(srs))
3235 return -EINVAL;
3236 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
3237
3238 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
3239 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
3240 dai->id, wm8994->aifclk[id], bclk_rate);
3241
3242 if (wm8994->aifclk[id] == 0) {
3243 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
3244 return -EINVAL;
3245 }
3246
3247 /* AIFCLK/fs ratio; look for a close match in either direction */
3248 best = 0;
3249 best_val = abs((fs_ratios[0] * params_rate(params))
3250 - wm8994->aifclk[id]);
3251 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
3252 cur_val = abs((fs_ratios[i] * params_rate(params))
3253 - wm8994->aifclk[id]);
3254 if (cur_val >= best_val)
3255 continue;
3256 best = i;
3257 best_val = cur_val;
3258 }
3259 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
3260 dai->id, fs_ratios[best]);
3261 rate_val |= best;
3262
3263 /* We may not get quite the right frequency if using
3264 * approximate clocks so look for the closest match that is
3265 * higher than the target (we need to ensure that there enough
3266 * BCLKs to clock out the samples).
3267 */
3268 best = 0;
3269 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
3270 if (bclk_divs[i] < 0)
3271 continue;
3272 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i])
3273 - bclk_rate * 10;
3274 if (cur_val < 0) /* BCLK table is sorted */
3275 break;
3276 best = i;
3277 }
3278 bclk_rate = wm8994->aifclk[id] / bclk_divs[best];
3279 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
3280 bclk_divs[best], bclk_rate);
3281 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
3282
3283 lrclk = bclk_rate / params_rate(params);
3284 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
3285 lrclk, bclk_rate / lrclk);
3286
3287 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
3288 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
3289 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
3290 lrclk);
3291 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
3292 WM8994_AIF1CLK_RATE_MASK, rate_val);
3293
3294 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3295 switch (dai->id) {
3296 case 1:
3297 wm8994->dac_rates[0] = params_rate(params);
3298 wm8994_set_retune_mobile(codec, 0);
3299 wm8994_set_retune_mobile(codec, 1);
3300 break;
3301 case 2:
3302 wm8994->dac_rates[1] = params_rate(params);
3303 wm8994_set_retune_mobile(codec, 2);
3304 break;
3305 }
3306 }
3307
3308 return 0;
3309}
3310
3311static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
3312{
3313 struct snd_soc_codec *codec = codec_dai->codec;
3314 int mute_reg;
3315 int reg;
3316
3317 switch (codec_dai->id) {
3318 case 1:
3319 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
3320 break;
3321 case 2:
3322 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3323 break;
3324 default:
3325 return -EINVAL;
3326 }
3327
3328 if (mute)
3329 reg = WM8994_AIF1DAC1_MUTE;
3330 else
3331 reg = 0;
3332
3333 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3334
3335 return 0;
3336}
3337
3338#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3339
3340#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3341 SNDRV_PCM_FMTBIT_S24_LE)
3342
3343static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3344 .set_sysclk = wm8994_set_dai_sysclk,
3345 .set_fmt = wm8994_set_dai_fmt,
3346 .hw_params = wm8994_hw_params,
3347 .digital_mute = wm8994_aif_mute,
3348 .set_pll = wm8994_set_fll,
3349};
3350
3351static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3352 .set_sysclk = wm8994_set_dai_sysclk,
3353 .set_fmt = wm8994_set_dai_fmt,
3354 .hw_params = wm8994_hw_params,
3355 .digital_mute = wm8994_aif_mute,
3356 .set_pll = wm8994_set_fll,
3357};
3358
3359struct snd_soc_dai wm8994_dai[] = {
3360 {
3361 .name = "WM8994 AIF1",
3362 .id = 1,
3363 .playback = {
3364 .stream_name = "AIF1 Playback",
3365 .channels_min = 2,
3366 .channels_max = 2,
3367 .rates = WM8994_RATES,
3368 .formats = WM8994_FORMATS,
3369 },
3370 .capture = {
3371 .stream_name = "AIF1 Capture",
3372 .channels_min = 2,
3373 .channels_max = 2,
3374 .rates = WM8994_RATES,
3375 .formats = WM8994_FORMATS,
3376 },
3377 .ops = &wm8994_aif1_dai_ops,
3378 },
3379 {
3380 .name = "WM8994 AIF2",
3381 .id = 2,
3382 .playback = {
3383 .stream_name = "AIF2 Playback",
3384 .channels_min = 2,
3385 .channels_max = 2,
3386 .rates = WM8994_RATES,
3387 .formats = WM8994_FORMATS,
3388 },
3389 .capture = {
3390 .stream_name = "AIF2 Capture",
3391 .channels_min = 2,
3392 .channels_max = 2,
3393 .rates = WM8994_RATES,
3394 .formats = WM8994_FORMATS,
3395 },
3396 .ops = &wm8994_aif2_dai_ops,
3397 },
3398 {
3399 .name = "WM8994 AIF3",
3400 .playback = {
3401 .stream_name = "AIF3 Playback",
3402 .channels_min = 2,
3403 .channels_max = 2,
3404 .rates = WM8994_RATES,
3405 .formats = WM8994_FORMATS,
3406 },
3407 .playback = {
3408 .stream_name = "AIF3 Capture",
3409 .channels_min = 2,
3410 .channels_max = 2,
3411 .rates = WM8994_RATES,
3412 .formats = WM8994_FORMATS,
3413 },
3414 }
3415};
3416EXPORT_SYMBOL_GPL(wm8994_dai);
3417
3418#ifdef CONFIG_PM
3419static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
3420{
3421 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3422 struct snd_soc_codec *codec = socdev->card->codec;
3423 struct wm8994_priv *wm8994 = codec->private_data;
3424 int i, ret;
3425
3426 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3427 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3428 sizeof(struct fll_config));
3429 ret = wm8994_set_fll(&codec->dai[0], i + 1, 0, 0, 0);
3430 if (ret < 0)
3431 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3432 i + 1, ret);
3433 }
3434
3435 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3436
3437 return 0;
3438}
3439
3440static int wm8994_resume(struct platform_device *pdev)
3441{
3442 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3443 struct snd_soc_codec *codec = socdev->card->codec;
3444 struct wm8994_priv *wm8994 = codec->private_data;
3445 u16 *reg_cache = codec->reg_cache;
3446 int i, ret;
3447
3448 /* Restore the registers */
3449 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
3450 switch (i) {
3451 case WM8994_LDO_1:
3452 case WM8994_LDO_2:
3453 case WM8994_SOFTWARE_RESET:
3454 /* Handled by other MFD drivers */
3455 continue;
3456 default:
3457 break;
3458 }
3459
3460 if (!access_masks[i].writable)
3461 continue;
3462
3463 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
3464 }
3465
3466 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3467
3468 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3469 ret = wm8994_set_fll(&codec->dai[0], i + 1,
3470 wm8994->fll_suspend[i].src,
3471 wm8994->fll_suspend[i].in,
3472 wm8994->fll_suspend[i].out);
3473 if (ret < 0)
3474 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3475 i + 1, ret);
3476 }
3477
3478 return 0;
3479}
3480#else
3481#define wm8994_suspend NULL
3482#define wm8994_resume NULL
3483#endif
3484
3485static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3486{
3487 struct snd_soc_codec *codec = &wm8994->codec;
3488 struct wm8994_pdata *pdata = wm8994->pdata;
3489 struct snd_kcontrol_new controls[] = {
3490 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3491 wm8994->retune_mobile_enum,
3492 wm8994_get_retune_mobile_enum,
3493 wm8994_put_retune_mobile_enum),
3494 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3495 wm8994->retune_mobile_enum,
3496 wm8994_get_retune_mobile_enum,
3497 wm8994_put_retune_mobile_enum),
3498 SOC_ENUM_EXT("AIF2 EQ Mode",
3499 wm8994->retune_mobile_enum,
3500 wm8994_get_retune_mobile_enum,
3501 wm8994_put_retune_mobile_enum),
3502 };
3503 int ret, i, j;
3504 const char **t;
3505
3506 /* We need an array of texts for the enum API but the number
3507 * of texts is likely to be less than the number of
3508 * configurations due to the sample rate dependency of the
3509 * configurations. */
3510 wm8994->num_retune_mobile_texts = 0;
3511 wm8994->retune_mobile_texts = NULL;
3512 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3513 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3514 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3515 wm8994->retune_mobile_texts[j]) == 0)
3516 break;
3517 }
3518
3519 if (j != wm8994->num_retune_mobile_texts)
3520 continue;
3521
3522 /* Expand the array... */
3523 t = krealloc(wm8994->retune_mobile_texts,
3524 sizeof(char *) *
3525 (wm8994->num_retune_mobile_texts + 1),
3526 GFP_KERNEL);
3527 if (t == NULL)
3528 continue;
3529
3530 /* ...store the new entry... */
3531 t[wm8994->num_retune_mobile_texts] =
3532 pdata->retune_mobile_cfgs[i].name;
3533
3534 /* ...and remember the new version. */
3535 wm8994->num_retune_mobile_texts++;
3536 wm8994->retune_mobile_texts = t;
3537 }
3538
3539 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3540 wm8994->num_retune_mobile_texts);
3541
3542 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3543 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3544
3545 ret = snd_soc_add_controls(&wm8994->codec, controls,
3546 ARRAY_SIZE(controls));
3547 if (ret != 0)
3548 dev_err(wm8994->codec.dev,
3549 "Failed to add ReTune Mobile controls: %d\n", ret);
3550}
3551
3552static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3553{
3554 struct snd_soc_codec *codec = &wm8994->codec;
3555 struct wm8994_pdata *pdata = wm8994->pdata;
3556 int ret, i;
3557
3558 if (!pdata)
3559 return;
3560
3561 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3562 pdata->lineout2_diff,
3563 pdata->lineout1fb,
3564 pdata->lineout2fb,
3565 pdata->jd_scthr,
3566 pdata->jd_thr,
3567 pdata->micbias1_lvl,
3568 pdata->micbias2_lvl);
3569
3570 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3571
3572 if (pdata->num_drc_cfgs) {
3573 struct snd_kcontrol_new controls[] = {
3574 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3575 wm8994_get_drc_enum, wm8994_put_drc_enum),
3576 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3577 wm8994_get_drc_enum, wm8994_put_drc_enum),
3578 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3579 wm8994_get_drc_enum, wm8994_put_drc_enum),
3580 };
3581
3582 /* We need an array of texts for the enum API */
3583 wm8994->drc_texts = kmalloc(sizeof(char *)
3584 * pdata->num_drc_cfgs, GFP_KERNEL);
3585 if (!wm8994->drc_texts) {
3586 dev_err(wm8994->codec.dev,
3587 "Failed to allocate %d DRC config texts\n",
3588 pdata->num_drc_cfgs);
3589 return;
3590 }
3591
3592 for (i = 0; i < pdata->num_drc_cfgs; i++)
3593 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3594
3595 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3596 wm8994->drc_enum.texts = wm8994->drc_texts;
3597
3598 ret = snd_soc_add_controls(&wm8994->codec, controls,
3599 ARRAY_SIZE(controls));
3600 if (ret != 0)
3601 dev_err(wm8994->codec.dev,
3602 "Failed to add DRC mode controls: %d\n", ret);
3603
3604 for (i = 0; i < WM8994_NUM_DRC; i++)
3605 wm8994_set_drc(codec, i);
3606 }
3607
3608 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3609 pdata->num_retune_mobile_cfgs);
3610
3611 if (pdata->num_retune_mobile_cfgs)
3612 wm8994_handle_retune_mobile_pdata(wm8994);
3613 else
3614 snd_soc_add_controls(&wm8994->codec, wm8994_eq_controls,
3615 ARRAY_SIZE(wm8994_eq_controls));
3616}
3617
3618static int wm8994_probe(struct platform_device *pdev)
3619{
3620 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3621 struct snd_soc_codec *codec;
3622 int ret = 0;
3623
3624 if (wm8994_codec == NULL) {
3625 dev_err(&pdev->dev, "Codec device not registered\n");
3626 return -ENODEV;
3627 }
3628
3629 socdev->card->codec = wm8994_codec;
3630 codec = wm8994_codec;
3631
3632 /* register pcms */
3633 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
3634 if (ret < 0) {
3635 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
3636 return ret;
3637 }
3638
3639 wm8994_handle_pdata(codec->private_data);
3640
3641 wm_hubs_add_analogue_controls(codec);
3642 snd_soc_add_controls(codec, wm8994_snd_controls,
3643 ARRAY_SIZE(wm8994_snd_controls));
3644 snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets,
3645 ARRAY_SIZE(wm8994_dapm_widgets));
3646 wm_hubs_add_analogue_routes(codec, 0, 0);
3647 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
3648
3649 return 0;
3650}
3651
3652static int wm8994_remove(struct platform_device *pdev)
3653{
3654 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3655
3656 snd_soc_free_pcms(socdev);
3657 snd_soc_dapm_free(socdev);
3658
3659 return 0;
3660}
3661
3662struct snd_soc_codec_device soc_codec_dev_wm8994 = {
3663 .probe = wm8994_probe,
3664 .remove = wm8994_remove,
3665 .suspend = wm8994_suspend,
3666 .resume = wm8994_resume,
3667};
3668EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
3669
3670static int wm8994_codec_probe(struct platform_device *pdev)
3671{
3672 int ret;
3673 struct wm8994_priv *wm8994;
3674 struct snd_soc_codec *codec;
3675 int i;
3676 u16 rev;
3677
3678 if (wm8994_codec) {
3679 dev_err(&pdev->dev, "Another WM8994 is registered\n");
3680 return -EINVAL;
3681 }
3682
3683 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3684 if (!wm8994) {
3685 dev_err(&pdev->dev, "Failed to allocate private data\n");
3686 return -ENOMEM;
3687 }
3688
3689 codec = &wm8994->codec;
3690
3691 mutex_init(&codec->mutex);
3692 INIT_LIST_HEAD(&codec->dapm_widgets);
3693 INIT_LIST_HEAD(&codec->dapm_paths);
3694
3695 codec->private_data = wm8994;
3696 codec->control_data = dev_get_drvdata(pdev->dev.parent);
3697 codec->name = "WM8994";
3698 codec->owner = THIS_MODULE;
3699 codec->read = wm8994_read;
3700 codec->write = wm8994_write;
3701 codec->readable_register = wm8994_readable;
3702 codec->bias_level = SND_SOC_BIAS_OFF;
3703 codec->set_bias_level = wm8994_set_bias_level;
3704 codec->dai = &wm8994_dai[0];
3705 codec->num_dai = 3;
3706 codec->reg_cache_size = WM8994_MAX_REGISTER;
3707 codec->reg_cache = &wm8994->reg_cache;
3708 codec->dev = &pdev->dev;
3709
3710 wm8994->pdata = pdev->dev.parent->platform_data;
3711
3712 /* Fill the cache with physical values we inherited; don't reset */
3713 ret = wm8994_bulk_read(codec->control_data, 0,
3714 ARRAY_SIZE(wm8994->reg_cache) - 1,
3715 codec->reg_cache);
3716 if (ret < 0) {
3717 dev_err(codec->dev, "Failed to fill register cache: %d\n",
3718 ret);
3719 goto err;
3720 }
3721
3722 /* Clear the cached values for unreadable/volatile registers to
3723 * avoid potential confusion.
3724 */
3725 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
3726 if (wm8994_volatile(i) || !wm8994_readable(i))
3727 wm8994->reg_cache[i] = 0;
3728
3729 /* Set revision-specific configuration */
3730 rev = snd_soc_read(codec, WM8994_CHIP_REVISION);
3731 switch (rev) {
3732 case 2:
3733 case 3:
3734 wm8994->hubs.dcs_codes = -5;
3735 wm8994->hubs.hp_startup_mode = 1;
3736 break;
3737 default:
3738 break;
3739 }
3740
3741
3742 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3743 * configured on init - if a system wants to do this dynamically
3744 * at runtime we can deal with that then.
3745 */
3746 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3747 if (ret < 0) {
3748 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3749 goto err;
3750 }
3751 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3752 wm8994->lrclk_shared[0] = 1;
3753 wm8994_dai[0].symmetric_rates = 1;
3754 } else {
3755 wm8994->lrclk_shared[0] = 0;
3756 }
3757
3758 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3759 if (ret < 0) {
3760 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3761 goto err;
3762 }
3763 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3764 wm8994->lrclk_shared[1] = 1;
3765 wm8994_dai[1].symmetric_rates = 1;
3766 } else {
3767 wm8994->lrclk_shared[1] = 0;
3768 }
3769
3770 for (i = 0; i < ARRAY_SIZE(wm8994_dai); i++)
3771 wm8994_dai[i].dev = codec->dev;
3772
3773 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3774
3775 wm8994_codec = codec;
3776
3777 /* Latch volume updates (right only; we always do left then right). */
3778 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3779 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3780 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3781 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3782 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3783 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3784 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3785 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3786 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3787 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3788 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3789 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3790 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3791 WM8994_DAC1_VU, WM8994_DAC1_VU);
3792 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3793 WM8994_DAC2_VU, WM8994_DAC2_VU);
3794
3795 /* Set the low bit of the 3D stereo depth so TLV matches */
3796 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3797 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3798 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3799 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3800 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3801 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3802 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3803 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3804 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3805
3806 wm8994_update_class_w(codec);
3807
3808 ret = snd_soc_register_codec(codec);
3809 if (ret != 0) {
3810 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
3811 goto err;
3812 }
3813
3814 ret = snd_soc_register_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
3815 if (ret != 0) {
3816 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
3817 goto err_codec;
3818 }
3819
3820 platform_set_drvdata(pdev, wm8994);
3821
3822 return 0;
3823
3824err_codec:
3825 snd_soc_unregister_codec(codec);
3826err:
3827 kfree(wm8994);
3828 return ret;
3829}
3830
3831static int __devexit wm8994_codec_remove(struct platform_device *pdev)
3832{
3833 struct wm8994_priv *wm8994 = platform_get_drvdata(pdev);
3834 struct snd_soc_codec *codec = &wm8994->codec;
3835
3836 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3837 snd_soc_unregister_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
3838 snd_soc_unregister_codec(&wm8994->codec);
3839 kfree(wm8994);
3840 wm8994_codec = NULL;
3841
3842 return 0;
3843}
3844
3845static struct platform_driver wm8994_codec_driver = {
3846 .driver = {
3847 .name = "wm8994-codec",
3848 .owner = THIS_MODULE,
3849 },
3850 .probe = wm8994_codec_probe,
3851 .remove = __devexit_p(wm8994_codec_remove),
3852};
3853
3854static __init int wm8994_init(void)
3855{
3856 return platform_driver_register(&wm8994_codec_driver);
3857}
3858module_init(wm8994_init);
3859
3860static __exit void wm8994_exit(void)
3861{
3862 platform_driver_unregister(&wm8994_codec_driver);
3863}
3864module_exit(wm8994_exit);
3865
3866
3867MODULE_DESCRIPTION("ASoC WM8994 driver");
3868MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3869MODULE_LICENSE("GPL");
3870MODULE_ALIAS("platform:wm8994-codec");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 15:06:53 -0500