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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-04-19 23:56:18 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-04-20 12:41:26 -0400
commit136ff2a272ad4bee33bf85f8c490ff8a2dd08f96 (patch)
tree4f8876c8acdb816e432916f5cd8ad84e1533cdd0 /sound/soc/codecs/wm8994.c
parent4f6f22d7bef77dfb6b27eaed4240784339c546e6 (diff)
ASoC: Support FLL input clock selection on WM8994
The WM8994 FLL can be clocked from one of four inputs, the two MCLKs and the LRCLK and BCLK of the AIF associated with the FLL. Allow all four inputs to be used rather than defaulting to MCLK1. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/wm8994.c')
-rw-r--r--sound/soc/codecs/wm8994.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 29c4cfccd6b9..a27b2ff769d9 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -2843,6 +2843,16 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2843 return -EINVAL; 2843 return -EINVAL;
2844 } 2844 }
2845 2845
2846 switch (src) {
2847 case WM8994_FLL_SRC_MCLK1:
2848 case WM8994_FLL_SRC_MCLK2:
2849 case WM8994_FLL_SRC_LRCLK:
2850 case WM8994_FLL_SRC_BCLK:
2851 break;
2852 default:
2853 return -EINVAL;
2854 }
2855
2846 /* Are we changing anything? */ 2856 /* Are we changing anything? */
2847 if (wm8994->fll[id].src == src && 2857 if (wm8994->fll[id].src == src &&
2848 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 2858 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
@@ -2883,8 +2893,10 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2883 fll.n << WM8994_FLL1_N_SHIFT); 2893 fll.n << WM8994_FLL1_N_SHIFT);
2884 2894
2885 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2895 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2886 WM8994_FLL1_REFCLK_DIV_MASK, 2896 WM8994_FLL1_REFCLK_DIV_MASK |
2887 fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT); 2897 WM8994_FLL1_REFCLK_SRC_MASK,
2898 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2899 (src - 1));
2888 2900
2889 /* Enable (with fractional mode if required) */ 2901 /* Enable (with fractional mode if required) */
2890 if (freq_out) { 2902 if (freq_out) {
@@ -2899,6 +2911,7 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2899 2911
2900 wm8994->fll[id].in = freq_in; 2912 wm8994->fll[id].in = freq_in;
2901 wm8994->fll[id].out = freq_out; 2913 wm8994->fll[id].out = freq_out;
2914 wm8994->fll[id].src = src;
2902 2915
2903 /* Enable any gated AIF clocks */ 2916 /* Enable any gated AIF clocks */
2904 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 2917 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,