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authorMark Brown <broonie@opensource.wolfsonmicro.com>2009-06-05 11:32:59 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-07-08 12:20:20 -0400
commit942c435ba79fd263a922bb114d56eccab6250662 (patch)
tree33dbd312f92e67841620823838b30c27b51686a5 /sound/soc/codecs/wm8993.c
parentff7d04b130d76ab3a7b79120070346ccf3a72b3f (diff)
ASoC: Add WM8993 CODEC driver
The WM8993 is a highly integrated ultra-low power hi-fi CODEC designed for portable devices such as multimedia phones. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/wm8993.c')
-rw-r--r--sound/soc/codecs/wm8993.c2203
1 files changed, 2203 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c
new file mode 100644
index 000000000000..3e5c65a1ea8b
--- /dev/null
+++ b/sound/soc/codecs/wm8993.c
@@ -0,0 +1,2203 @@
1/*
2 * wm8993.c -- WM8993 ALSA SoC audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
19#include <linux/spi/spi.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/tlv.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/wm8993.h>
28
29#include "wm8993.h"
30
31static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
32 0x8993, /* R0 - Software Reset */
33 0x0000, /* R1 - Power Management (1) */
34 0x6000, /* R2 - Power Management (2) */
35 0x0000, /* R3 - Power Management (3) */
36 0x4050, /* R4 - Audio Interface (1) */
37 0x4000, /* R5 - Audio Interface (2) */
38 0x01C8, /* R6 - Clocking 1 */
39 0x0000, /* R7 - Clocking 2 */
40 0x0000, /* R8 - Audio Interface (3) */
41 0x0040, /* R9 - Audio Interface (4) */
42 0x0004, /* R10 - DAC CTRL */
43 0x00C0, /* R11 - Left DAC Digital Volume */
44 0x00C0, /* R12 - Right DAC Digital Volume */
45 0x0000, /* R13 - Digital Side Tone */
46 0x0300, /* R14 - ADC CTRL */
47 0x00C0, /* R15 - Left ADC Digital Volume */
48 0x00C0, /* R16 - Right ADC Digital Volume */
49 0x0000, /* R17 */
50 0x0000, /* R18 - GPIO CTRL 1 */
51 0x0010, /* R19 - GPIO1 */
52 0x0000, /* R20 - IRQ_DEBOUNCE */
53 0x0000, /* R21 */
54 0x8000, /* R22 - GPIOCTRL 2 */
55 0x0800, /* R23 - GPIO_POL */
56 0x008B, /* R24 - Left Line Input 1&2 Volume */
57 0x008B, /* R25 - Left Line Input 3&4 Volume */
58 0x008B, /* R26 - Right Line Input 1&2 Volume */
59 0x008B, /* R27 - Right Line Input 3&4 Volume */
60 0x006D, /* R28 - Left Output Volume */
61 0x006D, /* R29 - Right Output Volume */
62 0x0066, /* R30 - Line Outputs Volume */
63 0x0020, /* R31 - HPOUT2 Volume */
64 0x0079, /* R32 - Left OPGA Volume */
65 0x0079, /* R33 - Right OPGA Volume */
66 0x0003, /* R34 - SPKMIXL Attenuation */
67 0x0003, /* R35 - SPKMIXR Attenuation */
68 0x0011, /* R36 - SPKOUT Mixers */
69 0x0100, /* R37 - SPKOUT Boost */
70 0x0079, /* R38 - Speaker Volume Left */
71 0x0079, /* R39 - Speaker Volume Right */
72 0x0000, /* R40 - Input Mixer2 */
73 0x0000, /* R41 - Input Mixer3 */
74 0x0000, /* R42 - Input Mixer4 */
75 0x0000, /* R43 - Input Mixer5 */
76 0x0000, /* R44 - Input Mixer6 */
77 0x0000, /* R45 - Output Mixer1 */
78 0x0000, /* R46 - Output Mixer2 */
79 0x0000, /* R47 - Output Mixer3 */
80 0x0000, /* R48 - Output Mixer4 */
81 0x0000, /* R49 - Output Mixer5 */
82 0x0000, /* R50 - Output Mixer6 */
83 0x0000, /* R51 - HPOUT2 Mixer */
84 0x0000, /* R52 - Line Mixer1 */
85 0x0000, /* R53 - Line Mixer2 */
86 0x0000, /* R54 - Speaker Mixer */
87 0x0000, /* R55 - Additional Control */
88 0x0000, /* R56 - AntiPOP1 */
89 0x0000, /* R57 - AntiPOP2 */
90 0x0000, /* R58 - MICBIAS */
91 0x0000, /* R59 */
92 0x0000, /* R60 - FLL Control 1 */
93 0x0000, /* R61 - FLL Control 2 */
94 0x0000, /* R62 - FLL Control 3 */
95 0x2EE0, /* R63 - FLL Control 4 */
96 0x0002, /* R64 - FLL Control 5 */
97 0x2287, /* R65 - Clocking 3 */
98 0x025F, /* R66 - Clocking 4 */
99 0x0000, /* R67 - MW Slave Control */
100 0x0000, /* R68 */
101 0x0002, /* R69 - Bus Control 1 */
102 0x0000, /* R70 - Write Sequencer 0 */
103 0x0000, /* R71 - Write Sequencer 1 */
104 0x0000, /* R72 - Write Sequencer 2 */
105 0x0000, /* R73 - Write Sequencer 3 */
106 0x0000, /* R74 - Write Sequencer 4 */
107 0x0000, /* R75 - Write Sequencer 5 */
108 0x1F25, /* R76 - Charge Pump 1 */
109 0x0000, /* R77 */
110 0x0000, /* R78 */
111 0x0000, /* R79 */
112 0x0000, /* R80 */
113 0x0000, /* R81 - Class W 0 */
114 0x0000, /* R82 */
115 0x0000, /* R83 */
116 0x0000, /* R84 - DC Servo 0 */
117 0x054A, /* R85 - DC Servo 1 */
118 0x0000, /* R86 */
119 0x0000, /* R87 - DC Servo 3 */
120 0x0000, /* R88 - DC Servo Readback 0 */
121 0x0000, /* R89 - DC Servo Readback 1 */
122 0x0000, /* R90 - DC Servo Readback 2 */
123 0x0000, /* R91 */
124 0x0000, /* R92 */
125 0x0000, /* R93 */
126 0x0000, /* R94 */
127 0x0000, /* R95 */
128 0x0100, /* R96 - Analogue HP 0 */
129 0x0000, /* R97 */
130 0x0000, /* R98 - EQ1 */
131 0x000C, /* R99 - EQ2 */
132 0x000C, /* R100 - EQ3 */
133 0x000C, /* R101 - EQ4 */
134 0x000C, /* R102 - EQ5 */
135 0x000C, /* R103 - EQ6 */
136 0x0FCA, /* R104 - EQ7 */
137 0x0400, /* R105 - EQ8 */
138 0x00D8, /* R106 - EQ9 */
139 0x1EB5, /* R107 - EQ10 */
140 0xF145, /* R108 - EQ11 */
141 0x0B75, /* R109 - EQ12 */
142 0x01C5, /* R110 - EQ13 */
143 0x1C58, /* R111 - EQ14 */
144 0xF373, /* R112 - EQ15 */
145 0x0A54, /* R113 - EQ16 */
146 0x0558, /* R114 - EQ17 */
147 0x168E, /* R115 - EQ18 */
148 0xF829, /* R116 - EQ19 */
149 0x07AD, /* R117 - EQ20 */
150 0x1103, /* R118 - EQ21 */
151 0x0564, /* R119 - EQ22 */
152 0x0559, /* R120 - EQ23 */
153 0x4000, /* R121 - EQ24 */
154 0x0000, /* R122 - Digital Pulls */
155 0x0F08, /* R123 - DRC Control 1 */
156 0x0000, /* R124 - DRC Control 2 */
157 0x0080, /* R125 - DRC Control 3 */
158 0x0000, /* R126 - DRC Control 4 */
159};
160
161static struct {
162 int ratio;
163 int clk_sys_rate;
164} clk_sys_rates[] = {
165 { 64, 0 },
166 { 128, 1 },
167 { 192, 2 },
168 { 256, 3 },
169 { 384, 4 },
170 { 512, 5 },
171 { 768, 6 },
172 { 1024, 7 },
173 { 1408, 8 },
174 { 1536, 9 },
175};
176
177static struct {
178 int rate;
179 int sample_rate;
180} sample_rates[] = {
181 { 8000, 0 },
182 { 11025, 1 },
183 { 12000, 1 },
184 { 16000, 2 },
185 { 22050, 3 },
186 { 24000, 3 },
187 { 32000, 4 },
188 { 44100, 5 },
189 { 48000, 5 },
190};
191
192static struct {
193 int div; /* *10 due to .5s */
194 int bclk_div;
195} bclk_divs[] = {
196 { 10, 0 },
197 { 15, 1 },
198 { 20, 2 },
199 { 30, 3 },
200 { 40, 4 },
201 { 55, 5 },
202 { 60, 6 },
203 { 80, 7 },
204 { 110, 8 },
205 { 120, 9 },
206 { 160, 10 },
207 { 220, 11 },
208 { 240, 12 },
209 { 320, 13 },
210 { 440, 14 },
211 { 480, 15 },
212};
213
214struct wm8993_priv {
215 u16 reg_cache[WM8993_REGISTER_COUNT];
216 struct wm8993_platform_data pdata;
217 struct snd_soc_codec codec;
218 int master;
219 int sysclk_source;
220 unsigned int mclk_rate;
221 unsigned int sysclk_rate;
222 unsigned int fs;
223 unsigned int bclk;
224 int class_w_users;
225 unsigned int fll_fref;
226 unsigned int fll_fout;
227};
228
229static unsigned int wm8993_read_hw(struct snd_soc_codec *codec, u8 reg)
230{
231 struct i2c_msg xfer[2];
232 u16 data;
233 int ret;
234 struct i2c_client *i2c = codec->control_data;
235
236 /* Write register */
237 xfer[0].addr = i2c->addr;
238 xfer[0].flags = 0;
239 xfer[0].len = 1;
240 xfer[0].buf = &reg;
241
242 /* Read data */
243 xfer[1].addr = i2c->addr;
244 xfer[1].flags = I2C_M_RD;
245 xfer[1].len = 2;
246 xfer[1].buf = (u8 *)&data;
247
248 ret = i2c_transfer(i2c->adapter, xfer, 2);
249 if (ret != 2) {
250 dev_err(codec->dev, "Failed to read 0x%x: %d\n", reg, ret);
251 return 0;
252 }
253
254 return (data >> 8) | ((data & 0xff) << 8);
255}
256
257static int wm8993_volatile(unsigned int reg)
258{
259 switch (reg) {
260 case WM8993_SOFTWARE_RESET:
261 case WM8993_DC_SERVO_0:
262 case WM8993_DC_SERVO_READBACK_0:
263 case WM8993_DC_SERVO_READBACK_1:
264 case WM8993_DC_SERVO_READBACK_2:
265 return 1;
266 default:
267 return 0;
268 }
269}
270
271static unsigned int wm8993_read(struct snd_soc_codec *codec,
272 unsigned int reg)
273{
274 u16 *reg_cache = codec->reg_cache;
275
276 BUG_ON(reg > WM8993_MAX_REGISTER);
277
278 if (wm8993_volatile(reg))
279 return wm8993_read_hw(codec, reg);
280 else
281 return reg_cache[reg];
282}
283
284static int wm8993_write(struct snd_soc_codec *codec, unsigned int reg,
285 unsigned int value)
286{
287 u16 *reg_cache = codec->reg_cache;
288 u8 data[3];
289 int ret;
290
291 BUG_ON(reg > WM8993_MAX_REGISTER);
292
293 /* data is
294 * D15..D9 WM8993 register offset
295 * D8...D0 register data
296 */
297 data[0] = reg;
298 data[1] = value >> 8;
299 data[2] = value & 0x00ff;
300
301 if (!wm8993_volatile(reg))
302 reg_cache[reg] = value;
303
304 ret = codec->hw_write(codec->control_data, data, 3);
305
306 if (ret == 3)
307 return 0;
308 if (ret < 0)
309 return ret;
310 return -EIO;
311}
312
313struct _fll_div {
314 u16 fll_fratio;
315 u16 fll_outdiv;
316 u16 fll_clk_ref_div;
317 u16 n;
318 u16 k;
319};
320
321/* The size in bits of the FLL divide multiplied by 10
322 * to allow rounding later */
323#define FIXED_FLL_SIZE ((1 << 16) * 10)
324
325static struct {
326 unsigned int min;
327 unsigned int max;
328 u16 fll_fratio;
329 int ratio;
330} fll_fratios[] = {
331 { 0, 64000, 4, 16 },
332 { 64000, 128000, 3, 8 },
333 { 128000, 256000, 2, 4 },
334 { 256000, 1000000, 1, 2 },
335 { 1000000, 13500000, 0, 1 },
336};
337
338static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
339 unsigned int Fout)
340{
341 u64 Kpart;
342 unsigned int K, Ndiv, Nmod, target;
343 unsigned int div;
344 int i;
345
346 /* Fref must be <=13.5MHz */
347 div = 1;
348 while ((Fref / div) > 13500000) {
349 div *= 2;
350
351 if (div > 8) {
352 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
353 Fref);
354 return -EINVAL;
355 }
356 }
357
358 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
359
360 /* Apply the division for our remaining calculations */
361 Fref /= div;
362
363 /* Fvco should be 90-100MHz; don't check the upper bound */
364 div = 0;
365 target = Fout * 2;
366 while (target < 90000000) {
367 div++;
368 target *= 2;
369 if (div > 7) {
370 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
371 Fout);
372 return -EINVAL;
373 }
374 }
375 fll_div->fll_outdiv = div;
376
377 pr_debug("Fvco=%dHz\n", target);
378
379 /* Find an appropraite FLL_FRATIO and factor it out of the target */
380 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
381 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
382 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
383 target /= fll_fratios[i].ratio;
384 break;
385 }
386 }
387 if (i == ARRAY_SIZE(fll_fratios)) {
388 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
389 return -EINVAL;
390 }
391
392 /* Now, calculate N.K */
393 Ndiv = target / Fref;
394
395 fll_div->n = Ndiv;
396 Nmod = target % Fref;
397 pr_debug("Nmod=%d\n", Nmod);
398
399 /* Calculate fractional part - scale up so we can round. */
400 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
401
402 do_div(Kpart, Fref);
403
404 K = Kpart & 0xFFFFFFFF;
405
406 if ((K % 10) >= 5)
407 K += 5;
408
409 /* Move down to proper range now rounding is done */
410 fll_div->k = K / 10;
411
412 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
413 fll_div->n, fll_div->k,
414 fll_div->fll_fratio, fll_div->fll_outdiv,
415 fll_div->fll_clk_ref_div);
416
417 return 0;
418}
419
420static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id,
421 unsigned int Fref, unsigned int Fout)
422{
423 struct snd_soc_codec *codec = dai->codec;
424 struct wm8993_priv *wm8993 = codec->private_data;
425 u16 reg1, reg4, reg5;
426 struct _fll_div fll_div;
427 int ret;
428
429 /* Any change? */
430 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
431 return 0;
432
433 /* Disable the FLL */
434 if (Fout == 0) {
435 dev_dbg(codec->dev, "FLL disabled\n");
436 wm8993->fll_fref = 0;
437 wm8993->fll_fout = 0;
438
439 reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1);
440 reg1 &= ~WM8993_FLL_ENA;
441 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
442
443 return 0;
444 }
445
446 ret = fll_factors(&fll_div, Fref, Fout);
447 if (ret != 0)
448 return ret;
449
450 reg5 = wm8993_read(codec, WM8993_FLL_CONTROL_5);
451 reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
452
453 switch (fll_id) {
454 case WM8993_FLL_MCLK:
455 break;
456
457 case WM8993_FLL_LRCLK:
458 reg5 |= 1;
459 break;
460
461 case WM8993_FLL_BCLK:
462 reg5 |= 2;
463 break;
464
465 default:
466 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
467 return -EINVAL;
468 }
469
470 /* Any FLL configuration change requires that the FLL be
471 * disabled first. */
472 reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1);
473 reg1 &= ~WM8993_FLL_ENA;
474 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
475
476 /* Apply the configuration */
477 if (fll_div.k)
478 reg1 |= WM8993_FLL_FRAC_MASK;
479 else
480 reg1 &= ~WM8993_FLL_FRAC_MASK;
481 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
482
483 wm8993_write(codec, WM8993_FLL_CONTROL_2,
484 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
485 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
486 wm8993_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
487
488 reg4 = wm8993_read(codec, WM8993_FLL_CONTROL_4);
489 reg4 &= ~WM8993_FLL_N_MASK;
490 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
491 wm8993_write(codec, WM8993_FLL_CONTROL_4, reg4);
492
493 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
494 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
495 wm8993_write(codec, WM8993_FLL_CONTROL_5, reg5);
496
497 /* Enable the FLL */
498 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
499
500 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
501
502 wm8993->fll_fref = Fref;
503 wm8993->fll_fout = Fout;
504
505 return 0;
506}
507
508static int configure_clock(struct snd_soc_codec *codec)
509{
510 struct wm8993_priv *wm8993 = codec->private_data;
511 unsigned int reg;
512
513 /* This should be done on init() for bypass paths */
514 switch (wm8993->sysclk_source) {
515 case WM8993_SYSCLK_MCLK:
516 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
517
518 reg = wm8993_read(codec, WM8993_CLOCKING_2);
519 reg &= ~WM8993_SYSCLK_SRC;
520 if (wm8993->mclk_rate > 13500000) {
521 reg |= WM8993_MCLK_DIV;
522 wm8993->sysclk_rate = wm8993->mclk_rate / 2;
523 } else {
524 reg &= ~WM8993_MCLK_DIV;
525 wm8993->sysclk_rate = wm8993->mclk_rate;
526 }
527 reg &= ~WM8993_MCLK_DIV;
528 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
529 wm8993_write(codec, WM8993_CLOCKING_2, reg);
530 break;
531
532 case WM8993_SYSCLK_FLL:
533 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
534 wm8993->fll_fout);
535
536 reg = wm8993_read(codec, WM8993_CLOCKING_2);
537 reg |= WM8993_SYSCLK_SRC;
538 if (wm8993->fll_fout > 13500000) {
539 reg |= WM8993_MCLK_DIV;
540 wm8993->sysclk_rate = wm8993->fll_fout / 2;
541 } else {
542 reg &= ~WM8993_MCLK_DIV;
543 wm8993->sysclk_rate = wm8993->fll_fout;
544 }
545 wm8993_write(codec, WM8993_CLOCKING_2, reg);
546 break;
547
548 default:
549 dev_err(codec->dev, "System clock not configured\n");
550 return -EINVAL;
551 }
552
553 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
554
555 return 0;
556}
557
558static void wait_for_dc_servo(struct snd_soc_codec *codec, int mask)
559{
560 unsigned int reg;
561 int count = 0;
562
563 dev_dbg(codec->dev, "Waiting for DC servo...\n");
564 do {
565 count++;
566 msleep(1);
567 reg = wm8993_read(codec, WM8993_DC_SERVO_READBACK_0);
568 dev_dbg(codec->dev, "DC servo status: %x\n", reg);
569 } while ((reg & WM8993_DCS_CAL_COMPLETE_MASK)
570 != WM8993_DCS_CAL_COMPLETE_MASK && count < 1000);
571
572 if ((reg & WM8993_DCS_CAL_COMPLETE_MASK)
573 != WM8993_DCS_CAL_COMPLETE_MASK)
574 dev_err(codec->dev, "Timed out waiting for DC Servo\n");
575}
576
577static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1650, 150, 0);
578static const DECLARE_TLV_DB_SCALE(inmix_sw_tlv, 0, 3000, 0);
579static const DECLARE_TLV_DB_SCALE(inmix_tlv, -1500, 300, 1);
580static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
581static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
582static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
583static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
584static const unsigned int drc_max_tlv[] = {
585 TLV_DB_RANGE_HEAD(4),
586 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
587 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
588};
589static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
590static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
591static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
592static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
593static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
594static const DECLARE_TLV_DB_SCALE(earpiece_tlv, -600, 600, 0);
595static const DECLARE_TLV_DB_SCALE(outmix_tlv, -2100, 300, 0);
596static const DECLARE_TLV_DB_SCALE(spkmix_tlv, -300, 300, 0);
597static const DECLARE_TLV_DB_SCALE(spkmixout_tlv, -1800, 600, 1);
598static const DECLARE_TLV_DB_SCALE(outpga_tlv, -5700, 100, 0);
599static const unsigned int spkboost_tlv[] = {
600 TLV_DB_RANGE_HEAD(7),
601 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
602 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
603};
604static const DECLARE_TLV_DB_SCALE(line_tlv, -600, 600, 0);
605
606static const char *speaker_ref_text[] = {
607 "SPKVDD/2",
608 "VMID",
609};
610
611static const struct soc_enum speaker_ref =
612 SOC_ENUM_SINGLE(WM8993_SPEAKER_MIXER, 8, 2, speaker_ref_text);
613
614static const char *speaker_mode_text[] = {
615 "Class D",
616 "Class AB",
617};
618
619static const struct soc_enum speaker_mode =
620 SOC_ENUM_SINGLE(WM8993_SPKMIXR_ATTENUATION, 8, 2, speaker_mode_text);
621
622static const char *dac_deemph_text[] = {
623 "None",
624 "32kHz",
625 "44.1kHz",
626 "48kHz",
627};
628
629static const struct soc_enum dac_deemph =
630 SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
631
632static const char *adc_hpf_text[] = {
633 "Hi-Fi",
634 "Voice 1",
635 "Voice 2",
636 "Voice 3",
637};
638
639static const struct soc_enum adc_hpf =
640 SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
641
642static const char *drc_path_text[] = {
643 "ADC",
644 "DAC"
645};
646
647static const struct soc_enum drc_path =
648 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
649
650static const char *drc_r0_text[] = {
651 "1",
652 "1/2",
653 "1/4",
654 "1/8",
655 "1/16",
656 "0",
657};
658
659static const struct soc_enum drc_r0 =
660 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
661
662static const char *drc_r1_text[] = {
663 "1",
664 "1/2",
665 "1/4",
666 "1/8",
667 "0",
668};
669
670static const struct soc_enum drc_r1 =
671 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
672
673static const char *drc_attack_text[] = {
674 "Reserved",
675 "181us",
676 "363us",
677 "726us",
678 "1.45ms",
679 "2.9ms",
680 "5.8ms",
681 "11.6ms",
682 "23.2ms",
683 "46.4ms",
684 "92.8ms",
685 "185.6ms",
686};
687
688static const struct soc_enum drc_attack =
689 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
690
691static const char *drc_decay_text[] = {
692 "186ms",
693 "372ms",
694 "743ms",
695 "1.49s",
696 "2.97ms",
697 "5.94ms",
698 "11.89ms",
699 "23.78ms",
700 "47.56ms",
701};
702
703static const struct soc_enum drc_decay =
704 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
705
706static const char *drc_ff_text[] = {
707 "5 samples",
708 "9 samples",
709};
710
711static const struct soc_enum drc_ff =
712 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
713
714static const char *drc_qr_rate_text[] = {
715 "0.725ms",
716 "1.45ms",
717 "5.8ms",
718};
719
720static const struct soc_enum drc_qr_rate =
721 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
722
723static const char *drc_smooth_text[] = {
724 "Low",
725 "Medium",
726 "High",
727};
728
729static const struct soc_enum drc_smooth =
730 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
731
732
733/*
734 * Update the DC servo calibration on gain changes
735 */
736static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
737 struct snd_ctl_elem_value *ucontrol)
738{
739 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
740 int ret;
741
742 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
743
744 /* Only need to do this if the outputs are active */
745 if (wm8993_read(codec, WM8993_POWER_MANAGEMENT_1)
746 & (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
747 snd_soc_update_bits(codec,
748 WM8993_DC_SERVO_0,
749 WM8993_DCS_TRIG_SINGLE_0 |
750 WM8993_DCS_TRIG_SINGLE_1,
751 WM8993_DCS_TRIG_SINGLE_0 |
752 WM8993_DCS_TRIG_SINGLE_1);
753
754 return ret;
755}
756
757static const struct snd_kcontrol_new wm8993_snd_controls[] = {
758SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
759 inpga_tlv),
760SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
761SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 0),
762
763SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
764 inpga_tlv),
765SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
766SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 0),
767
768
769SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
770 inpga_tlv),
771SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
772SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 0),
773
774SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
775 inpga_tlv),
776SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
777SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 0),
778
779SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
780 inmix_sw_tlv),
781SOC_SINGLE_TLV("MIXINL IN1L Volume", WM8993_INPUT_MIXER3, 4, 1, 0,
782 inmix_sw_tlv),
783SOC_SINGLE_TLV("MIXINL Output Record Volume", WM8993_INPUT_MIXER3, 0, 7, 0,
784 inmix_tlv),
785SOC_SINGLE_TLV("MIXINL IN1LP Volume", WM8993_INPUT_MIXER5, 6, 7, 0, inmix_tlv),
786SOC_SINGLE_TLV("MIXINL Direct Voice Volume", WM8993_INPUT_MIXER5, 0, 6, 0,
787 inmix_tlv),
788
789SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8993_INPUT_MIXER4, 7, 1, 0,
790 inmix_sw_tlv),
791SOC_SINGLE_TLV("MIXINR IN1R Volume", WM8993_INPUT_MIXER4, 4, 1, 0,
792 inmix_sw_tlv),
793SOC_SINGLE_TLV("MIXINR Output Record Volume", WM8993_INPUT_MIXER4, 0, 7, 0,
794 inmix_tlv),
795SOC_SINGLE_TLV("MIXINR IN1RP Volume", WM8993_INPUT_MIXER6, 6, 7, 0, inmix_tlv),
796SOC_SINGLE_TLV("MIXINR Direct Voice Volume", WM8993_INPUT_MIXER6, 0, 6, 0,
797 inmix_tlv),
798
799SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
800 5, 9, 12, 0, sidetone_tlv),
801
802SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
803SOC_ENUM("DRC Path", drc_path),
804SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8993_DRC_CONTROL_2,
805 2, 60, 1, drc_comp_threash),
806SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
807 11, 30, 1, drc_comp_amp),
808SOC_ENUM("DRC R0", drc_r0),
809SOC_ENUM("DRC R1", drc_r1),
810SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
811 drc_min_tlv),
812SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
813 drc_max_tlv),
814SOC_ENUM("DRC Attack Rate", drc_attack),
815SOC_ENUM("DRC Decay Rate", drc_decay),
816SOC_ENUM("DRC FF Delay", drc_ff),
817SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
818SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
819SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
820 drc_qr_tlv),
821SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
822SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
823SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
824SOC_ENUM("DRC Smoothing Hysteresis Threashold", drc_smooth),
825SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
826 drc_startup_tlv),
827
828SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
829
830SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
831 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
832SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
833SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
834
835SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
836 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
837SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
838 dac_boost_tlv),
839SOC_ENUM("DAC Deemphasis", dac_deemph),
840
841SOC_SINGLE_TLV("Left Output Mixer IN2RN Volume", WM8993_OUTPUT_MIXER5, 6, 7, 1,
842 outmix_tlv),
843SOC_SINGLE_TLV("Left Output Mixer IN2LN Volume", WM8993_OUTPUT_MIXER3, 6, 7, 1,
844 outmix_tlv),
845SOC_SINGLE_TLV("Left Output Mixer IN2LP Volume", WM8993_OUTPUT_MIXER3, 9, 7, 1,
846 outmix_tlv),
847SOC_SINGLE_TLV("Left Output Mixer IN1L Volume", WM8993_OUTPUT_MIXER3, 0, 7, 1,
848 outmix_tlv),
849SOC_SINGLE_TLV("Left Output Mixer IN1R Volume", WM8993_OUTPUT_MIXER3, 3, 7, 1,
850 outmix_tlv),
851SOC_SINGLE_TLV("Left Output Mixer Right Input Volume",
852 WM8993_OUTPUT_MIXER5, 3, 7, 1, outmix_tlv),
853SOC_SINGLE_TLV("Left Output Mixer Left Input Volume",
854 WM8993_OUTPUT_MIXER5, 0, 7, 1, outmix_tlv),
855SOC_SINGLE_TLV("Left Output Mixer DAC Volume", WM8993_OUTPUT_MIXER5, 9, 7, 1,
856 outmix_tlv),
857
858SOC_SINGLE_TLV("Right Output Mixer IN2LN Volume",
859 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
860SOC_SINGLE_TLV("Right Output Mixer IN2RN Volume",
861 WM8993_OUTPUT_MIXER4, 6, 7, 1, outmix_tlv),
862SOC_SINGLE_TLV("Right Output Mixer IN1L Volume",
863 WM8993_OUTPUT_MIXER4, 3, 7, 1, outmix_tlv),
864SOC_SINGLE_TLV("Right Output Mixer IN1R Volume",
865 WM8993_OUTPUT_MIXER4, 0, 7, 1, outmix_tlv),
866SOC_SINGLE_TLV("Right Output Mixer IN2RP Volume",
867 WM8993_OUTPUT_MIXER4, 9, 7, 1, outmix_tlv),
868SOC_SINGLE_TLV("Right Output Mixer Left Input Volume",
869 WM8993_OUTPUT_MIXER6, 3, 7, 1, outmix_tlv),
870SOC_SINGLE_TLV("Right Output Mixer Right Input Volume",
871 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
872SOC_SINGLE_TLV("Right Output Mixer DAC Volume",
873 WM8993_OUTPUT_MIXER6, 9, 7, 1, outmix_tlv),
874
875SOC_DOUBLE_R_TLV("Output Volume", WM8993_LEFT_OPGA_VOLUME,
876 WM8993_RIGHT_OPGA_VOLUME, 0, 63, 0, outpga_tlv),
877SOC_DOUBLE_R("Output Switch", WM8993_LEFT_OPGA_VOLUME,
878 WM8993_RIGHT_OPGA_VOLUME, 6, 1, 0),
879SOC_DOUBLE_R("Output ZC Switch", WM8993_LEFT_OPGA_VOLUME,
880 WM8993_RIGHT_OPGA_VOLUME, 7, 1, 0),
881
882SOC_SINGLE("Earpiece Switch", WM8993_HPOUT2_VOLUME, 5, 1, 1),
883SOC_SINGLE_TLV("Earpiece Volume", WM8993_HPOUT2_VOLUME, 4, 1, 1, earpiece_tlv),
884
885SOC_SINGLE_TLV("SPKL Input Volume", WM8993_SPKMIXL_ATTENUATION,
886 5, 1, 1, spkmix_tlv),
887SOC_SINGLE_TLV("SPKL IN1LP Volume", WM8993_SPKMIXL_ATTENUATION,
888 4, 1, 1, spkmix_tlv),
889SOC_SINGLE_TLV("SPKL Output Volume", WM8993_SPKMIXL_ATTENUATION,
890 3, 1, 1, spkmix_tlv),
891SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
892 2, 1, 1, spkmix_tlv),
893
894SOC_SINGLE_TLV("SPKR Input Volume", WM8993_SPKMIXR_ATTENUATION,
895 5, 1, 1, spkmix_tlv),
896SOC_SINGLE_TLV("SPKR IN1RP Volume", WM8993_SPKMIXR_ATTENUATION,
897 4, 1, 1, spkmix_tlv),
898SOC_SINGLE_TLV("SPKR Output Volume", WM8993_SPKMIXR_ATTENUATION,
899 3, 1, 1, spkmix_tlv),
900SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
901 2, 1, 1, spkmix_tlv),
902
903SOC_DOUBLE_R_TLV("Speaker Mixer Volume",
904 WM8993_SPKMIXL_ATTENUATION, WM8993_SPKMIXR_ATTENUATION,
905 0, 3, 1, spkmixout_tlv),
906SOC_DOUBLE_R_TLV("Speaker Volume",
907 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
908 0, 63, 0, outpga_tlv),
909SOC_DOUBLE_R("Speaker Switch",
910 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
911 6, 1, 0),
912SOC_DOUBLE_R("Speaker ZC Switch",
913 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
914 7, 1, 0),
915SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 0, 3, 7, 0,
916 spkboost_tlv),
917SOC_ENUM("Speaker Reference", speaker_ref),
918SOC_ENUM("Speaker Mode", speaker_mode),
919
920{
921 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphone Volume",
922 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
923 SNDRV_CTL_ELEM_ACCESS_READWRITE,
924 .tlv.p = outpga_tlv,
925 .info = snd_soc_info_volsw_2r,
926 .get = snd_soc_get_volsw_2r, .put = wm8993_put_dc_servo,
927 .private_value = (unsigned long)&(struct soc_mixer_control) {
928 .reg = WM8993_LEFT_OUTPUT_VOLUME,
929 .rreg = WM8993_RIGHT_OUTPUT_VOLUME,
930 .shift = 0, .max = 63
931 },
932},
933SOC_DOUBLE_R("Headphone Switch", WM8993_LEFT_OUTPUT_VOLUME,
934 WM8993_RIGHT_OUTPUT_VOLUME, 6, 1, 0),
935SOC_DOUBLE_R("Headphone ZC Switch", WM8993_LEFT_OUTPUT_VOLUME,
936 WM8993_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
937
938SOC_SINGLE("LINEOUT1N Switch", WM8993_LINE_OUTPUTS_VOLUME, 6, 1, 1),
939SOC_SINGLE("LINEOUT1P Switch", WM8993_LINE_OUTPUTS_VOLUME, 5, 1, 1),
940SOC_SINGLE_TLV("LINEOUT1 Volume", WM8993_LINE_OUTPUTS_VOLUME, 4, 1, 1,
941 line_tlv),
942
943SOC_SINGLE("LINEOUT2N Switch", WM8993_LINE_OUTPUTS_VOLUME, 2, 1, 1),
944SOC_SINGLE("LINEOUT2P Switch", WM8993_LINE_OUTPUTS_VOLUME, 1, 1, 1),
945SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
946 line_tlv),
947};
948
949static const struct snd_kcontrol_new wm8993_eq_controls[] = {
950SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
951SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
952SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
953SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
954SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
955};
956
957static int wm8993_earpiece_event(struct snd_soc_dapm_widget *w,
958 struct snd_kcontrol *control, int event)
959{
960 struct snd_soc_codec *codec = w->codec;
961 u16 reg = wm8993_read(codec, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA;
962
963 switch (event) {
964 case SND_SOC_DAPM_PRE_PMU:
965 reg |= WM8993_HPOUT2_IN_ENA;
966 wm8993_write(codec, WM8993_ANTIPOP1, reg);
967 udelay(50);
968 break;
969
970 case SND_SOC_DAPM_POST_PMD:
971 wm8993_write(codec, WM8993_ANTIPOP1, reg);
972 break;
973
974 default:
975 BUG();
976 break;
977 }
978
979 return 0;
980}
981
982static int clk_sys_event(struct snd_soc_dapm_widget *w,
983 struct snd_kcontrol *kcontrol, int event)
984{
985 struct snd_soc_codec *codec = w->codec;
986
987 switch (event) {
988 case SND_SOC_DAPM_PRE_PMU:
989 return configure_clock(codec);
990
991 case SND_SOC_DAPM_POST_PMD:
992 break;
993 }
994
995 return 0;
996}
997
998/*
999 * When used with DAC outputs only the WM8993 charge pump supports
1000 * operation in class W mode, providing very low power consumption
1001 * when used with digital sources. Enable and disable this mode
1002 * automatically depending on the mixer configuration.
1003 *
1004 * Currently the only supported paths are the direct DAC->headphone
1005 * paths (which provide minimum power consumption anyway).
1006 */
1007static int wm8993_class_w_put(struct snd_kcontrol *kcontrol,
1008 struct snd_ctl_elem_value *ucontrol)
1009{
1010 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
1011 struct snd_soc_codec *codec = widget->codec;
1012 struct wm8993_priv *wm8993 = codec->private_data;
1013 int ret;
1014
1015 /* Turn it off if we're using the main output mixer */
1016 if (ucontrol->value.integer.value[0] == 0) {
1017 if (wm8993->class_w_users == 0) {
1018 dev_dbg(codec->dev, "Disabling Class W\n");
1019 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
1020 WM8993_CP_DYN_FREQ |
1021 WM8993_CP_DYN_V,
1022 0);
1023 }
1024 wm8993->class_w_users++;
1025 }
1026
1027 /* Implement the change */
1028 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1029
1030 /* Enable it if we're using the direct DAC path */
1031 if (ucontrol->value.integer.value[0] == 1) {
1032 if (wm8993->class_w_users == 1) {
1033 dev_dbg(codec->dev, "Enabling Class W\n");
1034 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
1035 WM8993_CP_DYN_FREQ |
1036 WM8993_CP_DYN_V,
1037 WM8993_CP_DYN_FREQ |
1038 WM8993_CP_DYN_V);
1039 }
1040 wm8993->class_w_users--;
1041 }
1042
1043 dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
1044 wm8993->class_w_users);
1045
1046 return ret;
1047}
1048
1049#define SOC_DAPM_ENUM_W(xname, xenum) \
1050{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1051 .info = snd_soc_info_enum_double, \
1052 .get = snd_soc_dapm_get_enum_double, \
1053 .put = wm8993_class_w_put, \
1054 .private_value = (unsigned long)&xenum }
1055
1056static int hp_event(struct snd_soc_dapm_widget *w,
1057 struct snd_kcontrol *kcontrol, int event)
1058{
1059 struct snd_soc_codec *codec = w->codec;
1060 unsigned int reg = wm8993_read(codec, WM8993_ANALOGUE_HP_0);
1061
1062 switch (event) {
1063 case SND_SOC_DAPM_POST_PMU:
1064 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
1065 WM8993_CP_ENA, WM8993_CP_ENA);
1066
1067 msleep(5);
1068
1069 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1070 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
1071 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA);
1072
1073 reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
1074 wm8993_write(codec, WM8993_ANALOGUE_HP_0, reg);
1075
1076 /* Start the DC servo */
1077 snd_soc_update_bits(codec, WM8993_DC_SERVO_0,
1078 WM8993_DCS_ENA_CHAN_0 |
1079 WM8993_DCS_ENA_CHAN_1 |
1080 WM8993_DCS_TRIG_STARTUP_1 |
1081 WM8993_DCS_TRIG_STARTUP_0,
1082 WM8993_DCS_ENA_CHAN_0 |
1083 WM8993_DCS_ENA_CHAN_1 |
1084 WM8993_DCS_TRIG_STARTUP_1 |
1085 WM8993_DCS_TRIG_STARTUP_0);
1086 wait_for_dc_servo(codec, WM8993_DCS_TRIG_STARTUP_0 |
1087 WM8993_DCS_TRIG_STARTUP_1);
1088 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
1089 WM8993_DCS_TIMER_PERIOD_01_MASK, 0xa);
1090
1091 reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
1092 WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
1093 wm8993_write(codec, WM8993_ANALOGUE_HP_0, reg);
1094 break;
1095
1096 case SND_SOC_DAPM_PRE_PMD:
1097 reg &= ~(WM8993_HPOUT1L_RMV_SHORT |
1098 WM8993_HPOUT1L_DLY |
1099 WM8993_HPOUT1L_OUTP |
1100 WM8993_HPOUT1R_RMV_SHORT |
1101 WM8993_HPOUT1R_DLY |
1102 WM8993_HPOUT1R_OUTP);
1103
1104 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
1105 WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
1106 snd_soc_update_bits(codec, WM8993_DC_SERVO_0,
1107 WM8993_DCS_ENA_CHAN_0 |
1108 WM8993_DCS_ENA_CHAN_1, 0);
1109
1110 wm8993_write(codec, WM8993_ANALOGUE_HP_0, reg);
1111 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1112 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
1113 0);
1114
1115 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
1116 WM8993_CP_ENA, 0);
1117 break;
1118 }
1119
1120 return 0;
1121}
1122
1123static const struct snd_kcontrol_new in1l_pga[] = {
1124SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
1125SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
1126};
1127
1128static const struct snd_kcontrol_new in1r_pga[] = {
1129SOC_DAPM_SINGLE("IN1RP Switch", WM8993_INPUT_MIXER2, 1, 1, 0),
1130SOC_DAPM_SINGLE("IN1RN Switch", WM8993_INPUT_MIXER2, 0, 1, 0),
1131};
1132
1133static const struct snd_kcontrol_new in2l_pga[] = {
1134SOC_DAPM_SINGLE("IN2LP Switch", WM8993_INPUT_MIXER2, 7, 1, 0),
1135SOC_DAPM_SINGLE("IN2LN Switch", WM8993_INPUT_MIXER2, 6, 1, 0),
1136};
1137
1138static const struct snd_kcontrol_new in2r_pga[] = {
1139SOC_DAPM_SINGLE("IN2RP Switch", WM8993_INPUT_MIXER2, 3, 1, 0),
1140SOC_DAPM_SINGLE("IN2RN Switch", WM8993_INPUT_MIXER2, 2, 1, 0),
1141};
1142
1143static const struct snd_kcontrol_new mixinl[] = {
1144SOC_DAPM_SINGLE("IN2L Switch", WM8993_INPUT_MIXER3, 8, 1, 0),
1145SOC_DAPM_SINGLE("IN1L Switch", WM8993_INPUT_MIXER3, 5, 1, 0),
1146};
1147
1148static const struct snd_kcontrol_new mixinr[] = {
1149SOC_DAPM_SINGLE("IN2R Switch", WM8993_INPUT_MIXER4, 8, 1, 0),
1150SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
1151};
1152
1153static const struct snd_kcontrol_new left_output_mixer[] = {
1154SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
1155SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
1156SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
1157SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
1158SOC_DAPM_SINGLE("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
1159SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
1160SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
1161SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
1162};
1163
1164static const struct snd_kcontrol_new right_output_mixer[] = {
1165SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
1166SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
1167SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
1168SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
1169SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
1170SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
1171SOC_DAPM_SINGLE("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
1172SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
1173};
1174
1175static const struct snd_kcontrol_new earpiece_mixer[] = {
1176SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_HPOUT2_MIXER, 5, 1, 0),
1177SOC_DAPM_SINGLE("Left Output Switch", WM8993_HPOUT2_MIXER, 4, 1, 0),
1178SOC_DAPM_SINGLE("Right Output Switch", WM8993_HPOUT2_MIXER, 3, 1, 0),
1179};
1180
1181static const struct snd_kcontrol_new left_speaker_mixer[] = {
1182SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
1183SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
1184SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
1185SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
1186};
1187
1188static const struct snd_kcontrol_new right_speaker_mixer[] = {
1189SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
1190SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
1191SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
1192SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
1193};
1194
1195static const struct snd_kcontrol_new left_speaker_boost[] = {
1196SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 5, 1, 0),
1197SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 4, 1, 0),
1198SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 3, 1, 0),
1199};
1200
1201static const struct snd_kcontrol_new right_speaker_boost[] = {
1202SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 2, 1, 0),
1203SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 1, 1, 0),
1204SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 0, 1, 0),
1205};
1206
1207static const char *hp_mux_text[] = {
1208 "Mixer",
1209 "DAC",
1210};
1211
1212static const struct soc_enum hpl_enum =
1213 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
1214
1215static const struct snd_kcontrol_new hpl_mux =
1216 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
1217
1218static const struct soc_enum hpr_enum =
1219 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
1220
1221static const struct snd_kcontrol_new hpr_mux =
1222 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
1223
1224static const struct snd_kcontrol_new line1_mix[] = {
1225SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER1, 2, 1, 0),
1226SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER1, 1, 1, 0),
1227SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
1228};
1229
1230static const struct snd_kcontrol_new line1n_mix[] = {
1231SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 6, 1, 0),
1232SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER1, 5, 1, 0),
1233};
1234
1235static const struct snd_kcontrol_new line1p_mix[] = {
1236SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
1237};
1238
1239static const struct snd_kcontrol_new line2_mix[] = {
1240SOC_DAPM_SINGLE("IN2R Switch", WM8993_LINE_MIXER2, 2, 1, 0),
1241SOC_DAPM_SINGLE("IN2L Switch", WM8993_LINE_MIXER2, 1, 1, 0),
1242SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
1243};
1244
1245static const struct snd_kcontrol_new line2n_mix[] = {
1246SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER2, 6, 1, 0),
1247SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 5, 1, 0),
1248};
1249
1250static const struct snd_kcontrol_new line2p_mix[] = {
1251SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
1252};
1253
1254static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
1255SND_SOC_DAPM_INPUT("IN1LN"),
1256SND_SOC_DAPM_INPUT("IN1LP"),
1257SND_SOC_DAPM_INPUT("IN2LN"),
1258SND_SOC_DAPM_INPUT("IN2LP/VXRN"),
1259SND_SOC_DAPM_INPUT("IN1RN"),
1260SND_SOC_DAPM_INPUT("IN1RP"),
1261SND_SOC_DAPM_INPUT("IN2RN"),
1262SND_SOC_DAPM_INPUT("IN2RP/VXRP"),
1263
1264SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
1265 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1266SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
1267SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
1268
1269SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0),
1270SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0),
1271
1272SND_SOC_DAPM_MIXER("IN1L PGA", WM8993_POWER_MANAGEMENT_2, 6, 0,
1273 in1l_pga, ARRAY_SIZE(in1l_pga)),
1274SND_SOC_DAPM_MIXER("IN1R PGA", WM8993_POWER_MANAGEMENT_2, 4, 0,
1275 in1r_pga, ARRAY_SIZE(in1r_pga)),
1276
1277SND_SOC_DAPM_MIXER("IN2L PGA", WM8993_POWER_MANAGEMENT_2, 7, 0,
1278 in2l_pga, ARRAY_SIZE(in2l_pga)),
1279SND_SOC_DAPM_MIXER("IN2R PGA", WM8993_POWER_MANAGEMENT_2, 5, 0,
1280 in2r_pga, ARRAY_SIZE(in2r_pga)),
1281
1282/* Dummy widgets to represent differential paths */
1283SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1284
1285SND_SOC_DAPM_MIXER("MIXINL", WM8993_POWER_MANAGEMENT_2, 9, 0,
1286 mixinl, ARRAY_SIZE(mixinl)),
1287SND_SOC_DAPM_MIXER("MIXINR", WM8993_POWER_MANAGEMENT_2, 8, 0,
1288 mixinr, ARRAY_SIZE(mixinr)),
1289
1290SND_SOC_DAPM_ADC("ADCL", "Capture", WM8993_POWER_MANAGEMENT_2, 1, 0),
1291SND_SOC_DAPM_ADC("ADCR", "Capture", WM8993_POWER_MANAGEMENT_2, 0, 0),
1292
1293SND_SOC_DAPM_DAC("DACL", "Playback", WM8993_POWER_MANAGEMENT_3, 1, 0),
1294SND_SOC_DAPM_DAC("DACR", "Playback", WM8993_POWER_MANAGEMENT_3, 0, 0),
1295
1296SND_SOC_DAPM_MIXER("Left Output Mixer", WM8993_POWER_MANAGEMENT_3, 5, 0,
1297 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
1298SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
1299 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
1300
1301SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
1302SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
1303
1304SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1305 earpiece_mixer, ARRAY_SIZE(earpiece_mixer)),
1306SND_SOC_DAPM_PGA_E("Earpiece Driver", WM8993_POWER_MANAGEMENT_1, 11, 0,
1307 NULL, 0, wm8993_earpiece_event,
1308 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1309
1310SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
1311 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1312SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
1313 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1314
1315SND_SOC_DAPM_MIXER("SPKL Boost", SND_SOC_NOPM, 0, 0,
1316 left_speaker_boost, ARRAY_SIZE(left_speaker_boost)),
1317SND_SOC_DAPM_MIXER("SPKR Boost", SND_SOC_NOPM, 0, 0,
1318 right_speaker_boost, ARRAY_SIZE(right_speaker_boost)),
1319
1320SND_SOC_DAPM_PGA("SPKL Driver", WM8993_POWER_MANAGEMENT_1, 12, 0,
1321 NULL, 0),
1322SND_SOC_DAPM_PGA("SPKR Driver", WM8993_POWER_MANAGEMENT_1, 13, 0,
1323 NULL, 0),
1324
1325SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1326SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1327SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0,
1328 NULL, 0,
1329 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1330
1331SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
1332 line1_mix, ARRAY_SIZE(line1_mix)),
1333SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
1334 line2_mix, ARRAY_SIZE(line2_mix)),
1335
1336SND_SOC_DAPM_MIXER("LINEOUT1N Mixer", SND_SOC_NOPM, 0, 0,
1337 line1n_mix, ARRAY_SIZE(line1n_mix)),
1338SND_SOC_DAPM_MIXER("LINEOUT1P Mixer", SND_SOC_NOPM, 0, 0,
1339 line1p_mix, ARRAY_SIZE(line1p_mix)),
1340SND_SOC_DAPM_MIXER("LINEOUT2N Mixer", SND_SOC_NOPM, 0, 0,
1341 line2n_mix, ARRAY_SIZE(line2n_mix)),
1342SND_SOC_DAPM_MIXER("LINEOUT2P Mixer", SND_SOC_NOPM, 0, 0,
1343 line2p_mix, ARRAY_SIZE(line2p_mix)),
1344
1345SND_SOC_DAPM_PGA("LINEOUT1N Driver", WM8993_POWER_MANAGEMENT_3, 13, 0,
1346 NULL, 0),
1347SND_SOC_DAPM_PGA("LINEOUT1P Driver", WM8993_POWER_MANAGEMENT_3, 12, 0,
1348 NULL, 0),
1349SND_SOC_DAPM_PGA("LINEOUT2N Driver", WM8993_POWER_MANAGEMENT_3, 11, 0,
1350 NULL, 0),
1351SND_SOC_DAPM_PGA("LINEOUT2P Driver", WM8993_POWER_MANAGEMENT_3, 10, 0,
1352 NULL, 0),
1353
1354SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
1355SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
1356SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
1357SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
1358SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1359SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1360SND_SOC_DAPM_OUTPUT("HPOUT2P"),
1361SND_SOC_DAPM_OUTPUT("HPOUT2N"),
1362SND_SOC_DAPM_OUTPUT("LINEOUT1P"),
1363SND_SOC_DAPM_OUTPUT("LINEOUT1N"),
1364SND_SOC_DAPM_OUTPUT("LINEOUT2P"),
1365SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
1366};
1367
1368static const struct snd_soc_dapm_route routes[] = {
1369 { "IN1L PGA", "IN1LP Switch", "IN1LP" },
1370 { "IN1L PGA", "IN1LN Switch", "IN1LN" },
1371
1372 { "IN1R PGA", "IN1RP Switch", "IN1RP" },
1373 { "IN1R PGA", "IN1RN Switch", "IN1RN" },
1374
1375 { "IN2L PGA", "IN2LP Switch", "IN2LP/VXRN" },
1376 { "IN2L PGA", "IN2LN Switch", "IN2LN" },
1377
1378 { "IN2R PGA", "IN2RP Switch", "IN2RP/VXRP" },
1379 { "IN2R PGA", "IN2RN Switch", "IN2RN" },
1380
1381 { "Direct Voice", NULL, "IN2LP/VXRN" },
1382 { "Direct Voice", NULL, "IN2RP/VXRP" },
1383
1384 { "MIXINL", "IN1L Switch", "IN1L PGA" },
1385 { "MIXINL", "IN2L Switch", "IN2L PGA" },
1386 { "MIXINL", NULL, "Direct Voice" },
1387 { "MIXINL", NULL, "IN1LP" },
1388 { "MIXINL", NULL, "Left Output Mixer" },
1389
1390 { "MIXINR", "IN1R Switch", "IN1R PGA" },
1391 { "MIXINR", "IN2R Switch", "IN2R PGA" },
1392 { "MIXINR", NULL, "Direct Voice" },
1393 { "MIXINR", NULL, "IN1RP" },
1394 { "MIXINR", NULL, "Right Output Mixer" },
1395
1396 { "ADCL", NULL, "MIXINL" },
1397 { "ADCL", NULL, "CLK_SYS" },
1398 { "ADCL", NULL, "CLK_DSP" },
1399 { "ADCR", NULL, "MIXINR" },
1400 { "ADCR", NULL, "CLK_SYS" },
1401 { "ADCR", NULL, "CLK_DSP" },
1402
1403 { "DACL", NULL, "CLK_SYS" },
1404 { "DACL", NULL, "CLK_DSP" },
1405 { "DACR", NULL, "CLK_SYS" },
1406 { "DACR", NULL, "CLK_DSP" },
1407
1408 { "Left Output Mixer", "Left Input Switch", "MIXINL" },
1409 { "Left Output Mixer", "Right Input Switch", "MIXINR" },
1410 { "Left Output Mixer", "IN2RN Switch", "IN2RN" },
1411 { "Left Output Mixer", "IN2LN Switch", "IN2LN" },
1412 { "Left Output Mixer", "IN2LP Switch", "IN2LP/VXRN" },
1413 { "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
1414 { "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
1415 { "Left Output Mixer", "DAC Switch", "DACL" },
1416
1417 { "Right Output Mixer", "Left Input Switch", "MIXINL" },
1418 { "Right Output Mixer", "Right Input Switch", "MIXINR" },
1419 { "Right Output Mixer", "IN2LN Switch", "IN2LN" },
1420 { "Right Output Mixer", "IN2RN Switch", "IN2RN" },
1421 { "Right Output Mixer", "IN2RP Switch", "IN2RP/VXRP" },
1422 { "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
1423 { "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
1424 { "Right Output Mixer", "DAC Switch", "DACR" },
1425
1426 { "Left Output PGA", NULL, "Left Output Mixer" },
1427 { "Left Output PGA", NULL, "CLK_SYS" },
1428 { "Left Output PGA", NULL, "TOCLK" },
1429
1430 { "Right Output PGA", NULL, "Right Output Mixer" },
1431 { "Right Output PGA", NULL, "CLK_SYS" },
1432 { "Right Output PGA", NULL, "TOCLK" },
1433
1434 { "Earpiece Mixer", "Direct Voice Switch", "Direct Voice" },
1435 { "Earpiece Mixer", "Left Output Switch", "Left Output PGA" },
1436 { "Earpiece Mixer", "Right Output Switch", "Right Output PGA" },
1437
1438 { "Earpiece Driver", NULL, "Earpiece Mixer" },
1439 { "HPOUT2N", NULL, "Earpiece Driver" },
1440 { "HPOUT2P", NULL, "Earpiece Driver" },
1441
1442 { "SPKL", "Input Switch", "MIXINL" },
1443 { "SPKL", "IN1LP Switch", "IN1LP" },
1444 { "SPKL", "Output Switch", "Left Output Mixer" },
1445 { "SPKL", "DAC Switch", "DACL" },
1446 { "SPKL", NULL, "CLK_SYS" },
1447 { "SPKL", NULL, "TOCLK" },
1448
1449 { "SPKR", "Input Switch", "MIXINR" },
1450 { "SPKR", "IN1RP Switch", "IN1RP" },
1451 { "SPKR", "Output Switch", "Right Output Mixer" },
1452 { "SPKR", "DAC Switch", "DACR" },
1453 { "SPKR", NULL, "CLK_SYS" },
1454 { "SPKR", NULL, "TOCLK" },
1455
1456 { "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
1457 { "SPKL Boost", "SPKL Switch", "SPKL" },
1458 { "SPKL Boost", "SPKR Switch", "SPKR" },
1459
1460 { "SPKR Boost", "Direct Voice Switch", "Direct Voice" },
1461 { "SPKR Boost", "SPKR Switch", "SPKR" },
1462 { "SPKR Boost", "SPKL Switch", "SPKL" },
1463
1464 { "SPKL Driver", NULL, "SPKL Boost" },
1465 { "SPKL Driver", NULL, "CLK_SYS" },
1466
1467 { "SPKR Driver", NULL, "SPKR Boost" },
1468 { "SPKR Driver", NULL, "CLK_SYS" },
1469
1470 { "SPKOUTLP", NULL, "SPKL Driver" },
1471 { "SPKOUTLN", NULL, "SPKL Driver" },
1472 { "SPKOUTRP", NULL, "SPKR Driver" },
1473 { "SPKOUTRN", NULL, "SPKR Driver" },
1474
1475 { "Left Headphone Mux", "DAC", "DACL" },
1476 { "Left Headphone Mux", "Mixer", "Left Output Mixer" },
1477 { "Right Headphone Mux", "DAC", "DACR" },
1478 { "Right Headphone Mux", "Mixer", "Right Output Mixer" },
1479
1480 { "Headphone PGA", NULL, "Left Headphone Mux" },
1481 { "Headphone PGA", NULL, "Right Headphone Mux" },
1482 { "Headphone PGA", NULL, "CLK_SYS" },
1483 { "Headphone PGA", NULL, "TOCLK" },
1484
1485 { "HPOUT1L", NULL, "Headphone PGA" },
1486 { "HPOUT1R", NULL, "Headphone PGA" },
1487
1488 { "LINEOUT1N", NULL, "LINEOUT1N Driver" },
1489 { "LINEOUT1P", NULL, "LINEOUT1P Driver" },
1490 { "LINEOUT2N", NULL, "LINEOUT2N Driver" },
1491 { "LINEOUT2P", NULL, "LINEOUT2P Driver" },
1492};
1493
1494static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
1495 { "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
1496 { "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
1497 { "LINEOUT1 Mixer", "Output Switch", "Left Output Mixer" },
1498
1499 { "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
1500 { "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
1501};
1502
1503static const struct snd_soc_dapm_route lineout1_se_routes[] = {
1504 { "LINEOUT1N Mixer", "Left Output Switch", "Left Output Mixer" },
1505 { "LINEOUT1N Mixer", "Right Output Switch", "Left Output Mixer" },
1506
1507 { "LINEOUT1P Mixer", "Left Output Switch", "Left Output Mixer" },
1508
1509 { "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
1510 { "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
1511};
1512
1513static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
1514 { "LINEOUT2 Mixer", "IN2L Switch", "IN2L PGA" },
1515 { "LINEOUT2 Mixer", "IN2R Switch", "IN2R PGA" },
1516 { "LINEOUT2 Mixer", "Output Switch", "Right Output Mixer" },
1517
1518 { "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
1519 { "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
1520};
1521
1522static const struct snd_soc_dapm_route lineout2_se_routes[] = {
1523 { "LINEOUT2N Mixer", "Left Output Switch", "Left Output Mixer" },
1524 { "LINEOUT2N Mixer", "Right Output Switch", "Left Output Mixer" },
1525
1526 { "LINEOUT2P Mixer", "Right Output Switch", "Right Output Mixer" },
1527
1528 { "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
1529 { "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
1530};
1531
1532static int wm8993_set_bias_level(struct snd_soc_codec *codec,
1533 enum snd_soc_bias_level level)
1534{
1535 struct wm8993_priv *wm8993 = codec->private_data;
1536
1537 switch (level) {
1538 case SND_SOC_BIAS_ON:
1539 case SND_SOC_BIAS_PREPARE:
1540 /* VMID=2*40k */
1541 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1542 WM8993_VMID_SEL_MASK, 0x2);
1543 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1544 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
1545 break;
1546
1547 case SND_SOC_BIAS_STANDBY:
1548 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1549 /* Bring up VMID with fast soft start */
1550 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1551 WM8993_STARTUP_BIAS_ENA |
1552 WM8993_VMID_BUF_ENA |
1553 WM8993_VMID_RAMP_MASK |
1554 WM8993_BIAS_SRC,
1555 WM8993_STARTUP_BIAS_ENA |
1556 WM8993_VMID_BUF_ENA |
1557 WM8993_VMID_RAMP_MASK |
1558 WM8993_BIAS_SRC);
1559
1560 /* If either line output is single ended we
1561 * need the VMID buffer */
1562 if (!wm8993->pdata.lineout1_diff ||
1563 !wm8993->pdata.lineout2_diff)
1564 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1565 WM8993_LINEOUT_VMID_BUF_ENA,
1566 WM8993_LINEOUT_VMID_BUF_ENA);
1567
1568 /* VMID=2*40k */
1569 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1570 WM8993_VMID_SEL_MASK |
1571 WM8993_BIAS_ENA,
1572 WM8993_BIAS_ENA | 0x2);
1573 msleep(32);
1574
1575 /* Switch to normal bias */
1576 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1577 WM8993_BIAS_SRC |
1578 WM8993_STARTUP_BIAS_ENA, 0);
1579 }
1580
1581 /* VMID=2*240k */
1582 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1583 WM8993_VMID_SEL_MASK, 0x4);
1584
1585 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1586 WM8993_TSHUT_ENA, 0);
1587 break;
1588
1589 case SND_SOC_BIAS_OFF:
1590 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1591 WM8993_LINEOUT_VMID_BUF_ENA, 0);
1592
1593 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1594 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1595 0);
1596 break;
1597 }
1598
1599 codec->bias_level = level;
1600
1601 return 0;
1602}
1603
1604static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1605 int clk_id, unsigned int freq, int dir)
1606{
1607 struct snd_soc_codec *codec = codec_dai->codec;
1608 struct wm8993_priv *wm8993 = codec->private_data;
1609
1610 switch (clk_id) {
1611 case WM8993_SYSCLK_MCLK:
1612 wm8993->mclk_rate = freq;
1613 case WM8993_SYSCLK_FLL:
1614 wm8993->sysclk_source = clk_id;
1615 break;
1616
1617 default:
1618 return -EINVAL;
1619 }
1620
1621 return 0;
1622}
1623
1624static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1625 unsigned int fmt)
1626{
1627 struct snd_soc_codec *codec = dai->codec;
1628 struct wm8993_priv *wm8993 = codec->private_data;
1629 unsigned int aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1);
1630 unsigned int aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4);
1631
1632 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1633 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1634 aif4 &= ~WM8993_LRCLK_DIR;
1635
1636 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1637 case SND_SOC_DAIFMT_CBS_CFS:
1638 wm8993->master = 0;
1639 break;
1640 case SND_SOC_DAIFMT_CBS_CFM:
1641 aif4 |= WM8993_LRCLK_DIR;
1642 wm8993->master = 1;
1643 break;
1644 case SND_SOC_DAIFMT_CBM_CFS:
1645 aif1 |= WM8993_BCLK_DIR;
1646 wm8993->master = 1;
1647 break;
1648 case SND_SOC_DAIFMT_CBM_CFM:
1649 aif1 |= WM8993_BCLK_DIR;
1650 aif4 |= WM8993_LRCLK_DIR;
1651 wm8993->master = 1;
1652 break;
1653 default:
1654 return -EINVAL;
1655 }
1656
1657 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1658 case SND_SOC_DAIFMT_DSP_B:
1659 aif1 |= WM8993_AIF_LRCLK_INV;
1660 case SND_SOC_DAIFMT_DSP_A:
1661 aif1 |= 0x18;
1662 break;
1663 case SND_SOC_DAIFMT_I2S:
1664 aif1 |= 0x10;
1665 break;
1666 case SND_SOC_DAIFMT_RIGHT_J:
1667 break;
1668 case SND_SOC_DAIFMT_LEFT_J:
1669 aif1 |= 0x8;
1670 break;
1671 default:
1672 return -EINVAL;
1673 }
1674
1675 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1676 case SND_SOC_DAIFMT_DSP_A:
1677 case SND_SOC_DAIFMT_DSP_B:
1678 /* frame inversion not valid for DSP modes */
1679 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1680 case SND_SOC_DAIFMT_NB_NF:
1681 break;
1682 case SND_SOC_DAIFMT_IB_NF:
1683 aif1 |= WM8993_AIF_BCLK_INV;
1684 break;
1685 default:
1686 return -EINVAL;
1687 }
1688 break;
1689
1690 case SND_SOC_DAIFMT_I2S:
1691 case SND_SOC_DAIFMT_RIGHT_J:
1692 case SND_SOC_DAIFMT_LEFT_J:
1693 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1694 case SND_SOC_DAIFMT_NB_NF:
1695 break;
1696 case SND_SOC_DAIFMT_IB_IF:
1697 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1698 break;
1699 case SND_SOC_DAIFMT_IB_NF:
1700 aif1 |= WM8993_AIF_BCLK_INV;
1701 break;
1702 case SND_SOC_DAIFMT_NB_IF:
1703 aif1 |= WM8993_AIF_LRCLK_INV;
1704 break;
1705 default:
1706 return -EINVAL;
1707 }
1708 break;
1709 default:
1710 return -EINVAL;
1711 }
1712
1713 wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1714 wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1715
1716 return 0;
1717}
1718
1719static int wm8993_hw_params(struct snd_pcm_substream *substream,
1720 struct snd_pcm_hw_params *params,
1721 struct snd_soc_dai *dai)
1722{
1723 struct snd_soc_codec *codec = dai->codec;
1724 struct wm8993_priv *wm8993 = codec->private_data;
1725 int ret, i, best, best_val, cur_val;
1726 unsigned int clocking1, clocking3, aif1, aif4;
1727
1728 clocking1 = wm8993_read(codec, WM8993_CLOCKING_1);
1729 clocking1 &= ~WM8993_BCLK_DIV_MASK;
1730
1731 clocking3 = wm8993_read(codec, WM8993_CLOCKING_3);
1732 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1733
1734 aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1);
1735 aif1 &= ~WM8993_AIF_WL_MASK;
1736
1737 aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4);
1738 aif4 &= ~WM8993_LRCLK_RATE_MASK;
1739
1740 /* What BCLK do we need? */
1741 wm8993->fs = params_rate(params);
1742 wm8993->bclk = 2 * wm8993->fs;
1743 switch (params_format(params)) {
1744 case SNDRV_PCM_FORMAT_S16_LE:
1745 wm8993->bclk *= 16;
1746 break;
1747 case SNDRV_PCM_FORMAT_S20_3LE:
1748 wm8993->bclk *= 20;
1749 aif1 |= 0x8;
1750 break;
1751 case SNDRV_PCM_FORMAT_S24_LE:
1752 wm8993->bclk *= 24;
1753 aif1 |= 0x10;
1754 break;
1755 case SNDRV_PCM_FORMAT_S32_LE:
1756 wm8993->bclk *= 32;
1757 aif1 |= 0x18;
1758 break;
1759 default:
1760 return -EINVAL;
1761 }
1762
1763 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1764
1765 ret = configure_clock(codec);
1766 if (ret != 0)
1767 return ret;
1768
1769 /* Select nearest CLK_SYS_RATE */
1770 best = 0;
1771 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1772 - wm8993->fs);
1773 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1774 cur_val = abs((wm8993->sysclk_rate /
1775 clk_sys_rates[i].ratio) - wm8993->fs);;
1776 if (cur_val < best_val) {
1777 best = i;
1778 best_val = cur_val;
1779 }
1780 }
1781 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1782 clk_sys_rates[best].ratio);
1783 clocking3 |= (clk_sys_rates[best].clk_sys_rate
1784 << WM8993_CLK_SYS_RATE_SHIFT);
1785
1786 /* SAMPLE_RATE */
1787 best = 0;
1788 best_val = abs(wm8993->fs - sample_rates[0].rate);
1789 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1790 /* Closest match */
1791 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1792 if (cur_val < best_val) {
1793 best = i;
1794 best_val = cur_val;
1795 }
1796 }
1797 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1798 sample_rates[best].rate);
1799 clocking3 |= (sample_rates[i].sample_rate << WM8993_SAMPLE_RATE_SHIFT);
1800
1801 /* BCLK_DIV */
1802 best = 0;
1803 best_val = INT_MAX;
1804 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1805 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1806 - wm8993->bclk;
1807 if (cur_val < 0) /* Table is sorted */
1808 break;
1809 if (cur_val < best_val) {
1810 best = i;
1811 best_val = cur_val;
1812 }
1813 }
1814 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1815 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1816 bclk_divs[best].div, wm8993->bclk);
1817 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1818
1819 /* LRCLK is a simple fraction of BCLK */
1820 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1821 aif4 |= wm8993->bclk / wm8993->fs;
1822
1823 wm8993_write(codec, WM8993_CLOCKING_1, clocking1);
1824 wm8993_write(codec, WM8993_CLOCKING_3, clocking3);
1825 wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1826 wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1827
1828 /* ReTune Mobile? */
1829 if (wm8993->pdata.num_retune_configs) {
1830 u16 eq1 = wm8993_read(codec, WM8993_EQ1);
1831 struct wm8993_retune_mobile_setting *s;
1832
1833 best = 0;
1834 best_val = abs(wm8993->pdata.retune_configs[0].rate
1835 - wm8993->fs);
1836 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1837 cur_val = abs(wm8993->pdata.retune_configs[i].rate
1838 - wm8993->fs);
1839 if (cur_val < best_val) {
1840 best_val = cur_val;
1841 best = i;
1842 }
1843 }
1844 s = &wm8993->pdata.retune_configs[best];
1845
1846 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1847 s->name, s->rate);
1848
1849 /* Disable EQ while we reconfigure */
1850 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1851
1852 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1853 wm8993_write(codec, WM8993_EQ1 + i, s->config[i]);
1854
1855 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1856 }
1857
1858 return 0;
1859}
1860
1861static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1862{
1863 struct snd_soc_codec *codec = codec_dai->codec;
1864 unsigned int reg;
1865
1866 reg = wm8993_read(codec, WM8993_DAC_CTRL);
1867
1868 if (mute)
1869 reg |= WM8993_DAC_MUTE;
1870 else
1871 reg &= ~WM8993_DAC_MUTE;
1872
1873 wm8993_write(codec, WM8993_DAC_CTRL, reg);
1874
1875 return 0;
1876}
1877
1878static struct snd_soc_dai_ops wm8993_ops = {
1879 .set_sysclk = wm8993_set_sysclk,
1880 .set_fmt = wm8993_set_dai_fmt,
1881 .hw_params = wm8993_hw_params,
1882 .digital_mute = wm8993_digital_mute,
1883 .set_pll = wm8993_set_fll,
1884};
1885
1886#define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1887
1888#define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1889 SNDRV_PCM_FMTBIT_S20_3LE |\
1890 SNDRV_PCM_FMTBIT_S24_LE |\
1891 SNDRV_PCM_FMTBIT_S32_LE)
1892
1893struct snd_soc_dai wm8993_dai = {
1894 .name = "WM8993",
1895 .playback = {
1896 .stream_name = "Playback",
1897 .channels_min = 1,
1898 .channels_max = 2,
1899 .rates = WM8993_RATES,
1900 .formats = WM8993_FORMATS,
1901 },
1902 .capture = {
1903 .stream_name = "Capture",
1904 .channels_min = 1,
1905 .channels_max = 2,
1906 .rates = WM8993_RATES,
1907 .formats = WM8993_FORMATS,
1908 },
1909 .ops = &wm8993_ops,
1910 .symmetric_rates = 1,
1911};
1912EXPORT_SYMBOL_GPL(wm8993_dai);
1913
1914static struct snd_soc_codec *wm8993_codec;
1915
1916static int wm8993_probe(struct platform_device *pdev)
1917{
1918 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1919 struct snd_soc_codec *codec;
1920 struct wm8993_priv *wm8993;
1921 int ret = 0;
1922
1923 if (!wm8993_codec) {
1924 dev_err(&pdev->dev, "I2C device not yet probed\n");
1925 goto err;
1926 }
1927
1928 socdev->card->codec = wm8993_codec;
1929 codec = wm8993_codec;
1930 wm8993 = codec->private_data;
1931
1932 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1933 if (ret < 0) {
1934 dev_err(codec->dev, "failed to create pcms\n");
1935 goto err;
1936 }
1937
1938 snd_soc_add_controls(codec, wm8993_snd_controls,
1939 ARRAY_SIZE(wm8993_snd_controls));
1940 if (wm8993->pdata.num_retune_configs != 0) {
1941 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1942 } else {
1943 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1944 snd_soc_add_controls(codec, wm8993_eq_controls,
1945 ARRAY_SIZE(wm8993_eq_controls));
1946 }
1947
1948 snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
1949 ARRAY_SIZE(wm8993_dapm_widgets));
1950
1951 snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
1952
1953 if (wm8993->pdata.lineout1_diff)
1954 snd_soc_dapm_add_routes(codec,
1955 lineout1_diff_routes,
1956 ARRAY_SIZE(lineout1_diff_routes));
1957 else
1958 snd_soc_dapm_add_routes(codec,
1959 lineout1_se_routes,
1960 ARRAY_SIZE(lineout1_se_routes));
1961
1962 if (wm8993->pdata.lineout2_diff)
1963 snd_soc_dapm_add_routes(codec,
1964 lineout2_diff_routes,
1965 ARRAY_SIZE(lineout2_diff_routes));
1966 else
1967 snd_soc_dapm_add_routes(codec,
1968 lineout2_se_routes,
1969 ARRAY_SIZE(lineout2_se_routes));
1970
1971 snd_soc_dapm_new_widgets(codec);
1972
1973 ret = snd_soc_init_card(socdev);
1974 if (ret < 0) {
1975 dev_err(codec->dev, "failed to register card\n");
1976 goto card_err;
1977 }
1978
1979 return ret;
1980
1981card_err:
1982 snd_soc_free_pcms(socdev);
1983 snd_soc_dapm_free(socdev);
1984err:
1985 return ret;
1986}
1987
1988static int wm8993_remove(struct platform_device *pdev)
1989{
1990 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1991
1992 snd_soc_free_pcms(socdev);
1993 snd_soc_dapm_free(socdev);
1994
1995 return 0;
1996}
1997
1998struct snd_soc_codec_device soc_codec_dev_wm8993 = {
1999 .probe = wm8993_probe,
2000 .remove = wm8993_remove,
2001};
2002EXPORT_SYMBOL_GPL(soc_codec_dev_wm8993);
2003
2004static int wm8993_i2c_probe(struct i2c_client *i2c,
2005 const struct i2c_device_id *id)
2006{
2007 struct wm8993_priv *wm8993;
2008 struct snd_soc_codec *codec;
2009 unsigned int val;
2010 int ret;
2011
2012 if (wm8993_codec) {
2013 dev_err(&i2c->dev, "A WM8993 is already registered\n");
2014 return -EINVAL;
2015 }
2016
2017 wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
2018 if (wm8993 == NULL)
2019 return -ENOMEM;
2020
2021 codec = &wm8993->codec;
2022 if (i2c->dev.platform_data)
2023 memcpy(&wm8993->pdata, i2c->dev.platform_data,
2024 sizeof(wm8993->pdata));
2025
2026 mutex_init(&codec->mutex);
2027 INIT_LIST_HEAD(&codec->dapm_widgets);
2028 INIT_LIST_HEAD(&codec->dapm_paths);
2029
2030 codec->name = "WM8993";
2031 codec->read = wm8993_read;
2032 codec->write = wm8993_write;
2033 codec->hw_write = (hw_write_t)i2c_master_send;
2034 codec->reg_cache = wm8993->reg_cache;
2035 codec->reg_cache_size = ARRAY_SIZE(wm8993->reg_cache);
2036 codec->bias_level = SND_SOC_BIAS_OFF;
2037 codec->set_bias_level = wm8993_set_bias_level;
2038 codec->dai = &wm8993_dai;
2039 codec->num_dai = 1;
2040 codec->private_data = wm8993;
2041
2042 memcpy(wm8993->reg_cache, wm8993_reg_defaults,
2043 sizeof(wm8993->reg_cache));
2044
2045 i2c_set_clientdata(i2c, wm8993);
2046 codec->control_data = i2c;
2047 wm8993_codec = codec;
2048
2049 codec->dev = &i2c->dev;
2050
2051 val = wm8993_read_hw(codec, WM8993_SOFTWARE_RESET);
2052 if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
2053 dev_err(codec->dev, "Invalid ID register value %x\n", val);
2054 ret = -EINVAL;
2055 goto err;
2056 }
2057
2058 ret = wm8993_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
2059 if (ret != 0)
2060 goto err;
2061
2062 /* By default we're using the output mixers */
2063 wm8993->class_w_users = 2;
2064
2065 /* Latch volume update bits and default ZC on */
2066 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
2067 WM8993_IN1_VU, WM8993_IN1_VU);
2068 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_1_2_VOLUME,
2069 WM8993_IN1_VU, WM8993_IN1_VU);
2070 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_3_4_VOLUME,
2071 WM8993_IN2_VU, WM8993_IN2_VU);
2072 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
2073 WM8993_IN2_VU, WM8993_IN2_VU);
2074
2075 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_RIGHT,
2076 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
2077
2078 snd_soc_update_bits(codec, WM8993_LEFT_OUTPUT_VOLUME,
2079 WM8993_HPOUT1L_ZC, WM8993_HPOUT1L_ZC);
2080 snd_soc_update_bits(codec, WM8993_RIGHT_OUTPUT_VOLUME,
2081 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
2082 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
2083
2084 snd_soc_update_bits(codec, WM8993_LEFT_OPGA_VOLUME,
2085 WM8993_MIXOUTL_ZC, WM8993_MIXOUTL_ZC);
2086 snd_soc_update_bits(codec, WM8993_RIGHT_OPGA_VOLUME,
2087 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
2088 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
2089
2090 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
2091 WM8993_DAC_VU, WM8993_DAC_VU);
2092 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
2093 WM8993_ADC_VU, WM8993_ADC_VU);
2094
2095 /* Manualy manage the HPOUT sequencing for independent stereo
2096 * control. */
2097 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
2098 WM8993_HPOUT1_AUTO_PU, 0);
2099
2100 /* Use automatic clock configuration */
2101 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
2102
2103 if (!wm8993->pdata.lineout1_diff)
2104 snd_soc_update_bits(codec, WM8993_LINE_MIXER1,
2105 WM8993_LINEOUT1_MODE,
2106 WM8993_LINEOUT1_MODE);
2107 if (!wm8993->pdata.lineout2_diff)
2108 snd_soc_update_bits(codec, WM8993_LINE_MIXER2,
2109 WM8993_LINEOUT2_MODE,
2110 WM8993_LINEOUT2_MODE);
2111
2112 if (wm8993->pdata.lineout1fb)
2113 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
2114 WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
2115
2116 if (wm8993->pdata.lineout2fb)
2117 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
2118 WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
2119
2120 /* Apply the microphone bias/detection configuration - the
2121 * platform data is directly applicable to the register. */
2122 snd_soc_update_bits(codec, WM8993_MICBIAS,
2123 WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
2124 WM8993_MICB1_LVL | WM8993_MICB2_LVL,
2125 wm8993->pdata.jd_scthr << WM8993_JD_SCTHR_SHIFT |
2126 wm8993->pdata.jd_thr << WM8993_JD_THR_SHIFT |
2127 wm8993->pdata.micbias1_lvl |
2128 wm8993->pdata.micbias1_lvl << 1);
2129
2130 ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2131 if (ret != 0)
2132 goto err;
2133
2134 wm8993_dai.dev = codec->dev;
2135
2136 ret = snd_soc_register_dai(&wm8993_dai);
2137 if (ret != 0)
2138 goto err_bias;
2139
2140 ret = snd_soc_register_codec(codec);
2141
2142 return 0;
2143
2144err_bias:
2145 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
2146err:
2147 wm8993_codec = NULL;
2148 kfree(wm8993);
2149 return ret;
2150}
2151
2152static int wm8993_i2c_remove(struct i2c_client *client)
2153{
2154 struct wm8993_priv *wm8993 = i2c_get_clientdata(client);
2155
2156 snd_soc_unregister_codec(&wm8993->codec);
2157 snd_soc_unregister_dai(&wm8993_dai);
2158
2159 wm8993_set_bias_level(&wm8993->codec, SND_SOC_BIAS_OFF);
2160 kfree(wm8993);
2161
2162 return 0;
2163}
2164
2165static const struct i2c_device_id wm8993_i2c_id[] = {
2166 { "wm8993", 0 },
2167 { }
2168};
2169MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
2170
2171static struct i2c_driver wm8993_i2c_driver = {
2172 .driver = {
2173 .name = "WM8993",
2174 .owner = THIS_MODULE,
2175 },
2176 .probe = wm8993_i2c_probe,
2177 .remove = wm8993_i2c_remove,
2178 .id_table = wm8993_i2c_id,
2179};
2180
2181
2182static int __init wm8993_modinit(void)
2183{
2184 int ret;
2185
2186 ret = i2c_add_driver(&wm8993_i2c_driver);
2187 if (ret != 0)
2188 pr_err("WM8993: Unable to register I2C driver: %d\n", ret);
2189
2190 return ret;
2191}
2192module_init(wm8993_modinit);
2193
2194static void __exit wm8993_exit(void)
2195{
2196 i2c_del_driver(&wm8993_i2c_driver);
2197}
2198module_exit(wm8993_exit);
2199
2200
2201MODULE_DESCRIPTION("ASoC WM8993 driver");
2202MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2203MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 22:07:38 -0500