ASoC: clean up wm8974 and wm8978 clock divider handling

wm8974 and wm8978 codec drivers control DAC and ADC oversampling rates in their
.set_clkdiv() methods, which is wrong, because these are simple boolean
switches and not clock dividers. Move these bits to sound controls. Also remove
manual configuration of the MCLK divider in wm8978, since it is configured
automatically.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

1 files changed, 4 insertions, 8 deletions

diff --git a/sound/soc/codecs/wm8974.c b/sound/soc/codecs/wm8974.c
index 8812751da8c9..ee637af4737a 100644
--- a/sound/soc/codecs/wm8974.c
+++ b/sound/soc/codecs/wm8974.c
@@ -170,6 +170,10 @@ SOC_ENUM("Aux Mode", wm8974_auxmode),
 
 SOC_SINGLE("Capture Boost(+20dB)", WM8974_ADCBOOST,  8, 1, 0),
 SOC_SINGLE("Mono Playback Switch", WM8974_MONOMIX, 6, 1, 1),
+
+/* DAC / ADC oversampling */
+SOC_SINGLE("DAC 128x Oversampling Switch", WM8974_DAC, 8, 1, 0),
+SOC_SINGLE("ADC 128x Oversampling Switch", WM8974_ADC, 8, 1, 0),
 };
 
 /* Speaker Output Mixer */
@@ -381,14 +385,6 @@ static int wm8974_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
                 reg = snd_soc_read(codec, WM8974_CLOCK) & 0x11f;
                 snd_soc_write(codec, WM8974_CLOCK, reg | div);
                 break;
-        case WM8974_ADCCLK:
-                reg = snd_soc_read(codec, WM8974_ADC) & 0x1f7;
-                snd_soc_write(codec, WM8974_ADC, reg | div);
-                break;
-        case WM8974_DACCLK:
-                reg = snd_soc_read(codec, WM8974_DAC) & 0x1f7;
-                snd_soc_write(codec, WM8974_DAC, reg | div);
-                break;
         case WM8974_BCLKDIV:
                 reg = snd_soc_read(codec, WM8974_CLOCK) & 0x1e3;
                 snd_soc_write(codec, WM8974_CLOCK, reg | div);