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authorMark Brown <broonie@opensource.wolfsonmicro.com>2009-11-26 06:56:07 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-12-04 11:50:53 -0500
commita91eb199e4dc8a2ab3fb7a53f1a23ce82b29fc04 (patch)
treef0ef6ed46e0ed0e6408d2c21e5e7b294c76fbf88 /sound/soc/codecs/wm8904.c
parentd033c36ae5cec22c893c710cd026fb732c4086b9 (diff)
ASoC: Initial WM8904 CODEC driver
The WM8904 is a high performance ultra-low power stereo CODEC optimised for portable audio applications, with features including a class W amplifier, FLL with free running mode, Mobile ReTune and ground referenced headphone and line outputs. Support for some features, most particularly the digital microphone interface, is not yet present. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'sound/soc/codecs/wm8904.c')
-rw-r--r--sound/soc/codecs/wm8904.c2538
1 files changed, 2538 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c
new file mode 100644
index 000000000000..8310e5d14b83
--- /dev/null
+++ b/sound/soc/codecs/wm8904.c
@@ -0,0 +1,2538 @@
1/*
2 * wm8904.c -- WM8904 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/wm8904.h>
30
31#include "wm8904.h"
32
33static struct snd_soc_codec *wm8904_codec;
34struct snd_soc_codec_device soc_codec_dev_wm8904;
35
36#define WM8904_NUM_DCS_CHANNELS 4
37
38#define WM8904_NUM_SUPPLIES 5
39static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
40 "DCVDD",
41 "DBVDD",
42 "AVDD",
43 "CPVDD",
44 "MICVDD",
45};
46
47/* codec private data */
48struct wm8904_priv {
49 struct snd_soc_codec codec;
50 u16 reg_cache[WM8904_MAX_REGISTER + 1];
51
52 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
53
54 struct wm8904_pdata *pdata;
55
56 int deemph;
57
58 /* Platform provided DRC configuration */
59 const char **drc_texts;
60 int drc_cfg;
61 struct soc_enum drc_enum;
62
63 /* Platform provided ReTune mobile configuration */
64 int num_retune_mobile_texts;
65 const char **retune_mobile_texts;
66 int retune_mobile_cfg;
67 struct soc_enum retune_mobile_enum;
68
69 /* FLL setup */
70 int fll_src;
71 int fll_fref;
72 int fll_fout;
73
74 /* Clocking configuration */
75 unsigned int mclk_rate;
76 int sysclk_src;
77 unsigned int sysclk_rate;
78
79 int tdm_width;
80 int tdm_slots;
81 int bclk;
82 int fs;
83
84 /* DC servo configuration - cached offset values */
85 int dcs_state[WM8904_NUM_DCS_CHANNELS];
86};
87
88static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = {
89 0x8904, /* R0 - SW Reset and ID */
90 0x0000, /* R1 - Revision */
91 0x0000, /* R2 */
92 0x0000, /* R3 */
93 0x0018, /* R4 - Bias Control 0 */
94 0x0000, /* R5 - VMID Control 0 */
95 0x0000, /* R6 - Mic Bias Control 0 */
96 0x0000, /* R7 - Mic Bias Control 1 */
97 0x0001, /* R8 - Analogue DAC 0 */
98 0x9696, /* R9 - mic Filter Control */
99 0x0001, /* R10 - Analogue ADC 0 */
100 0x0000, /* R11 */
101 0x0000, /* R12 - Power Management 0 */
102 0x0000, /* R13 */
103 0x0000, /* R14 - Power Management 2 */
104 0x0000, /* R15 - Power Management 3 */
105 0x0000, /* R16 */
106 0x0000, /* R17 */
107 0x0000, /* R18 - Power Management 6 */
108 0x0000, /* R19 */
109 0x945E, /* R20 - Clock Rates 0 */
110 0x0C05, /* R21 - Clock Rates 1 */
111 0x0006, /* R22 - Clock Rates 2 */
112 0x0000, /* R23 */
113 0x0050, /* R24 - Audio Interface 0 */
114 0x000A, /* R25 - Audio Interface 1 */
115 0x00E4, /* R26 - Audio Interface 2 */
116 0x0040, /* R27 - Audio Interface 3 */
117 0x0000, /* R28 */
118 0x0000, /* R29 */
119 0x00C0, /* R30 - DAC Digital Volume Left */
120 0x00C0, /* R31 - DAC Digital Volume Right */
121 0x0000, /* R32 - DAC Digital 0 */
122 0x0008, /* R33 - DAC Digital 1 */
123 0x0000, /* R34 */
124 0x0000, /* R35 */
125 0x00C0, /* R36 - ADC Digital Volume Left */
126 0x00C0, /* R37 - ADC Digital Volume Right */
127 0x0010, /* R38 - ADC Digital 0 */
128 0x0000, /* R39 - Digital Microphone 0 */
129 0x01AF, /* R40 - DRC 0 */
130 0x3248, /* R41 - DRC 1 */
131 0x0000, /* R42 - DRC 2 */
132 0x0000, /* R43 - DRC 3 */
133 0x0085, /* R44 - Analogue Left Input 0 */
134 0x0085, /* R45 - Analogue Right Input 0 */
135 0x0044, /* R46 - Analogue Left Input 1 */
136 0x0044, /* R47 - Analogue Right Input 1 */
137 0x0000, /* R48 */
138 0x0000, /* R49 */
139 0x0000, /* R50 */
140 0x0000, /* R51 */
141 0x0000, /* R52 */
142 0x0000, /* R53 */
143 0x0000, /* R54 */
144 0x0000, /* R55 */
145 0x0000, /* R56 */
146 0x002D, /* R57 - Analogue OUT1 Left */
147 0x002D, /* R58 - Analogue OUT1 Right */
148 0x0039, /* R59 - Analogue OUT2 Left */
149 0x0039, /* R60 - Analogue OUT2 Right */
150 0x0000, /* R61 - Analogue OUT12 ZC */
151 0x0000, /* R62 */
152 0x0000, /* R63 */
153 0x0000, /* R64 */
154 0x0000, /* R65 */
155 0x0000, /* R66 */
156 0x0000, /* R67 - DC Servo 0 */
157 0x0000, /* R68 - DC Servo 1 */
158 0xAAAA, /* R69 - DC Servo 2 */
159 0x0000, /* R70 */
160 0xAAAA, /* R71 - DC Servo 4 */
161 0xAAAA, /* R72 - DC Servo 5 */
162 0x0000, /* R73 - DC Servo 6 */
163 0x0000, /* R74 - DC Servo 7 */
164 0x0000, /* R75 - DC Servo 8 */
165 0x0000, /* R76 - DC Servo 9 */
166 0x0000, /* R77 - DC Servo Readback 0 */
167 0x0000, /* R78 */
168 0x0000, /* R79 */
169 0x0000, /* R80 */
170 0x0000, /* R81 */
171 0x0000, /* R82 */
172 0x0000, /* R83 */
173 0x0000, /* R84 */
174 0x0000, /* R85 */
175 0x0000, /* R86 */
176 0x0000, /* R87 */
177 0x0000, /* R88 */
178 0x0000, /* R89 */
179 0x0000, /* R90 - Analogue HP 0 */
180 0x0000, /* R91 */
181 0x0000, /* R92 */
182 0x0000, /* R93 */
183 0x0000, /* R94 - Analogue Lineout 0 */
184 0x0000, /* R95 */
185 0x0000, /* R96 */
186 0x0000, /* R97 */
187 0x0000, /* R98 - Charge Pump 0 */
188 0x0000, /* R99 */
189 0x0000, /* R100 */
190 0x0000, /* R101 */
191 0x0000, /* R102 */
192 0x0000, /* R103 */
193 0x0004, /* R104 - Class W 0 */
194 0x0000, /* R105 */
195 0x0000, /* R106 */
196 0x0000, /* R107 */
197 0x0000, /* R108 - Write Sequencer 0 */
198 0x0000, /* R109 - Write Sequencer 1 */
199 0x0000, /* R110 - Write Sequencer 2 */
200 0x0000, /* R111 - Write Sequencer 3 */
201 0x0000, /* R112 - Write Sequencer 4 */
202 0x0000, /* R113 */
203 0x0000, /* R114 */
204 0x0000, /* R115 */
205 0x0000, /* R116 - FLL Control 1 */
206 0x0007, /* R117 - FLL Control 2 */
207 0x0000, /* R118 - FLL Control 3 */
208 0x2EE0, /* R119 - FLL Control 4 */
209 0x0004, /* R120 - FLL Control 5 */
210 0x0014, /* R121 - GPIO Control 1 */
211 0x0010, /* R122 - GPIO Control 2 */
212 0x0010, /* R123 - GPIO Control 3 */
213 0x0000, /* R124 - GPIO Control 4 */
214 0x0000, /* R125 */
215 0x0000, /* R126 - Digital Pulls */
216 0x0000, /* R127 - Interrupt Status */
217 0xFFFF, /* R128 - Interrupt Status Mask */
218 0x0000, /* R129 - Interrupt Polarity */
219 0x0000, /* R130 - Interrupt Debounce */
220 0x0000, /* R131 */
221 0x0000, /* R132 */
222 0x0000, /* R133 */
223 0x0000, /* R134 - EQ1 */
224 0x000C, /* R135 - EQ2 */
225 0x000C, /* R136 - EQ3 */
226 0x000C, /* R137 - EQ4 */
227 0x000C, /* R138 - EQ5 */
228 0x000C, /* R139 - EQ6 */
229 0x0FCA, /* R140 - EQ7 */
230 0x0400, /* R141 - EQ8 */
231 0x00D8, /* R142 - EQ9 */
232 0x1EB5, /* R143 - EQ10 */
233 0xF145, /* R144 - EQ11 */
234 0x0B75, /* R145 - EQ12 */
235 0x01C5, /* R146 - EQ13 */
236 0x1C58, /* R147 - EQ14 */
237 0xF373, /* R148 - EQ15 */
238 0x0A54, /* R149 - EQ16 */
239 0x0558, /* R150 - EQ17 */
240 0x168E, /* R151 - EQ18 */
241 0xF829, /* R152 - EQ19 */
242 0x07AD, /* R153 - EQ20 */
243 0x1103, /* R154 - EQ21 */
244 0x0564, /* R155 - EQ22 */
245 0x0559, /* R156 - EQ23 */
246 0x4000, /* R157 - EQ24 */
247 0x0000, /* R158 */
248 0x0000, /* R159 */
249 0x0000, /* R160 */
250 0x0000, /* R161 - Control Interface Test 1 */
251 0x0000, /* R162 */
252 0x0000, /* R163 */
253 0x0000, /* R164 */
254 0x0000, /* R165 */
255 0x0000, /* R166 */
256 0x0000, /* R167 */
257 0x0000, /* R168 */
258 0x0000, /* R169 */
259 0x0000, /* R170 */
260 0x0000, /* R171 */
261 0x0000, /* R172 */
262 0x0000, /* R173 */
263 0x0000, /* R174 */
264 0x0000, /* R175 */
265 0x0000, /* R176 */
266 0x0000, /* R177 */
267 0x0000, /* R178 */
268 0x0000, /* R179 */
269 0x0000, /* R180 */
270 0x0000, /* R181 */
271 0x0000, /* R182 */
272 0x0000, /* R183 */
273 0x0000, /* R184 */
274 0x0000, /* R185 */
275 0x0000, /* R186 */
276 0x0000, /* R187 */
277 0x0000, /* R188 */
278 0x0000, /* R189 */
279 0x0000, /* R190 */
280 0x0000, /* R191 */
281 0x0000, /* R192 */
282 0x0000, /* R193 */
283 0x0000, /* R194 */
284 0x0000, /* R195 */
285 0x0000, /* R196 */
286 0x0000, /* R197 */
287 0x0000, /* R198 */
288 0x0000, /* R199 */
289 0x0000, /* R200 */
290 0x0000, /* R201 */
291 0x0000, /* R202 */
292 0x0000, /* R203 */
293 0x0000, /* R204 - Analogue Output Bias 0 */
294 0x0000, /* R205 */
295 0x0000, /* R206 */
296 0x0000, /* R207 */
297 0x0000, /* R208 */
298 0x0000, /* R209 */
299 0x0000, /* R210 */
300 0x0000, /* R211 */
301 0x0000, /* R212 */
302 0x0000, /* R213 */
303 0x0000, /* R214 */
304 0x0000, /* R215 */
305 0x0000, /* R216 */
306 0x0000, /* R217 */
307 0x0000, /* R218 */
308 0x0000, /* R219 */
309 0x0000, /* R220 */
310 0x0000, /* R221 */
311 0x0000, /* R222 */
312 0x0000, /* R223 */
313 0x0000, /* R224 */
314 0x0000, /* R225 */
315 0x0000, /* R226 */
316 0x0000, /* R227 */
317 0x0000, /* R228 */
318 0x0000, /* R229 */
319 0x0000, /* R230 */
320 0x0000, /* R231 */
321 0x0000, /* R232 */
322 0x0000, /* R233 */
323 0x0000, /* R234 */
324 0x0000, /* R235 */
325 0x0000, /* R236 */
326 0x0000, /* R237 */
327 0x0000, /* R238 */
328 0x0000, /* R239 */
329 0x0000, /* R240 */
330 0x0000, /* R241 */
331 0x0000, /* R242 */
332 0x0000, /* R243 */
333 0x0000, /* R244 */
334 0x0000, /* R245 */
335 0x0000, /* R246 */
336 0x0000, /* R247 - FLL NCO Test 0 */
337 0x0019, /* R248 - FLL NCO Test 1 */
338};
339
340static struct {
341 int readable;
342 int writable;
343 int vol;
344} wm8904_access[] = {
345 { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */
346 { 0x0000, 0x0000, 0 }, /* R1 - Revision */
347 { 0x0000, 0x0000, 0 }, /* R2 */
348 { 0x0000, 0x0000, 0 }, /* R3 */
349 { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */
350 { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */
351 { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */
352 { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */
353 { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */
354 { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */
355 { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */
356 { 0x0000, 0x0000, 0 }, /* R11 */
357 { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */
358 { 0x0000, 0x0000, 0 }, /* R13 */
359 { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */
360 { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */
361 { 0x0000, 0x0000, 0 }, /* R16 */
362 { 0x0000, 0x0000, 0 }, /* R17 */
363 { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */
364 { 0x0000, 0x0000, 0 }, /* R19 */
365 { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */
366 { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */
367 { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */
368 { 0x0000, 0x0000, 0 }, /* R23 */
369 { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */
370 { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */
371 { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */
372 { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */
373 { 0x0000, 0x0000, 0 }, /* R28 */
374 { 0x0000, 0x0000, 0 }, /* R29 */
375 { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */
376 { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */
377 { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */
378 { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */
379 { 0x0000, 0x0000, 0 }, /* R34 */
380 { 0x0000, 0x0000, 0 }, /* R35 */
381 { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */
382 { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */
383 { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */
384 { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */
385 { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */
386 { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */
387 { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */
388 { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */
389 { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */
390 { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */
391 { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */
392 { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */
393 { 0x0000, 0x0000, 0 }, /* R48 */
394 { 0x0000, 0x0000, 0 }, /* R49 */
395 { 0x0000, 0x0000, 0 }, /* R50 */
396 { 0x0000, 0x0000, 0 }, /* R51 */
397 { 0x0000, 0x0000, 0 }, /* R52 */
398 { 0x0000, 0x0000, 0 }, /* R53 */
399 { 0x0000, 0x0000, 0 }, /* R54 */
400 { 0x0000, 0x0000, 0 }, /* R55 */
401 { 0x0000, 0x0000, 0 }, /* R56 */
402 { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */
403 { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */
404 { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */
405 { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */
406 { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */
407 { 0x0000, 0x0000, 0 }, /* R62 */
408 { 0x0000, 0x0000, 0 }, /* R63 */
409 { 0x0000, 0x0000, 0 }, /* R64 */
410 { 0x0000, 0x0000, 0 }, /* R65 */
411 { 0x0000, 0x0000, 0 }, /* R66 */
412 { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */
413 { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */
414 { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */
415 { 0x0000, 0x0000, 0 }, /* R70 */
416 { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */
417 { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */
418 { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */
419 { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */
420 { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */
421 { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */
422 { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */
423 { 0x0000, 0x0000, 0 }, /* R78 */
424 { 0x0000, 0x0000, 0 }, /* R79 */
425 { 0x0000, 0x0000, 0 }, /* R80 */
426 { 0x0000, 0x0000, 0 }, /* R81 */
427 { 0x0000, 0x0000, 0 }, /* R82 */
428 { 0x0000, 0x0000, 0 }, /* R83 */
429 { 0x0000, 0x0000, 0 }, /* R84 */
430 { 0x0000, 0x0000, 0 }, /* R85 */
431 { 0x0000, 0x0000, 0 }, /* R86 */
432 { 0x0000, 0x0000, 0 }, /* R87 */
433 { 0x0000, 0x0000, 0 }, /* R88 */
434 { 0x0000, 0x0000, 0 }, /* R89 */
435 { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */
436 { 0x0000, 0x0000, 0 }, /* R91 */
437 { 0x0000, 0x0000, 0 }, /* R92 */
438 { 0x0000, 0x0000, 0 }, /* R93 */
439 { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */
440 { 0x0000, 0x0000, 0 }, /* R95 */
441 { 0x0000, 0x0000, 0 }, /* R96 */
442 { 0x0000, 0x0000, 0 }, /* R97 */
443 { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */
444 { 0x0000, 0x0000, 0 }, /* R99 */
445 { 0x0000, 0x0000, 0 }, /* R100 */
446 { 0x0000, 0x0000, 0 }, /* R101 */
447 { 0x0000, 0x0000, 0 }, /* R102 */
448 { 0x0000, 0x0000, 0 }, /* R103 */
449 { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */
450 { 0x0000, 0x0000, 0 }, /* R105 */
451 { 0x0000, 0x0000, 0 }, /* R106 */
452 { 0x0000, 0x0000, 0 }, /* R107 */
453 { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */
454 { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */
455 { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */
456 { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */
457 { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */
458 { 0x0000, 0x0000, 0 }, /* R113 */
459 { 0x0000, 0x0000, 0 }, /* R114 */
460 { 0x0000, 0x0000, 0 }, /* R115 */
461 { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */
462 { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */
463 { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */
464 { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */
465 { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */
466 { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */
467 { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */
468 { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */
469 { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */
470 { 0x0000, 0x0000, 0 }, /* R125 */
471 { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */
472 { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */
473 { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */
474 { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */
475 { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */
476 { 0x0000, 0x0000, 0 }, /* R131 */
477 { 0x0000, 0x0000, 0 }, /* R132 */
478 { 0x0000, 0x0000, 0 }, /* R133 */
479 { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */
480 { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */
481 { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */
482 { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */
483 { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */
484 { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */
485 { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */
486 { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */
487 { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */
488 { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */
489 { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */
490 { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */
491 { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */
492 { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */
493 { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */
494 { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */
495 { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */
496 { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */
497 { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */
498 { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */
499 { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */
500 { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */
501 { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */
502 { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */
503 { 0x0000, 0x0000, 0 }, /* R158 */
504 { 0x0000, 0x0000, 0 }, /* R159 */
505 { 0x0000, 0x0000, 0 }, /* R160 */
506 { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */
507 { 0x0000, 0x0000, 0 }, /* R162 */
508 { 0x0000, 0x0000, 0 }, /* R163 */
509 { 0x0000, 0x0000, 0 }, /* R164 */
510 { 0x0000, 0x0000, 0 }, /* R165 */
511 { 0x0000, 0x0000, 0 }, /* R166 */
512 { 0x0000, 0x0000, 0 }, /* R167 */
513 { 0x0000, 0x0000, 0 }, /* R168 */
514 { 0x0000, 0x0000, 0 }, /* R169 */
515 { 0x0000, 0x0000, 0 }, /* R170 */
516 { 0x0000, 0x0000, 0 }, /* R171 */
517 { 0x0000, 0x0000, 0 }, /* R172 */
518 { 0x0000, 0x0000, 0 }, /* R173 */
519 { 0x0000, 0x0000, 0 }, /* R174 */
520 { 0x0000, 0x0000, 0 }, /* R175 */
521 { 0x0000, 0x0000, 0 }, /* R176 */
522 { 0x0000, 0x0000, 0 }, /* R177 */
523 { 0x0000, 0x0000, 0 }, /* R178 */
524 { 0x0000, 0x0000, 0 }, /* R179 */
525 { 0x0000, 0x0000, 0 }, /* R180 */
526 { 0x0000, 0x0000, 0 }, /* R181 */
527 { 0x0000, 0x0000, 0 }, /* R182 */
528 { 0x0000, 0x0000, 0 }, /* R183 */
529 { 0x0000, 0x0000, 0 }, /* R184 */
530 { 0x0000, 0x0000, 0 }, /* R185 */
531 { 0x0000, 0x0000, 0 }, /* R186 */
532 { 0x0000, 0x0000, 0 }, /* R187 */
533 { 0x0000, 0x0000, 0 }, /* R188 */
534 { 0x0000, 0x0000, 0 }, /* R189 */
535 { 0x0000, 0x0000, 0 }, /* R190 */
536 { 0x0000, 0x0000, 0 }, /* R191 */
537 { 0x0000, 0x0000, 0 }, /* R192 */
538 { 0x0000, 0x0000, 0 }, /* R193 */
539 { 0x0000, 0x0000, 0 }, /* R194 */
540 { 0x0000, 0x0000, 0 }, /* R195 */
541 { 0x0000, 0x0000, 0 }, /* R196 */
542 { 0x0000, 0x0000, 0 }, /* R197 */
543 { 0x0000, 0x0000, 0 }, /* R198 */
544 { 0x0000, 0x0000, 0 }, /* R199 */
545 { 0x0000, 0x0000, 0 }, /* R200 */
546 { 0x0000, 0x0000, 0 }, /* R201 */
547 { 0x0000, 0x0000, 0 }, /* R202 */
548 { 0x0000, 0x0000, 0 }, /* R203 */
549 { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */
550 { 0x0000, 0x0000, 0 }, /* R205 */
551 { 0x0000, 0x0000, 0 }, /* R206 */
552 { 0x0000, 0x0000, 0 }, /* R207 */
553 { 0x0000, 0x0000, 0 }, /* R208 */
554 { 0x0000, 0x0000, 0 }, /* R209 */
555 { 0x0000, 0x0000, 0 }, /* R210 */
556 { 0x0000, 0x0000, 0 }, /* R211 */
557 { 0x0000, 0x0000, 0 }, /* R212 */
558 { 0x0000, 0x0000, 0 }, /* R213 */
559 { 0x0000, 0x0000, 0 }, /* R214 */
560 { 0x0000, 0x0000, 0 }, /* R215 */
561 { 0x0000, 0x0000, 0 }, /* R216 */
562 { 0x0000, 0x0000, 0 }, /* R217 */
563 { 0x0000, 0x0000, 0 }, /* R218 */
564 { 0x0000, 0x0000, 0 }, /* R219 */
565 { 0x0000, 0x0000, 0 }, /* R220 */
566 { 0x0000, 0x0000, 0 }, /* R221 */
567 { 0x0000, 0x0000, 0 }, /* R222 */
568 { 0x0000, 0x0000, 0 }, /* R223 */
569 { 0x0000, 0x0000, 0 }, /* R224 */
570 { 0x0000, 0x0000, 0 }, /* R225 */
571 { 0x0000, 0x0000, 0 }, /* R226 */
572 { 0x0000, 0x0000, 0 }, /* R227 */
573 { 0x0000, 0x0000, 0 }, /* R228 */
574 { 0x0000, 0x0000, 0 }, /* R229 */
575 { 0x0000, 0x0000, 0 }, /* R230 */
576 { 0x0000, 0x0000, 0 }, /* R231 */
577 { 0x0000, 0x0000, 0 }, /* R232 */
578 { 0x0000, 0x0000, 0 }, /* R233 */
579 { 0x0000, 0x0000, 0 }, /* R234 */
580 { 0x0000, 0x0000, 0 }, /* R235 */
581 { 0x0000, 0x0000, 0 }, /* R236 */
582 { 0x0000, 0x0000, 0 }, /* R237 */
583 { 0x0000, 0x0000, 0 }, /* R238 */
584 { 0x0000, 0x0000, 0 }, /* R239 */
585 { 0x0000, 0x0000, 0 }, /* R240 */
586 { 0x0000, 0x0000, 0 }, /* R241 */
587 { 0x0000, 0x0000, 0 }, /* R242 */
588 { 0x0000, 0x0000, 0 }, /* R243 */
589 { 0x0000, 0x0000, 0 }, /* R244 */
590 { 0x0000, 0x0000, 0 }, /* R245 */
591 { 0x0000, 0x0000, 0 }, /* R246 */
592 { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */
593 { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */
594};
595
596static int wm8904_volatile_register(unsigned int reg)
597{
598 return wm8904_access[reg].vol;
599}
600
601static int wm8904_reset(struct snd_soc_codec *codec)
602{
603 return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0);
604}
605
606static int wm8904_configure_clocking(struct snd_soc_codec *codec)
607{
608 struct wm8904_priv *wm8904 = codec->private_data;
609 unsigned int clock0, clock2, rate;
610
611 /* Gate the clock while we're updating to avoid misclocking */
612 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
613 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
614 WM8904_SYSCLK_SRC, 0);
615
616 /* This should be done on init() for bypass paths */
617 switch (wm8904->sysclk_src) {
618 case WM8904_CLK_MCLK:
619 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
620
621 clock2 &= ~WM8904_SYSCLK_SRC;
622 rate = wm8904->mclk_rate;
623
624 /* Ensure the FLL is stopped */
625 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
626 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
627 break;
628
629 case WM8904_CLK_FLL:
630 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
631 wm8904->fll_fout);
632
633 clock2 |= WM8904_SYSCLK_SRC;
634 rate = wm8904->fll_fout;
635 break;
636
637 default:
638 dev_err(codec->dev, "System clock not configured\n");
639 return -EINVAL;
640 }
641
642 /* SYSCLK shouldn't be over 13.5MHz */
643 if (rate > 13500000) {
644 clock0 = WM8904_MCLK_DIV;
645 wm8904->sysclk_rate = rate / 2;
646 } else {
647 clock0 = 0;
648 wm8904->sysclk_rate = rate;
649 }
650
651 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
652 clock0);
653
654 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
655 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
656
657 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
658
659 return 0;
660}
661
662static void wm8904_set_drc(struct snd_soc_codec *codec)
663{
664 struct wm8904_priv *wm8904 = codec->private_data;
665 struct wm8904_pdata *pdata = wm8904->pdata;
666 int save, i;
667
668 /* Save any enables; the configuration should clear them. */
669 save = snd_soc_read(codec, WM8904_DRC_0);
670
671 for (i = 0; i < WM8904_DRC_REGS; i++)
672 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
673 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
674
675 /* Reenable the DRC */
676 snd_soc_update_bits(codec, WM8904_DRC_0,
677 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
678}
679
680static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
681 struct snd_ctl_elem_value *ucontrol)
682{
683 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
684 struct wm8904_priv *wm8904 = codec->private_data;
685 struct wm8904_pdata *pdata = wm8904->pdata;
686 int value = ucontrol->value.integer.value[0];
687
688 if (value >= pdata->num_drc_cfgs)
689 return -EINVAL;
690
691 wm8904->drc_cfg = value;
692
693 wm8904_set_drc(codec);
694
695 return 0;
696}
697
698static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
699 struct snd_ctl_elem_value *ucontrol)
700{
701 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
702 struct wm8904_priv *wm8904 = codec->private_data;
703
704 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
705
706 return 0;
707}
708
709static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
710{
711 struct wm8904_priv *wm8904 = codec->private_data;
712 struct wm8904_pdata *pdata = wm8904->pdata;
713 int best, best_val, save, i, cfg;
714
715 if (!pdata || !wm8904->num_retune_mobile_texts)
716 return;
717
718 /* Find the version of the currently selected configuration
719 * with the nearest sample rate. */
720 cfg = wm8904->retune_mobile_cfg;
721 best = 0;
722 best_val = INT_MAX;
723 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
724 if (strcmp(pdata->retune_mobile_cfgs[i].name,
725 wm8904->retune_mobile_texts[cfg]) == 0 &&
726 abs(pdata->retune_mobile_cfgs[i].rate
727 - wm8904->fs) < best_val) {
728 best = i;
729 best_val = abs(pdata->retune_mobile_cfgs[i].rate
730 - wm8904->fs);
731 }
732 }
733
734 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
735 pdata->retune_mobile_cfgs[best].name,
736 pdata->retune_mobile_cfgs[best].rate,
737 wm8904->fs);
738
739 /* The EQ will be disabled while reconfiguring it, remember the
740 * current configuration.
741 */
742 save = snd_soc_read(codec, WM8904_EQ1);
743
744 for (i = 0; i < WM8904_EQ_REGS; i++)
745 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
746 pdata->retune_mobile_cfgs[best].regs[i]);
747
748 snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
749}
750
751static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
752 struct snd_ctl_elem_value *ucontrol)
753{
754 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
755 struct wm8904_priv *wm8904 = codec->private_data;
756 struct wm8904_pdata *pdata = wm8904->pdata;
757 int value = ucontrol->value.integer.value[0];
758
759 if (value >= pdata->num_retune_mobile_cfgs)
760 return -EINVAL;
761
762 wm8904->retune_mobile_cfg = value;
763
764 wm8904_set_retune_mobile(codec);
765
766 return 0;
767}
768
769static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
770 struct snd_ctl_elem_value *ucontrol)
771{
772 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
773 struct wm8904_priv *wm8904 = codec->private_data;
774
775 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
776
777 return 0;
778}
779
780static int deemph_settings[] = { 0, 32000, 44100, 48000 };
781
782static int wm8904_set_deemph(struct snd_soc_codec *codec)
783{
784 struct wm8904_priv *wm8904 = codec->private_data;
785 int val, i, best;
786
787 /* If we're using deemphasis select the nearest available sample
788 * rate.
789 */
790 if (wm8904->deemph) {
791 best = 1;
792 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
793 if (abs(deemph_settings[i] - wm8904->fs) <
794 abs(deemph_settings[best] - wm8904->fs))
795 best = i;
796 }
797
798 val = best << WM8904_DEEMPH_SHIFT;
799 } else {
800 val = 0;
801 }
802
803 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
804
805 return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
806 WM8904_DEEMPH_MASK, val);
807}
808
809static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
810 struct snd_ctl_elem_value *ucontrol)
811{
812 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
813 struct wm8904_priv *wm8904 = codec->private_data;
814
815 return wm8904->deemph;
816}
817
818static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
819 struct snd_ctl_elem_value *ucontrol)
820{
821 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
822 struct wm8904_priv *wm8904 = codec->private_data;
823 int deemph = ucontrol->value.enumerated.item[0];
824
825 if (deemph > 1)
826 return -EINVAL;
827
828 wm8904->deemph = deemph;
829
830 return wm8904_set_deemph(codec);
831}
832
833static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
834static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
835static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
836static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
837static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
838
839static const char *input_mode_text[] = {
840 "Single-Ended", "Differential Line", "Differential Mic"
841};
842
843static const struct soc_enum lin_mode =
844 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
845
846static const struct soc_enum rin_mode =
847 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
848
849static const char *hpf_mode_text[] = {
850 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
851};
852
853static const struct soc_enum hpf_mode =
854 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
855
856static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
857SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
858 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
859
860SOC_ENUM("Left Caputure Mode", lin_mode),
861SOC_ENUM("Right Capture Mode", rin_mode),
862
863/* No TLV since it depends on mode */
864SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
865 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
866SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
867 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0),
868
869SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
870SOC_ENUM("High Pass Filter Mode", hpf_mode),
871
872SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0),
873};
874
875static const char *drc_path_text[] = {
876 "ADC", "DAC"
877};
878
879static const struct soc_enum drc_path =
880 SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text);
881
882static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
883SOC_SINGLE_TLV("Digital Playback Boost Volume",
884 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
885SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
886 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
887
888SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
889 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
890SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
891 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
892SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
893 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
894
895SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
896 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
897SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
898 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
899SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
900 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
901
902SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
903SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
904SOC_ENUM("DRC Path", drc_path),
905SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
906SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
907 wm8904_get_deemph, wm8904_put_deemph),
908};
909
910static const struct snd_kcontrol_new wm8904_snd_controls[] = {
911SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
912 sidetone_tlv),
913};
914
915static const struct snd_kcontrol_new wm8904_eq_controls[] = {
916SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
917SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
918SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
919SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
920SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
921};
922
923static int cp_event(struct snd_soc_dapm_widget *w,
924 struct snd_kcontrol *kcontrol, int event)
925{
926 BUG_ON(event != SND_SOC_DAPM_POST_PMU);
927
928 /* Maximum startup time */
929 udelay(500);
930
931 return 0;
932}
933
934static int sysclk_event(struct snd_soc_dapm_widget *w,
935 struct snd_kcontrol *kcontrol, int event)
936{
937 struct snd_soc_codec *codec = w->codec;
938 struct wm8904_priv *wm8904 = codec->private_data;
939
940 switch (event) {
941 case SND_SOC_DAPM_PRE_PMU:
942 /* If we're using the FLL then we only start it when
943 * required; we assume that the configuration has been
944 * done previously and all we need to do is kick it
945 * off.
946 */
947 switch (wm8904->sysclk_src) {
948 case WM8904_CLK_FLL:
949 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
950 WM8904_FLL_OSC_ENA,
951 WM8904_FLL_OSC_ENA);
952
953 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
954 WM8904_FLL_ENA,
955 WM8904_FLL_ENA);
956 break;
957
958 default:
959 break;
960 }
961 break;
962
963 case SND_SOC_DAPM_POST_PMD:
964 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
965 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
966 break;
967 }
968
969 return 0;
970}
971
972static int out_pga_event(struct snd_soc_dapm_widget *w,
973 struct snd_kcontrol *kcontrol, int event)
974{
975 struct snd_soc_codec *codec = w->codec;
976 struct wm8904_priv *wm8904 = codec->private_data;
977 int reg, val;
978 int dcs_mask;
979 int dcs_l, dcs_r;
980 int dcs_l_reg, dcs_r_reg;
981 int timeout;
982
983 /* This code is shared between HP and LINEOUT; we do all our
984 * power management in stereo pairs to avoid latency issues so
985 * we reuse shift to identify which rather than strcmp() the
986 * name. */
987 reg = w->shift;
988
989 switch (reg) {
990 case WM8904_ANALOGUE_HP_0:
991 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
992 dcs_r_reg = WM8904_DC_SERVO_8;
993 dcs_l_reg = WM8904_DC_SERVO_9;
994 dcs_l = 0;
995 dcs_r = 1;
996 break;
997 case WM8904_ANALOGUE_LINEOUT_0:
998 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
999 dcs_r_reg = WM8904_DC_SERVO_6;
1000 dcs_l_reg = WM8904_DC_SERVO_7;
1001 dcs_l = 2;
1002 dcs_r = 3;
1003 break;
1004 default:
1005 BUG();
1006 return -EINVAL;
1007 }
1008
1009 switch (event) {
1010 case SND_SOC_DAPM_POST_PMU:
1011 /* Power on the amplifier */
1012 snd_soc_update_bits(codec, reg,
1013 WM8904_HPL_ENA | WM8904_HPR_ENA,
1014 WM8904_HPL_ENA | WM8904_HPR_ENA);
1015
1016 /* Enable the first stage */
1017 snd_soc_update_bits(codec, reg,
1018 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
1019 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
1020
1021 /* Power up the DC servo */
1022 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
1023 dcs_mask, dcs_mask);
1024
1025 /* Either calibrate the DC servo or restore cached state
1026 * if we have that.
1027 */
1028 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
1029 dev_dbg(codec->dev, "Restoring DC servo state\n");
1030
1031 snd_soc_write(codec, dcs_l_reg,
1032 wm8904->dcs_state[dcs_l]);
1033 snd_soc_write(codec, dcs_r_reg,
1034 wm8904->dcs_state[dcs_r]);
1035
1036 snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
1037
1038 timeout = 20;
1039 } else {
1040 dev_dbg(codec->dev, "Calibrating DC servo\n");
1041
1042 snd_soc_write(codec, WM8904_DC_SERVO_1,
1043 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
1044
1045 timeout = 500;
1046 }
1047
1048 /* Wait for DC servo to complete */
1049 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
1050 do {
1051 val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
1052 if ((val & dcs_mask) == dcs_mask)
1053 break;
1054
1055 msleep(1);
1056 } while (--timeout);
1057
1058 if ((val & dcs_mask) != dcs_mask)
1059 dev_warn(codec->dev, "DC servo timed out\n");
1060 else
1061 dev_dbg(codec->dev, "DC servo ready\n");
1062
1063 /* Enable the output stage */
1064 snd_soc_update_bits(codec, reg,
1065 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
1066 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
1067
1068 /* Unshort the output itself */
1069 snd_soc_update_bits(codec, reg,
1070 WM8904_HPL_RMV_SHORT |
1071 WM8904_HPR_RMV_SHORT,
1072 WM8904_HPL_RMV_SHORT |
1073 WM8904_HPR_RMV_SHORT);
1074
1075 break;
1076
1077 case SND_SOC_DAPM_PRE_PMD:
1078 /* Short the output */
1079 snd_soc_update_bits(codec, reg,
1080 WM8904_HPL_RMV_SHORT |
1081 WM8904_HPR_RMV_SHORT, 0);
1082
1083 /* Cache the DC servo configuration; this will be
1084 * invalidated if we change the configuration. */
1085 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
1086 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
1087
1088 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
1089 dcs_mask, 0);
1090
1091 /* Disable the amplifier input and output stages */
1092 snd_soc_update_bits(codec, reg,
1093 WM8904_HPL_ENA | WM8904_HPR_ENA |
1094 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
1095 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
1096 0);
1097 break;
1098 }
1099
1100 return 0;
1101}
1102
1103static const char *lin_text[] = {
1104 "IN1L", "IN2L", "IN3L"
1105};
1106
1107static const struct soc_enum lin_enum =
1108 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text);
1109
1110static const struct snd_kcontrol_new lin_mux =
1111 SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
1112
1113static const struct soc_enum lin_inv_enum =
1114 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text);
1115
1116static const struct snd_kcontrol_new lin_inv_mux =
1117 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
1118
1119static const char *rin_text[] = {
1120 "IN1R", "IN2R", "IN3R"
1121};
1122
1123static const struct soc_enum rin_enum =
1124 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text);
1125
1126static const struct snd_kcontrol_new rin_mux =
1127 SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
1128
1129static const struct soc_enum rin_inv_enum =
1130 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text);
1131
1132static const struct snd_kcontrol_new rin_inv_mux =
1133 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
1134
1135static const char *aif_text[] = {
1136 "Left", "Right"
1137};
1138
1139static const struct soc_enum aifoutl_enum =
1140 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text);
1141
1142static const struct snd_kcontrol_new aifoutl_mux =
1143 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
1144
1145static const struct soc_enum aifoutr_enum =
1146 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text);
1147
1148static const struct snd_kcontrol_new aifoutr_mux =
1149 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
1150
1151static const struct soc_enum aifinl_enum =
1152 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text);
1153
1154static const struct snd_kcontrol_new aifinl_mux =
1155 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
1156
1157static const struct soc_enum aifinr_enum =
1158 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text);
1159
1160static const struct snd_kcontrol_new aifinr_mux =
1161 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
1162
1163static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
1164SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
1165 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1166SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
1167SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
1168};
1169
1170static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
1171SND_SOC_DAPM_INPUT("IN1L"),
1172SND_SOC_DAPM_INPUT("IN1R"),
1173SND_SOC_DAPM_INPUT("IN2L"),
1174SND_SOC_DAPM_INPUT("IN2R"),
1175SND_SOC_DAPM_INPUT("IN3L"),
1176SND_SOC_DAPM_INPUT("IN3R"),
1177
1178SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0),
1179
1180SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
1181SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
1182 &lin_inv_mux),
1183SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
1184SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
1185 &rin_inv_mux),
1186
1187SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
1188 NULL, 0),
1189SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
1190 NULL, 0),
1191
1192SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
1193SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
1194
1195SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
1196SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
1197
1198SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
1199SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
1200};
1201
1202static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
1203SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
1204SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
1205
1206SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
1207SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
1208
1209SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
1210SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
1211
1212SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
1213 SND_SOC_DAPM_POST_PMU),
1214
1215SND_SOC_DAPM_PGA("HPL PGA", WM8904_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
1216SND_SOC_DAPM_PGA("HPR PGA", WM8904_POWER_MANAGEMENT_2, 0, 0, NULL, 0),
1217
1218SND_SOC_DAPM_PGA("LINEL PGA", WM8904_POWER_MANAGEMENT_3, 1, 0, NULL, 0),
1219SND_SOC_DAPM_PGA("LINER PGA", WM8904_POWER_MANAGEMENT_3, 0, 0, NULL, 0),
1220
1221SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
1222 0, NULL, 0, out_pga_event,
1223 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1224SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
1225 0, NULL, 0, out_pga_event,
1226 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1227
1228SND_SOC_DAPM_OUTPUT("HPOUTL"),
1229SND_SOC_DAPM_OUTPUT("HPOUTR"),
1230SND_SOC_DAPM_OUTPUT("LINEOUTL"),
1231SND_SOC_DAPM_OUTPUT("LINEOUTR"),
1232};
1233
1234static const char *out_mux_text[] = {
1235 "DAC", "Bypass"
1236};
1237
1238static const struct soc_enum hpl_enum =
1239 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text);
1240
1241static const struct snd_kcontrol_new hpl_mux =
1242 SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1243
1244static const struct soc_enum hpr_enum =
1245 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text);
1246
1247static const struct snd_kcontrol_new hpr_mux =
1248 SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1249
1250static const struct soc_enum linel_enum =
1251 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text);
1252
1253static const struct snd_kcontrol_new linel_mux =
1254 SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1255
1256static const struct soc_enum liner_enum =
1257 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text);
1258
1259static const struct snd_kcontrol_new liner_mux =
1260 SOC_DAPM_ENUM("LINEL Mux", liner_enum);
1261
1262static const char *sidetone_text[] = {
1263 "None", "Left", "Right"
1264};
1265
1266static const struct soc_enum dacl_sidetone_enum =
1267 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text);
1268
1269static const struct snd_kcontrol_new dacl_sidetone_mux =
1270 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1271
1272static const struct soc_enum dacr_sidetone_enum =
1273 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text);
1274
1275static const struct snd_kcontrol_new dacr_sidetone_mux =
1276 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1277
1278static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1279SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1280SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1281SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1282
1283SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1284SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1285
1286SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1287SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1288SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1289SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1290};
1291
1292static const struct snd_soc_dapm_route core_intercon[] = {
1293 { "CLK_DSP", NULL, "SYSCLK" },
1294 { "TOCLK", NULL, "SYSCLK" },
1295};
1296
1297static const struct snd_soc_dapm_route adc_intercon[] = {
1298 { "Left Capture Mux", "IN1L", "IN1L" },
1299 { "Left Capture Mux", "IN2L", "IN2L" },
1300 { "Left Capture Mux", "IN3L", "IN3L" },
1301
1302 { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1303 { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1304 { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1305
1306 { "Right Capture Mux", "IN1R", "IN1R" },
1307 { "Right Capture Mux", "IN2R", "IN2R" },
1308 { "Right Capture Mux", "IN3R", "IN3R" },
1309
1310 { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1311 { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1312 { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1313
1314 { "Left Capture PGA", NULL, "Left Capture Mux" },
1315 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
1316
1317 { "Right Capture PGA", NULL, "Right Capture Mux" },
1318 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
1319
1320 { "AIFOUTL", "Left", "ADCL" },
1321 { "AIFOUTL", "Right", "ADCR" },
1322 { "AIFOUTR", "Left", "ADCL" },
1323 { "AIFOUTR", "Right", "ADCR" },
1324
1325 { "ADCL", NULL, "CLK_DSP" },
1326 { "ADCL", NULL, "Left Capture PGA" },
1327
1328 { "ADCR", NULL, "CLK_DSP" },
1329 { "ADCR", NULL, "Right Capture PGA" },
1330};
1331
1332static const struct snd_soc_dapm_route dac_intercon[] = {
1333 { "DACL", "Right", "AIFINR" },
1334 { "DACL", "Left", "AIFINL" },
1335 { "DACL", NULL, "CLK_DSP" },
1336
1337 { "DACR", "Right", "AIFINR" },
1338 { "DACR", "Left", "AIFINL" },
1339 { "DACR", NULL, "CLK_DSP" },
1340
1341 { "Charge pump", NULL, "SYSCLK" },
1342
1343 { "Headphone Output", NULL, "HPL PGA" },
1344 { "Headphone Output", NULL, "HPR PGA" },
1345 { "Headphone Output", NULL, "Charge pump" },
1346 { "Headphone Output", NULL, "TOCLK" },
1347
1348 { "Line Output", NULL, "LINEL PGA" },
1349 { "Line Output", NULL, "LINER PGA" },
1350 { "Line Output", NULL, "Charge pump" },
1351 { "Line Output", NULL, "TOCLK" },
1352
1353 { "HPOUTL", NULL, "Headphone Output" },
1354 { "HPOUTR", NULL, "Headphone Output" },
1355
1356 { "LINEOUTL", NULL, "Line Output" },
1357 { "LINEOUTR", NULL, "Line Output" },
1358};
1359
1360static const struct snd_soc_dapm_route wm8904_intercon[] = {
1361 { "Left Sidetone", "Left", "ADCL" },
1362 { "Left Sidetone", "Right", "ADCR" },
1363 { "DACL", NULL, "Left Sidetone" },
1364
1365 { "Right Sidetone", "Left", "ADCL" },
1366 { "Right Sidetone", "Right", "ADCR" },
1367 { "DACR", NULL, "Right Sidetone" },
1368
1369 { "Left Bypass", NULL, "Class G" },
1370 { "Left Bypass", NULL, "Left Capture PGA" },
1371
1372 { "Right Bypass", NULL, "Class G" },
1373 { "Right Bypass", NULL, "Right Capture PGA" },
1374
1375 { "HPL Mux", "DAC", "DACL" },
1376 { "HPL Mux", "Bypass", "Left Bypass" },
1377
1378 { "HPR Mux", "DAC", "DACR" },
1379 { "HPR Mux", "Bypass", "Right Bypass" },
1380
1381 { "LINEL Mux", "DAC", "DACL" },
1382 { "LINEL Mux", "Bypass", "Left Bypass" },
1383
1384 { "LINER Mux", "DAC", "DACR" },
1385 { "LINER Mux", "Bypass", "Right Bypass" },
1386
1387 { "HPL PGA", NULL, "HPL Mux" },
1388 { "HPR PGA", NULL, "HPR Mux" },
1389
1390 { "LINEL PGA", NULL, "LINEL Mux" },
1391 { "LINER PGA", NULL, "LINER Mux" },
1392};
1393
1394static int wm8904_add_widgets(struct snd_soc_codec *codec)
1395{
1396 snd_soc_add_controls(codec, wm8904_adc_snd_controls,
1397 ARRAY_SIZE(wm8904_adc_snd_controls));
1398 snd_soc_add_controls(codec, wm8904_dac_snd_controls,
1399 ARRAY_SIZE(wm8904_dac_snd_controls));
1400 snd_soc_add_controls(codec, wm8904_snd_controls,
1401 ARRAY_SIZE(wm8904_snd_controls));
1402
1403 snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets,
1404 ARRAY_SIZE(wm8904_core_dapm_widgets));
1405 snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets,
1406 ARRAY_SIZE(wm8904_adc_dapm_widgets));
1407 snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets,
1408 ARRAY_SIZE(wm8904_dac_dapm_widgets));
1409 snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets,
1410 ARRAY_SIZE(wm8904_dapm_widgets));
1411
1412 snd_soc_dapm_add_routes(codec, core_intercon,
1413 ARRAY_SIZE(core_intercon));
1414 snd_soc_dapm_add_routes(codec, adc_intercon, ARRAY_SIZE(adc_intercon));
1415 snd_soc_dapm_add_routes(codec, dac_intercon, ARRAY_SIZE(dac_intercon));
1416 snd_soc_dapm_add_routes(codec, wm8904_intercon,
1417 ARRAY_SIZE(wm8904_intercon));
1418
1419 snd_soc_dapm_new_widgets(codec);
1420 return 0;
1421}
1422
1423static struct {
1424 int ratio;
1425 unsigned int clk_sys_rate;
1426} clk_sys_rates[] = {
1427 { 64, 0 },
1428 { 128, 1 },
1429 { 192, 2 },
1430 { 256, 3 },
1431 { 384, 4 },
1432 { 512, 5 },
1433 { 786, 6 },
1434 { 1024, 7 },
1435 { 1408, 8 },
1436 { 1536, 9 },
1437};
1438
1439static struct {
1440 int rate;
1441 int sample_rate;
1442} sample_rates[] = {
1443 { 8000, 0 },
1444 { 11025, 1 },
1445 { 12000, 1 },
1446 { 16000, 2 },
1447 { 22050, 3 },
1448 { 24000, 3 },
1449 { 32000, 4 },
1450 { 44100, 5 },
1451 { 48000, 5 },
1452};
1453
1454static struct {
1455 int div; /* *10 due to .5s */
1456 int bclk_div;
1457} bclk_divs[] = {
1458 { 10, 0 },
1459 { 15, 1 },
1460 { 20, 2 },
1461 { 30, 3 },
1462 { 40, 4 },
1463 { 50, 5 },
1464 { 55, 6 },
1465 { 60, 7 },
1466 { 80, 8 },
1467 { 100, 9 },
1468 { 110, 10 },
1469 { 120, 11 },
1470 { 160, 12 },
1471 { 200, 13 },
1472 { 220, 14 },
1473 { 240, 16 },
1474 { 200, 17 },
1475 { 320, 18 },
1476 { 440, 19 },
1477 { 480, 20 },
1478};
1479
1480
1481static int wm8904_hw_params(struct snd_pcm_substream *substream,
1482 struct snd_pcm_hw_params *params,
1483 struct snd_soc_dai *dai)
1484{
1485 struct snd_soc_codec *codec = dai->codec;
1486 struct wm8904_priv *wm8904 = codec->private_data;
1487 int ret, i, best, best_val, cur_val;
1488 unsigned int aif1 = 0;
1489 unsigned int aif2 = 0;
1490 unsigned int aif3 = 0;
1491 unsigned int clock1 = 0;
1492 unsigned int dac_digital1 = 0;
1493
1494 /* What BCLK do we need? */
1495 wm8904->fs = params_rate(params);
1496 if (wm8904->tdm_slots) {
1497 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1498 wm8904->tdm_slots, wm8904->tdm_width);
1499 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1500 wm8904->tdm_width, 2,
1501 wm8904->tdm_slots);
1502 } else {
1503 wm8904->bclk = snd_soc_params_to_bclk(params);
1504 }
1505
1506 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1507
1508 ret = wm8904_configure_clocking(codec);
1509 if (ret != 0)
1510 return ret;
1511
1512 /* Select nearest CLK_SYS_RATE */
1513 best = 0;
1514 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1515 - wm8904->fs);
1516 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1517 cur_val = abs((wm8904->sysclk_rate /
1518 clk_sys_rates[i].ratio) - wm8904->fs);;
1519 if (cur_val < best_val) {
1520 best = i;
1521 best_val = cur_val;
1522 }
1523 }
1524 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1525 clk_sys_rates[best].ratio);
1526 clock1 |= (clk_sys_rates[best].clk_sys_rate
1527 << WM8904_CLK_SYS_RATE_SHIFT);
1528
1529 /* SAMPLE_RATE */
1530 best = 0;
1531 best_val = abs(wm8904->fs - sample_rates[0].rate);
1532 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1533 /* Closest match */
1534 cur_val = abs(wm8904->fs - sample_rates[i].rate);
1535 if (cur_val < best_val) {
1536 best = i;
1537 best_val = cur_val;
1538 }
1539 }
1540 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1541 sample_rates[best].rate);
1542 clock1 |= (sample_rates[best].sample_rate
1543 << WM8904_SAMPLE_RATE_SHIFT);
1544
1545 /* Enable sloping stopband filter for low sample rates */
1546 if (wm8904->fs <= 24000)
1547 dac_digital1 |= WM8904_DAC_SB_FILT;
1548
1549 /* BCLK_DIV */
1550 best = 0;
1551 best_val = INT_MAX;
1552 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1553 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1554 - wm8904->bclk;
1555 if (cur_val < 0) /* Table is sorted */
1556 break;
1557 if (cur_val < best_val) {
1558 best = i;
1559 best_val = cur_val;
1560 }
1561 }
1562 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1563 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1564 bclk_divs[best].div, wm8904->bclk);
1565 aif2 |= bclk_divs[best].bclk_div;
1566
1567 /* LRCLK is a simple fraction of BCLK */
1568 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1569 aif3 |= wm8904->bclk / wm8904->fs;
1570
1571 /* Apply the settings */
1572 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
1573 WM8904_DAC_SB_FILT, dac_digital1);
1574 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1575 WM8904_AIF_WL_MASK, aif1);
1576 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
1577 WM8904_BCLK_DIV_MASK, aif2);
1578 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1579 WM8904_LRCLK_RATE_MASK, aif3);
1580 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
1581 WM8904_SAMPLE_RATE_MASK |
1582 WM8904_CLK_SYS_RATE_MASK, clock1);
1583
1584 /* Update filters for the new settings */
1585 wm8904_set_retune_mobile(codec);
1586 wm8904_set_deemph(codec);
1587
1588 return 0;
1589}
1590
1591
1592static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1593 unsigned int freq, int dir)
1594{
1595 struct snd_soc_codec *codec = dai->codec;
1596 struct wm8904_priv *priv = codec->private_data;
1597
1598 switch (clk_id) {
1599 case WM8904_CLK_MCLK:
1600 priv->sysclk_src = clk_id;
1601 priv->mclk_rate = freq;
1602 break;
1603
1604 case WM8904_CLK_FLL:
1605 priv->sysclk_src = clk_id;
1606 break;
1607
1608 default:
1609 return -EINVAL;
1610 }
1611
1612 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1613
1614 wm8904_configure_clocking(codec);
1615
1616 return 0;
1617}
1618
1619static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1620{
1621 struct snd_soc_codec *codec = dai->codec;
1622 unsigned int aif1 = 0;
1623 unsigned int aif3 = 0;
1624
1625 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1626 case SND_SOC_DAIFMT_CBS_CFS:
1627 break;
1628 case SND_SOC_DAIFMT_CBS_CFM:
1629 aif3 |= WM8904_LRCLK_DIR;
1630 break;
1631 case SND_SOC_DAIFMT_CBM_CFS:
1632 aif1 |= WM8904_BCLK_DIR;
1633 break;
1634 case SND_SOC_DAIFMT_CBM_CFM:
1635 aif1 |= WM8904_BCLK_DIR;
1636 aif3 |= WM8904_LRCLK_DIR;
1637 break;
1638 default:
1639 return -EINVAL;
1640 }
1641
1642 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1643 case SND_SOC_DAIFMT_DSP_B:
1644 aif1 |= WM8904_AIF_LRCLK_INV;
1645 case SND_SOC_DAIFMT_DSP_A:
1646 aif1 |= 0x3;
1647 break;
1648 case SND_SOC_DAIFMT_I2S:
1649 aif1 |= 0x2;
1650 break;
1651 case SND_SOC_DAIFMT_RIGHT_J:
1652 break;
1653 case SND_SOC_DAIFMT_LEFT_J:
1654 aif1 |= 0x1;
1655 break;
1656 default:
1657 return -EINVAL;
1658 }
1659
1660 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1661 case SND_SOC_DAIFMT_DSP_A:
1662 case SND_SOC_DAIFMT_DSP_B:
1663 /* frame inversion not valid for DSP modes */
1664 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1665 case SND_SOC_DAIFMT_NB_NF:
1666 break;
1667 case SND_SOC_DAIFMT_IB_NF:
1668 aif1 |= WM8904_AIF_BCLK_INV;
1669 break;
1670 default:
1671 return -EINVAL;
1672 }
1673 break;
1674
1675 case SND_SOC_DAIFMT_I2S:
1676 case SND_SOC_DAIFMT_RIGHT_J:
1677 case SND_SOC_DAIFMT_LEFT_J:
1678 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1679 case SND_SOC_DAIFMT_NB_NF:
1680 break;
1681 case SND_SOC_DAIFMT_IB_IF:
1682 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1683 break;
1684 case SND_SOC_DAIFMT_IB_NF:
1685 aif1 |= WM8904_AIF_BCLK_INV;
1686 break;
1687 case SND_SOC_DAIFMT_NB_IF:
1688 aif1 |= WM8904_AIF_LRCLK_INV;
1689 break;
1690 default:
1691 return -EINVAL;
1692 }
1693 break;
1694 default:
1695 return -EINVAL;
1696 }
1697
1698 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1699 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1700 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1701 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1702 WM8904_LRCLK_DIR, aif3);
1703
1704 return 0;
1705}
1706
1707
1708static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1709 unsigned int rx_mask, int slots, int slot_width)
1710{
1711 struct snd_soc_codec *codec = dai->codec;
1712 struct wm8904_priv *wm8904 = codec->private_data;
1713 int aif1 = 0;
1714
1715 /* Don't need to validate anything if we're turning off TDM */
1716 if (slots == 0)
1717 goto out;
1718
1719 /* Note that we allow configurations we can't handle ourselves -
1720 * for example, we can generate clocks for slots 2 and up even if
1721 * we can't use those slots ourselves.
1722 */
1723 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1724
1725 switch (rx_mask) {
1726 case 3:
1727 break;
1728 case 0xc:
1729 aif1 |= WM8904_AIFADC_TDM_CHAN;
1730 break;
1731 default:
1732 return -EINVAL;
1733 }
1734
1735
1736 switch (tx_mask) {
1737 case 3:
1738 break;
1739 case 0xc:
1740 aif1 |= WM8904_AIFDAC_TDM_CHAN;
1741 break;
1742 default:
1743 return -EINVAL;
1744 }
1745
1746out:
1747 wm8904->tdm_width = slot_width;
1748 wm8904->tdm_slots = slots / 2;
1749
1750 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1751 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1752 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1753
1754 return 0;
1755}
1756
1757struct _fll_div {
1758 u16 fll_fratio;
1759 u16 fll_outdiv;
1760 u16 fll_clk_ref_div;
1761 u16 n;
1762 u16 k;
1763};
1764
1765/* The size in bits of the FLL divide multiplied by 10
1766 * to allow rounding later */
1767#define FIXED_FLL_SIZE ((1 << 16) * 10)
1768
1769static struct {
1770 unsigned int min;
1771 unsigned int max;
1772 u16 fll_fratio;
1773 int ratio;
1774} fll_fratios[] = {
1775 { 0, 64000, 4, 16 },
1776 { 64000, 128000, 3, 8 },
1777 { 128000, 256000, 2, 4 },
1778 { 256000, 1000000, 1, 2 },
1779 { 1000000, 13500000, 0, 1 },
1780};
1781
1782static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1783 unsigned int Fout)
1784{
1785 u64 Kpart;
1786 unsigned int K, Ndiv, Nmod, target;
1787 unsigned int div;
1788 int i;
1789
1790 /* Fref must be <=13.5MHz */
1791 div = 1;
1792 fll_div->fll_clk_ref_div = 0;
1793 while ((Fref / div) > 13500000) {
1794 div *= 2;
1795 fll_div->fll_clk_ref_div++;
1796
1797 if (div > 8) {
1798 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1799 Fref);
1800 return -EINVAL;
1801 }
1802 }
1803
1804 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1805
1806 /* Apply the division for our remaining calculations */
1807 Fref /= div;
1808
1809 /* Fvco should be 90-100MHz; don't check the upper bound */
1810 div = 4;
1811 while (Fout * div < 90000000) {
1812 div++;
1813 if (div > 64) {
1814 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1815 Fout);
1816 return -EINVAL;
1817 }
1818 }
1819 target = Fout * div;
1820 fll_div->fll_outdiv = div - 1;
1821
1822 pr_debug("Fvco=%dHz\n", target);
1823
1824 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1825 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1826 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1827 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1828 target /= fll_fratios[i].ratio;
1829 break;
1830 }
1831 }
1832 if (i == ARRAY_SIZE(fll_fratios)) {
1833 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1834 return -EINVAL;
1835 }
1836
1837 /* Now, calculate N.K */
1838 Ndiv = target / Fref;
1839
1840 fll_div->n = Ndiv;
1841 Nmod = target % Fref;
1842 pr_debug("Nmod=%d\n", Nmod);
1843
1844 /* Calculate fractional part - scale up so we can round. */
1845 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1846
1847 do_div(Kpart, Fref);
1848
1849 K = Kpart & 0xFFFFFFFF;
1850
1851 if ((K % 10) >= 5)
1852 K += 5;
1853
1854 /* Move down to proper range now rounding is done */
1855 fll_div->k = K / 10;
1856
1857 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1858 fll_div->n, fll_div->k,
1859 fll_div->fll_fratio, fll_div->fll_outdiv,
1860 fll_div->fll_clk_ref_div);
1861
1862 return 0;
1863}
1864
1865static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1866 unsigned int Fref, unsigned int Fout)
1867{
1868 struct snd_soc_codec *codec = dai->codec;
1869 struct wm8904_priv *wm8904 = codec->private_data;
1870 struct _fll_div fll_div;
1871 int ret, val;
1872 int clock2, fll1;
1873
1874 /* Any change? */
1875 if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1876 Fout == wm8904->fll_fout)
1877 return 0;
1878
1879 if (Fout == 0) {
1880 dev_dbg(codec->dev, "FLL disabled\n");
1881
1882 wm8904->fll_fref = 0;
1883 wm8904->fll_fout = 0;
1884
1885 /* Gate SYSCLK to avoid glitches */
1886 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1887 WM8904_CLK_SYS_ENA, 0);
1888
1889 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1890 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1891
1892 goto out;
1893 }
1894
1895 /* Validate the FLL ID */
1896 switch (source) {
1897 case WM8904_FLL_MCLK:
1898 case WM8904_FLL_LRCLK:
1899 case WM8904_FLL_BCLK:
1900 ret = fll_factors(&fll_div, Fref, Fout);
1901 if (ret != 0)
1902 return ret;
1903 break;
1904
1905 case WM8904_FLL_FREE_RUNNING:
1906 dev_dbg(codec->dev, "Using free running FLL\n");
1907 /* Force 12MHz and output/4 for now */
1908 Fout = 12000000;
1909 Fref = 12000000;
1910
1911 memset(&fll_div, 0, sizeof(fll_div));
1912 fll_div.fll_outdiv = 3;
1913 break;
1914
1915 default:
1916 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
1917 return -EINVAL;
1918 }
1919
1920 /* Save current state then disable the FLL and SYSCLK to avoid
1921 * misclocking */
1922 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
1923 fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
1924 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1925 WM8904_CLK_SYS_ENA, 0);
1926 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1927 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1928
1929 /* Unlock forced oscilator control to switch it on/off */
1930 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1931 WM8904_USER_KEY, WM8904_USER_KEY);
1932
1933 if (fll_id == WM8904_FLL_FREE_RUNNING) {
1934 val = WM8904_FLL_FRC_NCO;
1935 } else {
1936 val = 0;
1937 }
1938
1939 snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1940 val);
1941 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1942 WM8904_USER_KEY, 0);
1943
1944 switch (fll_id) {
1945 case WM8904_FLL_MCLK:
1946 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1947 WM8904_FLL_CLK_REF_SRC_MASK, 0);
1948 break;
1949
1950 case WM8904_FLL_LRCLK:
1951 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1952 WM8904_FLL_CLK_REF_SRC_MASK, 1);
1953 break;
1954
1955 case WM8904_FLL_BCLK:
1956 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1957 WM8904_FLL_CLK_REF_SRC_MASK, 2);
1958 break;
1959 }
1960
1961 if (fll_div.k)
1962 val = WM8904_FLL_FRACN_ENA;
1963 else
1964 val = 0;
1965 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1966 WM8904_FLL_FRACN_ENA, val);
1967
1968 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
1969 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
1970 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
1971 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
1972
1973 snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
1974
1975 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
1976 fll_div.n << WM8904_FLL_N_SHIFT);
1977
1978 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1979 WM8904_FLL_CLK_REF_DIV_MASK,
1980 fll_div.fll_clk_ref_div
1981 << WM8904_FLL_CLK_REF_DIV_SHIFT);
1982
1983 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1984
1985 wm8904->fll_fref = Fref;
1986 wm8904->fll_fout = Fout;
1987 wm8904->fll_src = source;
1988
1989 /* Enable the FLL if it was previously active */
1990 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1991 WM8904_FLL_OSC_ENA, fll1);
1992 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1993 WM8904_FLL_ENA, fll1);
1994
1995out:
1996 /* Reenable SYSCLK if it was previously active */
1997 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1998 WM8904_CLK_SYS_ENA, clock2);
1999
2000 return 0;
2001}
2002
2003static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2004{
2005 struct snd_soc_codec *codec = codec_dai->codec;
2006 int val;
2007
2008 if (mute)
2009 val = WM8904_DAC_MUTE;
2010 else
2011 val = 0;
2012
2013 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
2014
2015 return 0;
2016}
2017
2018static int wm8904_set_bias_level(struct snd_soc_codec *codec,
2019 enum snd_soc_bias_level level)
2020{
2021 struct wm8904_priv *wm8904 = codec->private_data;
2022 int ret, i;
2023
2024 switch (level) {
2025 case SND_SOC_BIAS_ON:
2026 break;
2027
2028 case SND_SOC_BIAS_PREPARE:
2029 /* VMID resistance 2*50k */
2030 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2031 WM8904_VMID_RES_MASK,
2032 0x1 << WM8904_VMID_RES_SHIFT);
2033
2034 /* Normal bias current */
2035 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2036 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
2037 break;
2038
2039 case SND_SOC_BIAS_STANDBY:
2040 if (codec->bias_level == SND_SOC_BIAS_OFF) {
2041 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2042 wm8904->supplies);
2043 if (ret != 0) {
2044 dev_err(codec->dev,
2045 "Failed to enable supplies: %d\n",
2046 ret);
2047 return ret;
2048 }
2049
2050 /* Sync back cached values if they're
2051 * different from the hardware default.
2052 */
2053 for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) {
2054 if (!wm8904_access[i].writable)
2055 continue;
2056
2057 if (wm8904->reg_cache[i] == wm8904_reg[i])
2058 continue;
2059
2060 snd_soc_write(codec, i, wm8904->reg_cache[i]);
2061 }
2062
2063 /* Enable bias */
2064 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2065 WM8904_BIAS_ENA, WM8904_BIAS_ENA);
2066
2067 /* Enable VMID, VMID buffering, 2*5k resistance */
2068 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2069 WM8904_VMID_ENA |
2070 WM8904_VMID_RES_MASK,
2071 WM8904_VMID_ENA |
2072 0x3 << WM8904_VMID_RES_SHIFT);
2073
2074 /* Let VMID ramp */
2075 msleep(1);
2076 }
2077
2078 /* Maintain VMID with 2*250k */
2079 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2080 WM8904_VMID_RES_MASK,
2081 0x2 << WM8904_VMID_RES_SHIFT);
2082
2083 /* Bias current *0.5 */
2084 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2085 WM8904_ISEL_MASK, 0);
2086 break;
2087
2088 case SND_SOC_BIAS_OFF:
2089 /* Turn off VMID */
2090 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2091 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
2092
2093 /* Stop bias generation */
2094 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2095 WM8904_BIAS_ENA, 0);
2096
2097 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
2098 wm8904->supplies);
2099 break;
2100 }
2101 codec->bias_level = level;
2102 return 0;
2103}
2104
2105#define WM8904_RATES SNDRV_PCM_RATE_8000_96000
2106
2107#define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2108 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2109
2110static struct snd_soc_dai_ops wm8904_dai_ops = {
2111 .set_sysclk = wm8904_set_sysclk,
2112 .set_fmt = wm8904_set_fmt,
2113 .set_tdm_slot = wm8904_set_tdm_slot,
2114 .set_pll = wm8904_set_fll,
2115 .hw_params = wm8904_hw_params,
2116 .digital_mute = wm8904_digital_mute,
2117};
2118
2119struct snd_soc_dai wm8904_dai = {
2120 .name = "WM8904",
2121 .playback = {
2122 .stream_name = "Playback",
2123 .channels_min = 2,
2124 .channels_max = 2,
2125 .rates = WM8904_RATES,
2126 .formats = WM8904_FORMATS,
2127 },
2128 .capture = {
2129 .stream_name = "Capture",
2130 .channels_min = 2,
2131 .channels_max = 2,
2132 .rates = WM8904_RATES,
2133 .formats = WM8904_FORMATS,
2134 },
2135 .ops = &wm8904_dai_ops,
2136 .symmetric_rates = 1,
2137};
2138EXPORT_SYMBOL_GPL(wm8904_dai);
2139
2140#ifdef CONFIG_PM
2141static int wm8904_suspend(struct platform_device *pdev, pm_message_t state)
2142{
2143 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2144 struct snd_soc_codec *codec = socdev->card->codec;
2145
2146 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF);
2147
2148 return 0;
2149}
2150
2151static int wm8904_resume(struct platform_device *pdev)
2152{
2153 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2154 struct snd_soc_codec *codec = socdev->card->codec;
2155
2156 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2157
2158 return 0;
2159}
2160#else
2161#define wm8904_suspend NULL
2162#define wm8904_resume NULL
2163#endif
2164
2165static void wm8904_handle_retune_mobile_pdata(struct wm8904_priv *wm8904)
2166{
2167 struct snd_soc_codec *codec = &wm8904->codec;
2168 struct wm8904_pdata *pdata = wm8904->pdata;
2169 struct snd_kcontrol_new control =
2170 SOC_ENUM_EXT("EQ Mode",
2171 wm8904->retune_mobile_enum,
2172 wm8904_get_retune_mobile_enum,
2173 wm8904_put_retune_mobile_enum);
2174 int ret, i, j;
2175 const char **t;
2176
2177 /* We need an array of texts for the enum API but the number
2178 * of texts is likely to be less than the number of
2179 * configurations due to the sample rate dependency of the
2180 * configurations. */
2181 wm8904->num_retune_mobile_texts = 0;
2182 wm8904->retune_mobile_texts = NULL;
2183 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2184 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
2185 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2186 wm8904->retune_mobile_texts[j]) == 0)
2187 break;
2188 }
2189
2190 if (j != wm8904->num_retune_mobile_texts)
2191 continue;
2192
2193 /* Expand the array... */
2194 t = krealloc(wm8904->retune_mobile_texts,
2195 sizeof(char *) *
2196 (wm8904->num_retune_mobile_texts + 1),
2197 GFP_KERNEL);
2198 if (t == NULL)
2199 continue;
2200
2201 /* ...store the new entry... */
2202 t[wm8904->num_retune_mobile_texts] =
2203 pdata->retune_mobile_cfgs[i].name;
2204
2205 /* ...and remember the new version. */
2206 wm8904->num_retune_mobile_texts++;
2207 wm8904->retune_mobile_texts = t;
2208 }
2209
2210 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2211 wm8904->num_retune_mobile_texts);
2212
2213 wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts;
2214 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
2215
2216 ret = snd_soc_add_controls(&wm8904->codec, &control, 1);
2217 if (ret != 0)
2218 dev_err(wm8904->codec.dev,
2219 "Failed to add ReTune Mobile control: %d\n", ret);
2220}
2221
2222static void wm8904_handle_pdata(struct wm8904_priv *wm8904)
2223{
2224 struct snd_soc_codec *codec = &wm8904->codec;
2225 struct wm8904_pdata *pdata = wm8904->pdata;
2226 int ret, i;
2227
2228 if (!pdata) {
2229 snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls,
2230 ARRAY_SIZE(wm8904_eq_controls));
2231 return;
2232 }
2233
2234 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2235
2236 if (pdata->num_drc_cfgs) {
2237 struct snd_kcontrol_new control =
2238 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2239 wm8904_get_drc_enum, wm8904_put_drc_enum);
2240
2241 /* We need an array of texts for the enum API */
2242 wm8904->drc_texts = kmalloc(sizeof(char *)
2243 * pdata->num_drc_cfgs, GFP_KERNEL);
2244 if (!wm8904->drc_texts) {
2245 dev_err(wm8904->codec.dev,
2246 "Failed to allocate %d DRC config texts\n",
2247 pdata->num_drc_cfgs);
2248 return;
2249 }
2250
2251 for (i = 0; i < pdata->num_drc_cfgs; i++)
2252 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2253
2254 wm8904->drc_enum.max = pdata->num_drc_cfgs;
2255 wm8904->drc_enum.texts = wm8904->drc_texts;
2256
2257 ret = snd_soc_add_controls(&wm8904->codec, &control, 1);
2258 if (ret != 0)
2259 dev_err(wm8904->codec.dev,
2260 "Failed to add DRC mode control: %d\n", ret);
2261
2262 wm8904_set_drc(codec);
2263 }
2264
2265 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2266 pdata->num_retune_mobile_cfgs);
2267
2268 if (pdata->num_retune_mobile_cfgs)
2269 wm8904_handle_retune_mobile_pdata(wm8904);
2270 else
2271 snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls,
2272 ARRAY_SIZE(wm8904_eq_controls));
2273}
2274
2275static int wm8904_probe(struct platform_device *pdev)
2276{
2277 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2278 struct snd_soc_codec *codec;
2279 int ret = 0;
2280
2281 if (wm8904_codec == NULL) {
2282 dev_err(&pdev->dev, "Codec device not registered\n");
2283 return -ENODEV;
2284 }
2285
2286 socdev->card->codec = wm8904_codec;
2287 codec = wm8904_codec;
2288
2289 /* register pcms */
2290 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2291 if (ret < 0) {
2292 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
2293 goto pcm_err;
2294 }
2295
2296 wm8904_handle_pdata(codec->private_data);
2297
2298 wm8904_add_widgets(codec);
2299
2300 return ret;
2301
2302pcm_err:
2303 return ret;
2304}
2305
2306static int wm8904_remove(struct platform_device *pdev)
2307{
2308 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2309
2310 snd_soc_free_pcms(socdev);
2311 snd_soc_dapm_free(socdev);
2312
2313 return 0;
2314}
2315
2316struct snd_soc_codec_device soc_codec_dev_wm8904 = {
2317 .probe = wm8904_probe,
2318 .remove = wm8904_remove,
2319 .suspend = wm8904_suspend,
2320 .resume = wm8904_resume,
2321};
2322EXPORT_SYMBOL_GPL(soc_codec_dev_wm8904);
2323
2324static int wm8904_register(struct wm8904_priv *wm8904,
2325 enum snd_soc_control_type control)
2326{
2327 int ret;
2328 struct snd_soc_codec *codec = &wm8904->codec;
2329 int i;
2330
2331 if (wm8904_codec) {
2332 dev_err(codec->dev, "Another WM8904 is registered\n");
2333 return -EINVAL;
2334 }
2335
2336 mutex_init(&codec->mutex);
2337 INIT_LIST_HEAD(&codec->dapm_widgets);
2338 INIT_LIST_HEAD(&codec->dapm_paths);
2339
2340 codec->private_data = wm8904;
2341 codec->name = "WM8904";
2342 codec->owner = THIS_MODULE;
2343 codec->bias_level = SND_SOC_BIAS_OFF;
2344 codec->set_bias_level = wm8904_set_bias_level;
2345 codec->dai = &wm8904_dai;
2346 codec->num_dai = 1;
2347 codec->reg_cache_size = WM8904_MAX_REGISTER;
2348 codec->reg_cache = &wm8904->reg_cache;
2349 codec->volatile_register = wm8904_volatile_register;
2350
2351 memcpy(codec->reg_cache, wm8904_reg, sizeof(wm8904_reg));
2352
2353 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
2354 if (ret != 0) {
2355 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2356 goto err;
2357 }
2358
2359 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2360 wm8904->supplies[i].supply = wm8904_supply_names[i];
2361
2362 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies),
2363 wm8904->supplies);
2364 if (ret != 0) {
2365 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2366 goto err;
2367 }
2368
2369 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2370 wm8904->supplies);
2371 if (ret != 0) {
2372 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2373 goto err_get;
2374 }
2375
2376 ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID);
2377 if (ret < 0) {
2378 dev_err(codec->dev, "Failed to read ID register\n");
2379 goto err_enable;
2380 }
2381 if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) {
2382 dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret);
2383 ret = -EINVAL;
2384 goto err_enable;
2385 }
2386
2387 ret = snd_soc_read(codec, WM8904_REVISION);
2388 if (ret < 0) {
2389 dev_err(codec->dev, "Failed to read device revision: %d\n",
2390 ret);
2391 goto err_enable;
2392 }
2393 dev_info(codec->dev, "revision %c\n", ret + 'A');
2394
2395 ret = wm8904_reset(codec);
2396 if (ret < 0) {
2397 dev_err(codec->dev, "Failed to issue reset\n");
2398 goto err_enable;
2399 }
2400
2401 wm8904_dai.dev = codec->dev;
2402
2403 /* Change some default settings - latch VU and enable ZC */
2404 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU;
2405 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU;
2406 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU;
2407 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU;
2408 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU |
2409 WM8904_HPOUTLZC;
2410 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU |
2411 WM8904_HPOUTRZC;
2412 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU |
2413 WM8904_LINEOUTLZC;
2414 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU |
2415 WM8904_LINEOUTRZC;
2416 wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
2417
2418 /* Set Class W by default - this will be managed by the Class
2419 * G widget at runtime where bypass paths are available.
2420 */
2421 wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR;
2422
2423 /* Use normal bias source */
2424 wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL;
2425
2426 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2427
2428 /* Bias level configuration will have done an extra enable */
2429 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2430
2431 wm8904_codec = codec;
2432
2433 ret = snd_soc_register_codec(codec);
2434 if (ret != 0) {
2435 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2436 return ret;
2437 }
2438
2439 ret = snd_soc_register_dai(&wm8904_dai);
2440 if (ret != 0) {
2441 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
2442 snd_soc_unregister_codec(codec);
2443 return ret;
2444 }
2445
2446 return 0;
2447
2448err_enable:
2449 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2450err_get:
2451 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2452err:
2453 kfree(wm8904);
2454 return ret;
2455}
2456
2457static void wm8904_unregister(struct wm8904_priv *wm8904)
2458{
2459 wm8904_set_bias_level(&wm8904->codec, SND_SOC_BIAS_OFF);
2460 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2461 snd_soc_unregister_dai(&wm8904_dai);
2462 snd_soc_unregister_codec(&wm8904->codec);
2463 kfree(wm8904);
2464 wm8904_codec = NULL;
2465}
2466
2467#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2468static __devinit int wm8904_i2c_probe(struct i2c_client *i2c,
2469 const struct i2c_device_id *id)
2470{
2471 struct wm8904_priv *wm8904;
2472 struct snd_soc_codec *codec;
2473
2474 wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL);
2475 if (wm8904 == NULL)
2476 return -ENOMEM;
2477
2478 codec = &wm8904->codec;
2479 codec->hw_write = (hw_write_t)i2c_master_send;
2480
2481 i2c_set_clientdata(i2c, wm8904);
2482 codec->control_data = i2c;
2483 wm8904->pdata = i2c->dev.platform_data;
2484
2485 codec->dev = &i2c->dev;
2486
2487 return wm8904_register(wm8904, SND_SOC_I2C);
2488}
2489
2490static __devexit int wm8904_i2c_remove(struct i2c_client *client)
2491{
2492 struct wm8904_priv *wm8904 = i2c_get_clientdata(client);
2493 wm8904_unregister(wm8904);
2494 return 0;
2495}
2496
2497static const struct i2c_device_id wm8904_i2c_id[] = {
2498 { "wm8904", 0 },
2499 { }
2500};
2501MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2502
2503static struct i2c_driver wm8904_i2c_driver = {
2504 .driver = {
2505 .name = "WM8904",
2506 .owner = THIS_MODULE,
2507 },
2508 .probe = wm8904_i2c_probe,
2509 .remove = __devexit_p(wm8904_i2c_remove),
2510 .id_table = wm8904_i2c_id,
2511};
2512#endif
2513
2514static int __init wm8904_modinit(void)
2515{
2516 int ret;
2517#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2518 ret = i2c_add_driver(&wm8904_i2c_driver);
2519 if (ret != 0) {
2520 printk(KERN_ERR "Failed to register WM8904 I2C driver: %d\n",
2521 ret);
2522 }
2523#endif
2524 return 0;
2525}
2526module_init(wm8904_modinit);
2527
2528static void __exit wm8904_exit(void)
2529{
2530#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2531 i2c_del_driver(&wm8904_i2c_driver);
2532#endif
2533}
2534module_exit(wm8904_exit);
2535
2536MODULE_DESCRIPTION("ASoC WM8904 driver");
2537MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2538MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 17:14:06 -0500