diff options
| author | André Goddard Rosa <andre.goddard@gmail.com> | 2009-11-14 10:09:05 -0500 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2009-12-04 09:39:55 -0500 |
| commit | af901ca181d92aac3a7dc265144a9081a86d8f39 (patch) | |
| tree | 380054af22521144fbe1364c3bcd55ad24c9bde4 /sound/soc/codecs/wm8903.c | |
| parent | 972b94ffb90ea6d20c589d9a47215df103388ddd (diff) | |
tree-wide: fix assorted typos all over the place
That is "success", "unknown", "through", "performance", "[re|un]mapping"
, "access", "default", "reasonable", "[con]currently", "temperature"
, "channel", "[un]used", "application", "example","hierarchy", "therefore"
, "[over|under]flow", "contiguous", "threshold", "enough" and others.
Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'sound/soc/codecs/wm8903.c')
| -rw-r--r-- | sound/soc/codecs/wm8903.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index fe1307b500cf..d72347d90b70 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c | |||
| @@ -607,7 +607,7 @@ SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, | |||
| 607 | SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), | 607 | SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), |
| 608 | SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), | 608 | SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), |
| 609 | SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), | 609 | SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), |
| 610 | SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1, | 610 | SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, |
| 611 | drc_tlv_thresh), | 611 | drc_tlv_thresh), |
| 612 | SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), | 612 | SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), |
| 613 | SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), | 613 | SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), |
| @@ -617,11 +617,11 @@ SOC_ENUM("DRC Decay Rate", drc_decay), | |||
| 617 | SOC_ENUM("DRC FF Delay", drc_ff_delay), | 617 | SOC_ENUM("DRC FF Delay", drc_ff_delay), |
| 618 | SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), | 618 | SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), |
| 619 | SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), | 619 | SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), |
| 620 | SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), | 620 | SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), |
| 621 | SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), | 621 | SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), |
| 622 | SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), | 622 | SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), |
| 623 | SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), | 623 | SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), |
| 624 | SOC_ENUM("DRC Smoothing Threashold", drc_smoothing), | 624 | SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), |
| 625 | SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), | 625 | SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), |
| 626 | 626 | ||
| 627 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, | 627 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, |