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authorMark Brown <broonie@opensource.wolfsonmicro.com>2008-08-04 07:06:45 -0400
committerJaroslav Kysela <perex@perex.cz>2008-08-06 09:40:17 -0400
commit0e0e16a87a0b973702feb572c2552d82e1aec5b9 (patch)
treeeab346cfcd8617c938c107d942e183d6dc751c88 /sound/soc/codecs/wm8900.c
parent8c650087992f1d7a3a7be2e632f4e85a52d20619 (diff)
ALSA: ASoC: Add WM8900 CODEC driver
The WM8900 is designed for portable multimedia applications requiring low power consumption, high performance audio and a compact form factor providing: - 24 bit stereo ADC and DAC - Microphone and line inputs - Line outputs - Class G headphone amplifier Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
Diffstat (limited to 'sound/soc/codecs/wm8900.c')
-rw-r--r--sound/soc/codecs/wm8900.c1542
1 files changed, 1542 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
new file mode 100644
index 000000000000..0b8c6d38b48f
--- /dev/null
+++ b/sound/soc/codecs/wm8900.c
@@ -0,0 +1,1542 @@
1/*
2 * wm8900.c -- WM8900 ALSA Soc Audio driver
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - Tristating.
14 * - TDM.
15 * - Jack detect.
16 * - FLL source configuration, currently only MCLK is supported.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/version.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/pm.h>
26#include <linux/i2c.h>
27#include <linux/platform_device.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35
36#include "wm8900.h"
37
38/* WM8900 register space */
39#define WM8900_REG_RESET 0x0
40#define WM8900_REG_ID 0x0
41#define WM8900_REG_POWER1 0x1
42#define WM8900_REG_POWER2 0x2
43#define WM8900_REG_POWER3 0x3
44#define WM8900_REG_AUDIO1 0x4
45#define WM8900_REG_AUDIO2 0x5
46#define WM8900_REG_CLOCKING1 0x6
47#define WM8900_REG_CLOCKING2 0x7
48#define WM8900_REG_AUDIO3 0x8
49#define WM8900_REG_AUDIO4 0x9
50#define WM8900_REG_DACCTRL 0xa
51#define WM8900_REG_LDAC_DV 0xb
52#define WM8900_REG_RDAC_DV 0xc
53#define WM8900_REG_SIDETONE 0xd
54#define WM8900_REG_ADCCTRL 0xe
55#define WM8900_REG_LADC_DV 0xf
56#define WM8900_REG_RADC_DV 0x10
57#define WM8900_REG_GPIO 0x12
58#define WM8900_REG_INCTL 0x15
59#define WM8900_REG_LINVOL 0x16
60#define WM8900_REG_RINVOL 0x17
61#define WM8900_REG_INBOOSTMIX1 0x18
62#define WM8900_REG_INBOOSTMIX2 0x19
63#define WM8900_REG_ADCPATH 0x1a
64#define WM8900_REG_AUXBOOST 0x1b
65#define WM8900_REG_ADDCTL 0x1e
66#define WM8900_REG_FLLCTL1 0x24
67#define WM8900_REG_FLLCTL2 0x25
68#define WM8900_REG_FLLCTL3 0x26
69#define WM8900_REG_FLLCTL4 0x27
70#define WM8900_REG_FLLCTL5 0x28
71#define WM8900_REG_FLLCTL6 0x29
72#define WM8900_REG_LOUTMIXCTL1 0x2c
73#define WM8900_REG_ROUTMIXCTL1 0x2d
74#define WM8900_REG_BYPASS1 0x2e
75#define WM8900_REG_BYPASS2 0x2f
76#define WM8900_REG_AUXOUT_CTL 0x30
77#define WM8900_REG_LOUT1CTL 0x33
78#define WM8900_REG_ROUT1CTL 0x34
79#define WM8900_REG_LOUT2CTL 0x35
80#define WM8900_REG_ROUT2CTL 0x36
81#define WM8900_REG_HPCTL1 0x3a
82#define WM8900_REG_OUTBIASCTL 0x73
83
84#define WM8900_MAXREG 0x80
85
86#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
87#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
88#define WM8900_REG_ADDCTL_VMID_DIS 0x20
89#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
90#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
91#define WM8900_REG_ADDCTL_TEMP_SD 0x02
92
93#define WM8900_REG_GPIO_TEMP_ENA 0x2
94
95#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
96#define WM8900_REG_POWER1_BIAS_ENA 0x0008
97#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
98#define WM8900_REG_POWER1_FLL_ENA 0x0040
99
100#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
101#define WM8900_REG_POWER2_ADCL_ENA 0x0002
102#define WM8900_REG_POWER2_ADCR_ENA 0x0001
103
104#define WM8900_REG_POWER3_DACL_ENA 0x0002
105#define WM8900_REG_POWER3_DACR_ENA 0x0001
106
107#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
108#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
109#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
110
111#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
112#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
113#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
114#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
115
116#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
117#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
118
119#define WM8900_REG_DACCTRL_MUTE 0x004
120#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
121
122#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
123
124#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
125
126#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
127
128#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
129
130#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
131#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
132#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
133#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
134#define WM8900_REG_HPCTL1_HP_SHORT 0x08
135#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
136
137#define WM8900_LRC_MASK 0xfc00
138
139struct snd_soc_codec_device soc_codec_dev_wm8900;
140
141struct wm8900_priv {
142 u32 fll_in; /* FLL input frequency */
143 u32 fll_out; /* FLL output frequency */
144};
145
146/*
147 * wm8900 register cache. We can't read the entire register space and we
148 * have slow control buses so we cache the registers.
149 */
150static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
151 0x8900, 0x0000,
152 0xc000, 0x0000,
153 0x4050, 0x4000,
154 0x0008, 0x0000,
155 0x0040, 0x0040,
156 0x1004, 0x00c0,
157 0x00c0, 0x0000,
158 0x0100, 0x00c0,
159 0x00c0, 0x0000,
160 0xb001, 0x0000,
161 0x0000, 0x0044,
162 0x004c, 0x004c,
163 0x0044, 0x0044,
164 0x0000, 0x0044,
165 0x0000, 0x0000,
166 0x0002, 0x0000,
167 0x0000, 0x0000,
168 0x0000, 0x0000,
169 0x0008, 0x0000,
170 0x0000, 0x0008,
171 0x0097, 0x0100,
172 0x0000, 0x0000,
173 0x0050, 0x0050,
174 0x0055, 0x0055,
175 0x0055, 0x0000,
176 0x0000, 0x0079,
177 0x0079, 0x0079,
178 0x0079, 0x0000,
179 /* Remaining registers all zero */
180};
181
182/*
183 * read wm8900 register cache
184 */
185static inline unsigned int wm8900_read_reg_cache(struct snd_soc_codec *codec,
186 unsigned int reg)
187{
188 u16 *cache = codec->reg_cache;
189
190 BUG_ON(reg >= WM8900_MAXREG);
191
192 if (reg == WM8900_REG_ID)
193 return 0;
194
195 return cache[reg];
196}
197
198/*
199 * write wm8900 register cache
200 */
201static inline void wm8900_write_reg_cache(struct snd_soc_codec *codec,
202 u16 reg, unsigned int value)
203{
204 u16 *cache = codec->reg_cache;
205
206 BUG_ON(reg >= WM8900_MAXREG);
207
208 cache[reg] = value;
209}
210
211/*
212 * write to the WM8900 register space
213 */
214static int wm8900_write(struct snd_soc_codec *codec, unsigned int reg,
215 unsigned int value)
216{
217 u8 data[3];
218
219 if (value == wm8900_read_reg_cache(codec, reg))
220 return 0;
221
222 /* data is
223 * D15..D9 WM8900 register offset
224 * D8...D0 register data
225 */
226 data[0] = reg;
227 data[1] = value >> 8;
228 data[2] = value & 0x00ff;
229
230 wm8900_write_reg_cache(codec, reg, value);
231 if (codec->hw_write(codec->control_data, data, 3) == 3)
232 return 0;
233 else
234 return -EIO;
235}
236
237/*
238 * Read from the wm8900.
239 */
240static unsigned int wm8900_chip_read(struct snd_soc_codec *codec, u8 reg)
241{
242 struct i2c_msg xfer[2];
243 u16 data;
244 int ret;
245 struct i2c_client *client = codec->control_data;
246
247 BUG_ON(reg != WM8900_REG_ID && reg != WM8900_REG_POWER1);
248
249 /* Write register */
250 xfer[0].addr = client->addr;
251 xfer[0].flags = 0;
252 xfer[0].len = 1;
253 xfer[0].buf = &reg;
254
255 /* Read data */
256 xfer[1].addr = client->addr;
257 xfer[1].flags = I2C_M_RD;
258 xfer[1].len = 2;
259 xfer[1].buf = (u8 *)&data;
260
261 ret = i2c_transfer(client->adapter, xfer, 2);
262 if (ret != 2) {
263 printk(KERN_CRIT "i2c_transfer returned %d\n", ret);
264 return 0;
265 }
266
267 return (data >> 8) | ((data & 0xff) << 8);
268}
269
270/*
271 * Read from the WM8900 register space. Most registers can't be read
272 * and are therefore supplied from cache.
273 */
274static unsigned int wm8900_read(struct snd_soc_codec *codec, unsigned int reg)
275{
276 switch (reg) {
277 case WM8900_REG_ID:
278 return wm8900_chip_read(codec, reg);
279 default:
280 return wm8900_read_reg_cache(codec, reg);
281 }
282}
283
284static void wm8900_reset(struct snd_soc_codec *codec)
285{
286 wm8900_write(codec, WM8900_REG_RESET, 0);
287
288 memcpy(codec->reg_cache, wm8900_reg_defaults,
289 sizeof(codec->reg_cache));
290}
291
292static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
293 struct snd_kcontrol *kcontrol, int event)
294{
295 struct snd_soc_codec *codec = w->codec;
296 u16 hpctl1 = wm8900_read(codec, WM8900_REG_HPCTL1);
297
298 switch (event) {
299 case SND_SOC_DAPM_PRE_PMU:
300 /* Clamp headphone outputs */
301 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
302 WM8900_REG_HPCTL1_HP_CLAMP_OP;
303 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
304 break;
305
306 case SND_SOC_DAPM_POST_PMU:
307 /* Enable the input stage */
308 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
309 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
310 WM8900_REG_HPCTL1_HP_SHORT2 |
311 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
312 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
313
314 msleep(400);
315
316 /* Enable the output stage */
317 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
318 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
319 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
320
321 /* Remove the shorts */
322 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
323 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
324 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
325 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
326 break;
327
328 case SND_SOC_DAPM_PRE_PMD:
329 /* Short the output */
330 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
331 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
332
333 /* Disable the output stage */
334 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
335 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
336
337 /* Clamp the outputs and power down input */
338 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
339 WM8900_REG_HPCTL1_HP_CLAMP_OP;
340 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
341 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
342 break;
343
344 case SND_SOC_DAPM_POST_PMD:
345 /* Disable everything */
346 wm8900_write(codec, WM8900_REG_HPCTL1, 0);
347 break;
348
349 default:
350 BUG();
351 }
352
353 return 0;
354}
355
356static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
357
358static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
359
360static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
361
362static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
363
364static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
365
366static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
367
368static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
369
370static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
371
372static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
373
374static const struct soc_enum mic_bias_level =
375SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
376
377static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
378
379static const struct soc_enum dac_mute_rate =
380SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
381
382static const char *dac_deemphasis_txt[] = {
383 "Disabled", "32kHz", "44.1kHz", "48kHz"
384};
385
386static const struct soc_enum dac_deemphasis =
387SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
388
389static const char *adc_hpf_cut_txt[] = {
390 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
391};
392
393static const struct soc_enum adc_hpf_cut =
394SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
395
396static const char *lr_txt[] = {
397 "Left", "Right"
398};
399
400static const struct soc_enum aifl_src =
401SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
402
403static const struct soc_enum aifr_src =
404SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
405
406static const struct soc_enum dacl_src =
407SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
408
409static const struct soc_enum dacr_src =
410SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
411
412static const char *sidetone_txt[] = {
413 "Disabled", "Left ADC", "Right ADC"
414};
415
416static const struct soc_enum dacl_sidetone =
417SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
418
419static const struct soc_enum dacr_sidetone =
420SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
421
422static const struct snd_kcontrol_new wm8900_snd_controls[] = {
423SOC_ENUM("Mic Bias Level", mic_bias_level),
424
425SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
426 in_pga_tlv),
427SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
428SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
429
430SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
431 in_pga_tlv),
432SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
433SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
434
435SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
436SOC_ENUM("DAC Mute Rate", dac_mute_rate),
437SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
438SOC_ENUM("DAC Deemphasis", dac_deemphasis),
439SOC_SINGLE("DAC Sloping Stopband Filter Switch", WM8900_REG_DACCTRL, 8, 1, 0),
440SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
441 12, 1, 0),
442
443SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
444SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
445SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
446SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
447 adc_svol_tlv),
448SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
449 adc_svol_tlv),
450SOC_ENUM("Left Digital Audio Source", aifl_src),
451SOC_ENUM("Right Digital Audio Source", aifr_src),
452
453SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
454 dac_boost_tlv),
455SOC_ENUM("Left DAC Source", dacl_src),
456SOC_ENUM("Right DAC Source", dacr_src),
457SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
458SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
459SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
460
461SOC_DOUBLE_R_TLV("Digital Playback Volume",
462 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
463 1, 96, 0, dac_tlv),
464SOC_DOUBLE_R_TLV("Digital Capture Volume",
465 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
466
467SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
468 out_mix_tlv),
469SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
470 out_mix_tlv),
471SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
472 out_mix_tlv),
473SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
474 out_mix_tlv),
475
476SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
477 out_mix_tlv),
478SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
479 out_mix_tlv),
480SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
481 out_mix_tlv),
482SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
483 out_mix_tlv),
484
485SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
486 in_boost_tlv),
487SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
488 in_boost_tlv),
489SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
490 in_boost_tlv),
491SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
492 in_boost_tlv),
493SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
494 in_boost_tlv),
495SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
496 in_boost_tlv),
497
498SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
499 0, 63, 0, out_pga_tlv),
500SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
501 6, 1, 1),
502SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
503 7, 1, 0),
504
505SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
506 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
507 0, 63, 0, out_pga_tlv),
508SOC_DOUBLE_R("LINEOUT2 Switch",
509 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
510SOC_DOUBLE_R("LINEOUT2 ZC Switch",
511 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
512SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
513 0, 1, 1),
514
515};
516
517/* add non dapm controls */
518static int wm8900_add_controls(struct snd_soc_codec *codec)
519{
520 int err, i;
521
522 for (i = 0; i < ARRAY_SIZE(wm8900_snd_controls); i++) {
523 err = snd_ctl_add(codec->card,
524 snd_soc_cnew(&wm8900_snd_controls[i],
525 codec, NULL));
526 if (err < 0)
527 return err;
528 }
529
530 return 0;
531}
532
533static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
534SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
535
536static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
537SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
538
539static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
540SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
541SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
542SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
543SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
544SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
545};
546
547static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
548SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
549SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
550SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
551SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
552SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
553};
554
555static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
556SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
557SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
558SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
559SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
560};
561
562static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
563SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
564SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
565SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
566SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
567};
568
569static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
570SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
571SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
572SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
573};
574
575static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
576SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
577SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
578SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
579};
580
581static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
582
583static const struct soc_enum wm8900_lineout2_lp_mux =
584SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
585
586static const struct snd_kcontrol_new wm8900_lineout2_lp =
587SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
588
589static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
590
591/* Externally visible pins */
592SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
593SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
594SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
595SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
596SND_SOC_DAPM_OUTPUT("HP_L"),
597SND_SOC_DAPM_OUTPUT("HP_R"),
598
599SND_SOC_DAPM_INPUT("RINPUT1"),
600SND_SOC_DAPM_INPUT("LINPUT1"),
601SND_SOC_DAPM_INPUT("RINPUT2"),
602SND_SOC_DAPM_INPUT("LINPUT2"),
603SND_SOC_DAPM_INPUT("RINPUT3"),
604SND_SOC_DAPM_INPUT("LINPUT3"),
605SND_SOC_DAPM_INPUT("AUX"),
606
607SND_SOC_DAPM_VMID("VMID"),
608
609/* Input */
610SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
611 wm8900_linpga_controls,
612 ARRAY_SIZE(wm8900_linpga_controls)),
613SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
614 wm8900_rinpga_controls,
615 ARRAY_SIZE(wm8900_rinpga_controls)),
616
617SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
618 wm8900_linmix_controls,
619 ARRAY_SIZE(wm8900_linmix_controls)),
620SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
621 wm8900_rinmix_controls,
622 ARRAY_SIZE(wm8900_rinmix_controls)),
623
624SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
625
626SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
627SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
628
629/* Output */
630SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
631SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
632
633SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
634 wm8900_hp_event,
635 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
636 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
637
638SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
639SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
640
641SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
642SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
643SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
644
645SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
646 wm8900_loutmix_controls,
647 ARRAY_SIZE(wm8900_loutmix_controls)),
648SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
649 wm8900_routmix_controls,
650 ARRAY_SIZE(wm8900_routmix_controls)),
651};
652
653/* Target, Path, Source */
654static const struct snd_soc_dapm_route audio_map[] = {
655/* Inputs */
656{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
657{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
658{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
659
660{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
661{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
662{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
663
664{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
665{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
666{"Left Input Mixer", "AUX Switch", "AUX"},
667{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
668
669{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
670{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
671{"Right Input Mixer", "AUX Switch", "AUX"},
672{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
673
674{"ADCL", NULL, "Left Input Mixer"},
675{"ADCR", NULL, "Right Input Mixer"},
676
677/* Outputs */
678{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
679{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
680{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
681{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
682
683{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
684{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
685{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
686{"LINEOUT2L", NULL, "LINEOUT2 LP"},
687
688{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
689{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
690{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
691{"LINEOUT2R", NULL, "LINEOUT2 LP"},
692
693{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
694{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
695{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
696{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
697{"Left Output Mixer", "DACL Switch", "DACL"},
698
699{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
700{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
701{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
702{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
703{"Right Output Mixer", "DACR Switch", "DACR"},
704
705/* Note that the headphone output stage needs to be connected
706 * externally to LINEOUT2 via DC blocking capacitors. Other
707 * configurations are not supported.
708 *
709 * Note also that left and right headphone paths are treated as a
710 * mono path.
711 */
712{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
713{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
714{"HP_L", NULL, "Headphone Amplifier"},
715{"HP_R", NULL, "Headphone Amplifier"},
716};
717
718static int wm8900_add_widgets(struct snd_soc_codec *codec)
719{
720 snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets,
721 ARRAY_SIZE(wm8900_dapm_widgets));
722
723 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
724
725 snd_soc_dapm_new_widgets(codec);
726
727 return 0;
728}
729
730static int wm8900_hw_params(struct snd_pcm_substream *substream,
731 struct snd_pcm_hw_params *params)
732{
733 struct snd_soc_pcm_runtime *rtd = substream->private_data;
734 struct snd_soc_device *socdev = rtd->socdev;
735 struct snd_soc_codec *codec = socdev->codec;
736 u16 reg;
737
738 reg = wm8900_read(codec, WM8900_REG_AUDIO1) & ~0x60;
739
740 switch (params_format(params)) {
741 case SNDRV_PCM_FORMAT_S16_LE:
742 break;
743 case SNDRV_PCM_FORMAT_S20_3LE:
744 reg |= 0x20;
745 break;
746 case SNDRV_PCM_FORMAT_S24_LE:
747 reg |= 0x40;
748 break;
749 case SNDRV_PCM_FORMAT_S32_LE:
750 reg |= 0x60;
751 break;
752 default:
753 return -EINVAL;
754 }
755
756 wm8900_write(codec, WM8900_REG_AUDIO1, reg);
757
758 return 0;
759}
760
761/* FLL divisors */
762struct _fll_div {
763 u16 fll_ratio;
764 u16 fllclk_div;
765 u16 fll_slow_lock_ref;
766 u16 n;
767 u16 k;
768};
769
770/* The size in bits of the FLL divide multiplied by 10
771 * to allow rounding later */
772#define FIXED_FLL_SIZE ((1 << 16) * 10)
773
774static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
775 unsigned int Fout)
776{
777 u64 Kpart;
778 unsigned int K, Ndiv, Nmod, target;
779 unsigned int div;
780
781 BUG_ON(!Fout);
782
783 /* The FLL must run at 90-100MHz which is then scaled down to
784 * the output value by FLLCLK_DIV. */
785 target = Fout;
786 div = 1;
787 while (target < 90000000) {
788 div *= 2;
789 target *= 2;
790 }
791
792 if (target > 100000000)
793 printk(KERN_WARNING "wm8900: FLL rate %d out of range, Fref=%d"
794 " Fout=%d\n", target, Fref, Fout);
795 if (div > 32) {
796 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
797 "Fref=%d, Fout=%d, target=%d\n",
798 div, Fref, Fout, target);
799 return -EINVAL;
800 }
801
802 fll_div->fllclk_div = div >> 2;
803
804 if (Fref < 48000)
805 fll_div->fll_slow_lock_ref = 1;
806 else
807 fll_div->fll_slow_lock_ref = 0;
808
809 Ndiv = target / Fref;
810
811 if (Fref < 1000000)
812 fll_div->fll_ratio = 8;
813 else
814 fll_div->fll_ratio = 1;
815
816 fll_div->n = Ndiv / fll_div->fll_ratio;
817 Nmod = (target / fll_div->fll_ratio) % Fref;
818
819 /* Calculate fractional part - scale up so we can round. */
820 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
821
822 do_div(Kpart, Fref);
823
824 K = Kpart & 0xFFFFFFFF;
825
826 if ((K % 10) >= 5)
827 K += 5;
828
829 /* Move down to proper range now rounding is done */
830 fll_div->k = K / 10;
831
832 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
833 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
834
835 return 0;
836}
837
838static int wm8900_set_fll(struct snd_soc_codec *codec,
839 int fll_id, unsigned int freq_in, unsigned int freq_out)
840{
841 struct wm8900_priv *wm8900 = codec->private_data;
842 struct _fll_div fll_div;
843 unsigned int reg;
844
845 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
846 return 0;
847
848 /* The digital side should be disabled during any change. */
849 reg = wm8900_read(codec, WM8900_REG_POWER1);
850 wm8900_write(codec, WM8900_REG_POWER1,
851 reg & (~WM8900_REG_POWER1_FLL_ENA));
852
853 /* Disable the FLL? */
854 if (!freq_in || !freq_out) {
855 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
856 wm8900_write(codec, WM8900_REG_CLOCKING1,
857 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
858
859 reg = wm8900_read(codec, WM8900_REG_FLLCTL1);
860 wm8900_write(codec, WM8900_REG_FLLCTL1,
861 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
862
863 wm8900->fll_in = freq_in;
864 wm8900->fll_out = freq_out;
865
866 return 0;
867 }
868
869 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
870 goto reenable;
871
872 wm8900->fll_in = freq_in;
873 wm8900->fll_out = freq_out;
874
875 /* The osclilator *MUST* be enabled before we enable the
876 * digital circuit. */
877 wm8900_write(codec, WM8900_REG_FLLCTL1,
878 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
879
880 wm8900_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
881 wm8900_write(codec, WM8900_REG_FLLCTL5,
882 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
883
884 if (fll_div.k) {
885 wm8900_write(codec, WM8900_REG_FLLCTL2,
886 (fll_div.k >> 8) | 0x100);
887 wm8900_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
888 } else
889 wm8900_write(codec, WM8900_REG_FLLCTL2, 0);
890
891 if (fll_div.fll_slow_lock_ref)
892 wm8900_write(codec, WM8900_REG_FLLCTL6,
893 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
894 else
895 wm8900_write(codec, WM8900_REG_FLLCTL6, 0);
896
897 reg = wm8900_read(codec, WM8900_REG_POWER1);
898 wm8900_write(codec, WM8900_REG_POWER1,
899 reg | WM8900_REG_POWER1_FLL_ENA);
900
901reenable:
902 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
903 wm8900_write(codec, WM8900_REG_CLOCKING1,
904 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
905
906 return 0;
907}
908
909static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai,
910 int pll_id, unsigned int freq_in, unsigned int freq_out)
911{
912 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
913}
914
915static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
916 int div_id, int div)
917{
918 struct snd_soc_codec *codec = codec_dai->codec;
919 unsigned int reg;
920
921 switch (div_id) {
922 case WM8900_BCLK_DIV:
923 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
924 wm8900_write(codec, WM8900_REG_CLOCKING1,
925 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
926 break;
927 case WM8900_OPCLK_DIV:
928 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
929 wm8900_write(codec, WM8900_REG_CLOCKING1,
930 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
931 break;
932 case WM8900_DAC_LRCLK:
933 reg = wm8900_read(codec, WM8900_REG_AUDIO4);
934 wm8900_write(codec, WM8900_REG_AUDIO4,
935 div | (reg & WM8900_LRC_MASK));
936 break;
937 case WM8900_ADC_LRCLK:
938 reg = wm8900_read(codec, WM8900_REG_AUDIO3);
939 wm8900_write(codec, WM8900_REG_AUDIO3,
940 div | (reg & WM8900_LRC_MASK));
941 break;
942 case WM8900_DAC_CLKDIV:
943 reg = wm8900_read(codec, WM8900_REG_CLOCKING2);
944 wm8900_write(codec, WM8900_REG_CLOCKING2,
945 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
946 break;
947 case WM8900_ADC_CLKDIV:
948 reg = wm8900_read(codec, WM8900_REG_CLOCKING2);
949 wm8900_write(codec, WM8900_REG_CLOCKING2,
950 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
951 break;
952 case WM8900_LRCLK_MODE:
953 reg = wm8900_read(codec, WM8900_REG_DACCTRL);
954 wm8900_write(codec, WM8900_REG_DACCTRL,
955 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
956 break;
957 default:
958 return -EINVAL;
959 }
960
961 return 0;
962}
963
964
965static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
966 unsigned int fmt)
967{
968 struct snd_soc_codec *codec = codec_dai->codec;
969 unsigned int clocking1, aif1, aif3, aif4;
970
971 clocking1 = wm8900_read(codec, WM8900_REG_CLOCKING1);
972 aif1 = wm8900_read(codec, WM8900_REG_AUDIO1);
973 aif3 = wm8900_read(codec, WM8900_REG_AUDIO3);
974 aif4 = wm8900_read(codec, WM8900_REG_AUDIO4);
975
976 /* set master/slave audio interface */
977 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
978 case SND_SOC_DAIFMT_CBS_CFS:
979 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
980 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
981 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
982 break;
983 case SND_SOC_DAIFMT_CBS_CFM:
984 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
985 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
986 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
987 break;
988 case SND_SOC_DAIFMT_CBM_CFM:
989 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
990 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
991 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
992 break;
993 case SND_SOC_DAIFMT_CBM_CFS:
994 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
995 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
996 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
997 break;
998 default:
999 return -EINVAL;
1000 }
1001
1002 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1003 case SND_SOC_DAIFMT_DSP_A:
1004 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
1005 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1006 break;
1007 case SND_SOC_DAIFMT_DSP_B:
1008 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
1009 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1010 break;
1011 case SND_SOC_DAIFMT_I2S:
1012 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
1013 aif1 |= 0x10;
1014 break;
1015 case SND_SOC_DAIFMT_RIGHT_J:
1016 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
1017 break;
1018 case SND_SOC_DAIFMT_LEFT_J:
1019 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
1020 aif1 |= 0x8;
1021 break;
1022 default:
1023 return -EINVAL;
1024 }
1025
1026 /* Clock inversion */
1027 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1028 case SND_SOC_DAIFMT_DSP_A:
1029 case SND_SOC_DAIFMT_DSP_B:
1030 /* frame inversion not valid for DSP modes */
1031 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1032 case SND_SOC_DAIFMT_NB_NF:
1033 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1034 break;
1035 case SND_SOC_DAIFMT_IB_NF:
1036 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1037 break;
1038 default:
1039 return -EINVAL;
1040 }
1041 break;
1042 case SND_SOC_DAIFMT_I2S:
1043 case SND_SOC_DAIFMT_RIGHT_J:
1044 case SND_SOC_DAIFMT_LEFT_J:
1045 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1046 case SND_SOC_DAIFMT_NB_NF:
1047 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1048 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1049 break;
1050 case SND_SOC_DAIFMT_IB_IF:
1051 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1052 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1053 break;
1054 case SND_SOC_DAIFMT_IB_NF:
1055 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1056 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1057 break;
1058 case SND_SOC_DAIFMT_NB_IF:
1059 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1060 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1061 break;
1062 default:
1063 return -EINVAL;
1064 }
1065 break;
1066 default:
1067 return -EINVAL;
1068 }
1069
1070 wm8900_write(codec, WM8900_REG_CLOCKING1, clocking1);
1071 wm8900_write(codec, WM8900_REG_AUDIO1, aif1);
1072 wm8900_write(codec, WM8900_REG_AUDIO3, aif3);
1073 wm8900_write(codec, WM8900_REG_AUDIO4, aif4);
1074
1075 return 0;
1076}
1077
1078static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1079{
1080 struct snd_soc_codec *codec = codec_dai->codec;
1081 u16 reg;
1082
1083 reg = wm8900_read(codec, WM8900_REG_DACCTRL);
1084
1085 if (mute)
1086 reg |= WM8900_REG_DACCTRL_MUTE;
1087 else
1088 reg &= ~WM8900_REG_DACCTRL_MUTE;
1089
1090 wm8900_write(codec, WM8900_REG_DACCTRL, reg);
1091
1092 return 0;
1093}
1094
1095#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1096 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1097 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1098
1099#define WM8900_PCM_FORMATS \
1100 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1101 SNDRV_PCM_FORMAT_S24_LE)
1102
1103struct snd_soc_dai wm8900_dai = {
1104 .name = "WM8900 HiFi",
1105 .playback = {
1106 .stream_name = "HiFi Playback",
1107 .channels_min = 1,
1108 .channels_max = 2,
1109 .rates = WM8900_RATES,
1110 .formats = WM8900_PCM_FORMATS,
1111 },
1112 .capture = {
1113 .stream_name = "HiFi Capture",
1114 .channels_min = 1,
1115 .channels_max = 2,
1116 .rates = WM8900_RATES,
1117 .formats = WM8900_PCM_FORMATS,
1118 },
1119 .ops = {
1120 .hw_params = wm8900_hw_params,
1121 },
1122 .dai_ops = {
1123 .set_clkdiv = wm8900_set_dai_clkdiv,
1124 .set_pll = wm8900_set_dai_pll,
1125 .set_fmt = wm8900_set_dai_fmt,
1126 .digital_mute = wm8900_digital_mute,
1127 },
1128};
1129EXPORT_SYMBOL_GPL(wm8900_dai);
1130
1131static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1132 enum snd_soc_bias_level level)
1133{
1134 u16 reg;
1135
1136 switch (level) {
1137 case SND_SOC_BIAS_ON:
1138 /* Enable thermal shutdown */
1139 reg = wm8900_read(codec, WM8900_REG_GPIO);
1140 wm8900_write(codec, WM8900_REG_GPIO,
1141 reg | WM8900_REG_GPIO_TEMP_ENA);
1142 reg = wm8900_read(codec, WM8900_REG_ADDCTL);
1143 wm8900_write(codec, WM8900_REG_ADDCTL,
1144 reg | WM8900_REG_ADDCTL_TEMP_SD);
1145 break;
1146
1147 case SND_SOC_BIAS_PREPARE:
1148 break;
1149
1150 case SND_SOC_BIAS_STANDBY:
1151 /* Charge capacitors if initial power up */
1152 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1153 /* STARTUP_BIAS_ENA on */
1154 wm8900_write(codec, WM8900_REG_POWER1,
1155 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1156
1157 /* Startup bias mode */
1158 wm8900_write(codec, WM8900_REG_ADDCTL,
1159 WM8900_REG_ADDCTL_BIAS_SRC |
1160 WM8900_REG_ADDCTL_VMID_SOFTST);
1161
1162 /* VMID 2x50k */
1163 wm8900_write(codec, WM8900_REG_POWER1,
1164 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1165
1166 /* Allow capacitors to charge */
1167 schedule_timeout_interruptible(msecs_to_jiffies(400));
1168
1169 /* Enable bias */
1170 wm8900_write(codec, WM8900_REG_POWER1,
1171 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1172 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1173
1174 wm8900_write(codec, WM8900_REG_ADDCTL, 0);
1175
1176 wm8900_write(codec, WM8900_REG_POWER1,
1177 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1178 }
1179
1180 reg = wm8900_read(codec, WM8900_REG_POWER1);
1181 wm8900_write(codec, WM8900_REG_POWER1,
1182 (reg & WM8900_REG_POWER1_FLL_ENA) |
1183 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1184 wm8900_write(codec, WM8900_REG_POWER2,
1185 WM8900_REG_POWER2_SYSCLK_ENA);
1186 wm8900_write(codec, WM8900_REG_POWER3, 0);
1187 break;
1188
1189 case SND_SOC_BIAS_OFF:
1190 /* Startup bias enable */
1191 reg = wm8900_read(codec, WM8900_REG_POWER1);
1192 wm8900_write(codec, WM8900_REG_POWER1,
1193 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1194 wm8900_write(codec, WM8900_REG_ADDCTL,
1195 WM8900_REG_ADDCTL_BIAS_SRC |
1196 WM8900_REG_ADDCTL_VMID_SOFTST);
1197
1198 /* Discharge caps */
1199 wm8900_write(codec, WM8900_REG_POWER1,
1200 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1201 schedule_timeout_interruptible(msecs_to_jiffies(500));
1202
1203 /* Remove clamp */
1204 wm8900_write(codec, WM8900_REG_HPCTL1, 0);
1205
1206 /* Power down */
1207 wm8900_write(codec, WM8900_REG_ADDCTL, 0);
1208 wm8900_write(codec, WM8900_REG_POWER1, 0);
1209 wm8900_write(codec, WM8900_REG_POWER2, 0);
1210 wm8900_write(codec, WM8900_REG_POWER3, 0);
1211
1212 /* Need to let things settle before stopping the clock
1213 * to ensure that restart works, see "Stopping the
1214 * master clock" in the datasheet. */
1215 schedule_timeout_interruptible(msecs_to_jiffies(1));
1216 wm8900_write(codec, WM8900_REG_POWER2,
1217 WM8900_REG_POWER2_SYSCLK_ENA);
1218 break;
1219 }
1220 codec->bias_level = level;
1221 return 0;
1222}
1223
1224static int wm8900_suspend(struct platform_device *pdev, pm_message_t state)
1225{
1226 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1227 struct snd_soc_codec *codec = socdev->codec;
1228 struct wm8900_priv *wm8900 = codec->private_data;
1229 int fll_out = wm8900->fll_out;
1230 int fll_in = wm8900->fll_in;
1231 int ret;
1232
1233 /* Stop the FLL in an orderly fashion */
1234 ret = wm8900_set_fll(codec, 0, 0, 0);
1235 if (ret != 0) {
1236 dev_err(&pdev->dev, "Failed to stop FLL\n");
1237 return ret;
1238 }
1239
1240 wm8900->fll_out = fll_out;
1241 wm8900->fll_in = fll_in;
1242
1243 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1244
1245 return 0;
1246}
1247
1248static int wm8900_resume(struct platform_device *pdev)
1249{
1250 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1251 struct snd_soc_codec *codec = socdev->codec;
1252 struct wm8900_priv *wm8900 = codec->private_data;
1253 u16 *cache;
1254 int i, ret;
1255
1256 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1257 GFP_KERNEL);
1258
1259 wm8900_reset(codec);
1260 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1261
1262 /* Restart the FLL? */
1263 if (wm8900->fll_out) {
1264 int fll_out = wm8900->fll_out;
1265 int fll_in = wm8900->fll_in;
1266
1267 wm8900->fll_in = 0;
1268 wm8900->fll_out = 0;
1269
1270 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1271 if (ret != 0) {
1272 dev_err(&pdev->dev, "Failed to restart FLL\n");
1273 return ret;
1274 }
1275 }
1276
1277 if (cache) {
1278 for (i = 0; i < WM8900_MAXREG; i++)
1279 wm8900_write(codec, i, cache[i]);
1280 kfree(cache);
1281 } else
1282 dev_err(&pdev->dev, "Unable to allocate register cache\n");
1283
1284 return 0;
1285}
1286
1287/*
1288 * initialise the WM8900 driver
1289 * register the mixer and dsp interfaces with the kernel
1290 */
1291static int wm8900_init(struct snd_soc_device *socdev)
1292{
1293 struct snd_soc_codec *codec = socdev->codec;
1294 int ret = 0;
1295 unsigned int reg;
1296 struct i2c_client *i2c_client = socdev->codec->control_data;
1297
1298 codec->name = "WM8900";
1299 codec->owner = THIS_MODULE;
1300 codec->read = wm8900_read;
1301 codec->write = wm8900_write;
1302 codec->dai = &wm8900_dai;
1303 codec->num_dai = 1;
1304 codec->reg_cache_size = WM8900_MAXREG;
1305 codec->reg_cache = kmemdup(wm8900_reg_defaults,
1306 sizeof(wm8900_reg_defaults), GFP_KERNEL);
1307
1308 if (codec->reg_cache == NULL)
1309 return -ENOMEM;
1310
1311 reg = wm8900_read(codec, WM8900_REG_ID);
1312 if (reg != 0x8900) {
1313 dev_err(&i2c_client->dev, "Device is not a WM8900 - ID %x\n",
1314 reg);
1315 return -ENODEV;
1316 }
1317
1318 codec->private_data = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1319 if (codec->private_data == NULL) {
1320 ret = -ENOMEM;
1321 goto priv_err;
1322 }
1323
1324 /* Read back from the chip */
1325 reg = wm8900_chip_read(codec, WM8900_REG_POWER1);
1326 reg = (reg >> 12) & 0xf;
1327 dev_info(&i2c_client->dev, "WM8900 revision %d\n", reg);
1328
1329 wm8900_reset(codec);
1330
1331 /* Latch the volume update bits */
1332 wm8900_write(codec, WM8900_REG_LINVOL,
1333 wm8900_read(codec, WM8900_REG_LINVOL) | 0x100);
1334 wm8900_write(codec, WM8900_REG_RINVOL,
1335 wm8900_read(codec, WM8900_REG_RINVOL) | 0x100);
1336 wm8900_write(codec, WM8900_REG_LOUT1CTL,
1337 wm8900_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1338 wm8900_write(codec, WM8900_REG_ROUT1CTL,
1339 wm8900_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1340 wm8900_write(codec, WM8900_REG_LOUT2CTL,
1341 wm8900_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1342 wm8900_write(codec, WM8900_REG_ROUT2CTL,
1343 wm8900_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1344 wm8900_write(codec, WM8900_REG_LDAC_DV,
1345 wm8900_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1346 wm8900_write(codec, WM8900_REG_RDAC_DV,
1347 wm8900_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1348 wm8900_write(codec, WM8900_REG_LADC_DV,
1349 wm8900_read(codec, WM8900_REG_LADC_DV) | 0x100);
1350 wm8900_write(codec, WM8900_REG_RADC_DV,
1351 wm8900_read(codec, WM8900_REG_RADC_DV) | 0x100);
1352
1353 /* Set the DAC and mixer output bias */
1354 wm8900_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1355
1356 /* Register pcms */
1357 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1358 if (ret < 0) {
1359 dev_err(&i2c_client->dev, "Failed to register new PCMs\n");
1360 goto pcm_err;
1361 }
1362
1363 /* Turn the chip on */
1364 codec->bias_level = SND_SOC_BIAS_OFF;
1365 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1366
1367 wm8900_add_controls(codec);
1368 wm8900_add_widgets(codec);
1369
1370 ret = snd_soc_register_card(socdev);
1371 if (ret < 0) {
1372 dev_err(&i2c_client->dev, "Failed to register card\n");
1373 goto card_err;
1374 }
1375 return ret;
1376
1377card_err:
1378 snd_soc_free_pcms(socdev);
1379 snd_soc_dapm_free(socdev);
1380pcm_err:
1381 kfree(codec->reg_cache);
1382priv_err:
1383 kfree(codec->private_data);
1384 return ret;
1385}
1386
1387static struct snd_soc_device *wm8900_socdev;
1388
1389#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1390
1391static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
1392
1393/* Magic definition of all other variables and things */
1394I2C_CLIENT_INSMOD;
1395
1396static struct i2c_driver wm8900_i2c_driver;
1397static struct i2c_client client_template;
1398
1399/* If the i2c layer weren't so broken, we could pass this kind of data
1400 around */
1401static int wm8900_codec_probe(struct i2c_adapter *adap, int addr, int kind)
1402{
1403 struct snd_soc_device *socdev = wm8900_socdev;
1404 struct wm8900_setup_data *setup = socdev->codec_data;
1405 struct snd_soc_codec *codec = socdev->codec;
1406 struct i2c_client *i2c;
1407 int ret;
1408
1409 if (addr != setup->i2c_address)
1410 return -ENODEV;
1411
1412 dev_err(&adap->dev, "Probe on %x\n", addr);
1413
1414 client_template.adapter = adap;
1415 client_template.addr = addr;
1416
1417 i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
1418 if (i2c == NULL) {
1419 kfree(codec);
1420 return -ENOMEM;
1421 }
1422 i2c_set_clientdata(i2c, codec);
1423 codec->control_data = i2c;
1424
1425 ret = i2c_attach_client(i2c);
1426 if (ret < 0) {
1427 dev_err(&adap->dev,
1428 "failed to attach codec at addr %x\n", addr);
1429 goto err;
1430 }
1431
1432 ret = wm8900_init(socdev);
1433 if (ret < 0) {
1434 dev_err(&adap->dev, "failed to initialise WM8900\n");
1435 goto err;
1436 }
1437 return ret;
1438
1439err:
1440 kfree(codec);
1441 kfree(i2c);
1442 return ret;
1443}
1444
1445static int wm8900_i2c_detach(struct i2c_client *client)
1446{
1447 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1448 i2c_detach_client(client);
1449 kfree(codec->reg_cache);
1450 kfree(client);
1451 return 0;
1452}
1453
1454static int wm8900_i2c_attach(struct i2c_adapter *adap)
1455{
1456 return i2c_probe(adap, &addr_data, wm8900_codec_probe);
1457}
1458
1459/* corgi i2c codec control layer */
1460static struct i2c_driver wm8900_i2c_driver = {
1461 .driver = {
1462 .name = "WM8900 I2C codec",
1463 .owner = THIS_MODULE,
1464 },
1465 .attach_adapter = wm8900_i2c_attach,
1466 .detach_client = wm8900_i2c_detach,
1467 .command = NULL,
1468};
1469
1470static struct i2c_client client_template = {
1471 .name = "WM8900",
1472 .driver = &wm8900_i2c_driver,
1473};
1474#endif
1475
1476static int wm8900_probe(struct platform_device *pdev)
1477{
1478 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1479 struct wm8900_setup_data *setup;
1480 struct snd_soc_codec *codec;
1481 int ret = 0;
1482
1483 dev_info(&pdev->dev, "WM8900 Audio Codec\n");
1484
1485 setup = socdev->codec_data;
1486 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1487 if (codec == NULL)
1488 return -ENOMEM;
1489
1490 mutex_init(&codec->mutex);
1491 INIT_LIST_HEAD(&codec->dapm_widgets);
1492 INIT_LIST_HEAD(&codec->dapm_paths);
1493
1494 socdev->codec = codec;
1495
1496 codec->set_bias_level = wm8900_set_bias_level;
1497
1498 wm8900_socdev = socdev;
1499#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1500 if (setup->i2c_address) {
1501 normal_i2c[0] = setup->i2c_address;
1502 codec->hw_write = (hw_write_t)i2c_master_send;
1503 ret = i2c_add_driver(&wm8900_i2c_driver);
1504 if (ret != 0)
1505 printk(KERN_ERR "can't add i2c driver");
1506 }
1507#else
1508#error Non-I2C interfaces not yet supported
1509#endif
1510 return ret;
1511}
1512
1513/* power down chip */
1514static int wm8900_remove(struct platform_device *pdev)
1515{
1516 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1517 struct snd_soc_codec *codec = socdev->codec;
1518
1519 if (codec->control_data)
1520 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1521
1522 snd_soc_free_pcms(socdev);
1523 snd_soc_dapm_free(socdev);
1524#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1525 i2c_del_driver(&wm8900_i2c_driver);
1526#endif
1527 kfree(codec);
1528
1529 return 0;
1530}
1531
1532struct snd_soc_codec_device soc_codec_dev_wm8900 = {
1533 .probe = wm8900_probe,
1534 .remove = wm8900_remove,
1535 .suspend = wm8900_suspend,
1536 .resume = wm8900_resume,
1537};
1538EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900);
1539
1540MODULE_DESCRIPTION("ASoC WM8900 driver");
1541MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1542MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 05:03:35 -0500