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authorTakashi Iwai <tiwai@suse.de>2009-06-10 01:26:18 -0400
committerTakashi Iwai <tiwai@suse.de>2009-06-10 01:26:18 -0400
commitba252af8d60f543a2a2c03f5574f64007ae9c2f3 (patch)
treea37b2723f0c4ea10447600f321f4df261e45bde6 /sound/soc/codecs/wm8580.c
parent07a2039b8eb0af4ff464efd3dfd95de5c02648c6 (diff)
parent74b8f955a73d20b1e22403fd1ef85834fbf38d98 (diff)
Merge branch 'topic/asoc' into for-linus
* topic/asoc: (135 commits) ASoC: Apostrophe patrol ASoC: codec tlv320aic23 fix bogus divide by 0 message ASoC: fix NULL pointer dereference in soc_suspend() ASoC: Fix build error in twl4030.c ASoC: SSM2602: assign last substream to the master when shutting down ASoC: Blackfin: document how anomaly 05000250 is handled ASoC: Blackfin: set the transfer size according the ac97_frame size ASoC: SSM2602: remove unsupported sample rates ASoC: TWL4030: Check the interface format for 4 channel mode ASoC: TWL4030: Use reg_cache in twl4030_init_chip ASoC: Initialise dev for the dummy S/PDIF DAI ASoC: Add dummy S/PDIF codec support ASoC: correct print specifiers for unsigneds ASoC: Modify mpc5200 AC97 driver to use V9 of spin_event_timeout() ASoC: Switch FSL SSI DAI over to symmetric_rates ASoC: Mark MPC5200 AC97 as BROKEN until PowerPC merge issues are resolved ASoC: Fabric bindings for STAC9766 on the Efika ASoC: Support for AC97 on Phytec pmc030 base board. ASoC: AC97 driver for mpc5200 ASoC: Main rewite of the mpc5200 audio DMA code ...
Diffstat (limited to 'sound/soc/codecs/wm8580.c')
-rw-r--r--sound/soc/codecs/wm8580.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index 9f6be3d31ac0..86c4b24db817 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -415,7 +415,7 @@ static int pll_factors(struct _pll_div *pll_div, unsigned int target,
415 unsigned int K, Ndiv, Nmod; 415 unsigned int K, Ndiv, Nmod;
416 int i; 416 int i;
417 417
418 pr_debug("wm8580: PLL %dHz->%dHz\n", source, target); 418 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
419 419
420 /* Scale the output frequency up; the PLL should run in the 420 /* Scale the output frequency up; the PLL should run in the
421 * region of 90-100MHz. 421 * region of 90-100MHz.
@@ -447,7 +447,7 @@ static int pll_factors(struct _pll_div *pll_div, unsigned int target,
447 447
448 if ((Ndiv < 5) || (Ndiv > 13)) { 448 if ((Ndiv < 5) || (Ndiv > 13)) {
449 printk(KERN_ERR 449 printk(KERN_ERR
450 "WM8580 N=%d outside supported range\n", Ndiv); 450 "WM8580 N=%u outside supported range\n", Ndiv);
451 return -EINVAL; 451 return -EINVAL;
452 } 452 }
453 453