diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-08-13 15:08:55 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-08-15 09:52:53 -0400 |
commit | 6bfb6aa91f61f2a7c526a6353c8c50676ca528da (patch) | |
tree | cca002bdb1cd88f743772417a0c9c9aec25beb9b /sound/soc/codecs/wm8580.c | |
parent | dacfe9f277f765dcebc7b34588d3af4a687ea2f3 (diff) |
ASoC: Automatically manage WM8580 DAC OSR
The DAC OSR should be selected based on the sample clock ratio.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'sound/soc/codecs/wm8580.c')
-rw-r--r-- | sound/soc/codecs/wm8580.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index 834cf141ea2f..d66db4bf11e4 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c | |||
@@ -94,6 +94,8 @@ | |||
94 | 94 | ||
95 | #define WM8580_MAX_REGISTER 0x35 | 95 | #define WM8580_MAX_REGISTER 0x35 |
96 | 96 | ||
97 | #define WM8580_DACOSR 0x40 | ||
98 | |||
97 | /* PLLB4 (register 7h) */ | 99 | /* PLLB4 (register 7h) */ |
98 | #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60 | 100 | #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60 |
99 | #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20 | 101 | #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20 |
@@ -481,7 +483,7 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream, | |||
481 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); | 483 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
482 | u16 paifa = 0; | 484 | u16 paifa = 0; |
483 | u16 paifb = 0; | 485 | u16 paifb = 0; |
484 | int i, ratio; | 486 | int i, ratio, osr; |
485 | 487 | ||
486 | /* bit size */ | 488 | /* bit size */ |
487 | switch (params_format(params)) { | 489 | switch (params_format(params)) { |
@@ -518,6 +520,22 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream, | |||
518 | dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n", | 520 | dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n", |
519 | wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]); | 521 | wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]); |
520 | 522 | ||
523 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | ||
524 | switch (ratio) { | ||
525 | case 128: | ||
526 | case 192: | ||
527 | osr = WM8580_DACOSR; | ||
528 | dev_dbg(codec->dev, "Selecting 64x OSR\n"); | ||
529 | break; | ||
530 | default: | ||
531 | osr = 0; | ||
532 | dev_dbg(codec->dev, "Selecting 128x OSR\n"); | ||
533 | break; | ||
534 | } | ||
535 | |||
536 | snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr); | ||
537 | } | ||
538 | |||
521 | snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id, | 539 | snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id, |
522 | WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK, | 540 | WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK, |
523 | paifa); | 541 | paifa); |