ASoC: TWL4030: Add analog loopback support

This patch adds the analog loopback/bypass support for twl4030 codec.

Details for the implementation:
It seams that the analog loopback needs the DAC powered on on the channel,
where the loopback is selected. The switch for the DACs has been moved from
the DAPM_DAC to the "Analog XX Playback Mixer". In this way the DAC will be
powered while the audio playback is used or/and the loopback is enabled for
the channel.

The twl4030 codec powering has been reworked. Now the codec will be powered as
long as it does not receives the SND_SOC_BIAS_OFF event. The exceptions are
when the given change in the registers needs the codec power down/up cycle in
order to take effect. Otherwise the codec is on.

When the codec enters to STANDBY state and none of the loopback paths are
enabled, than the amplifiers, which are no in the DAPM path are forced to turn
off and the PLL is disabled. When playback/capture starts the disabled gains
are restored and the PLL is enabled.

When one of the loopback enabled in STANDBY mode, the disabled gains are
restored and the PLL is enabled also.

In short: the codec always goes to the lowest power state based on the
bias_level and the bypass_state.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

1 files changed, 15 insertions, 0 deletions

diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h
index 442e5a828617..33dbb144dad1 100644
--- a/sound/soc/codecs/twl4030.h
+++ b/sound/soc/codecs/twl4030.h
@@ -170,6 +170,9 @@
 #define TWL4030_CLK256FS_EN             0x02
 #define TWL4030_AIF_EN                  0x01
 
+/* EAR_CTL (0x21) */
+#define TWL4030_EAR_GAIN                0x30
+
 /* HS_GAIN_SET (0x23) Fields */
 
 #define TWL4030_HSR_GAIN                0x0C
@@ -198,6 +201,18 @@
 #define TWL4030_RAMP_DELAY_2581MS       0x1C
 #define TWL4030_RAMP_EN                 0x02
 
+/* PREDL_CTL (0x25) */
+#define TWL4030_PREDL_GAIN              0x30
+
+/* PREDR_CTL (0x26) */
+#define TWL4030_PREDR_GAIN              0x30
+
+/* PRECKL_CTL (0x27) */
+#define TWL4030_PRECKL_GAIN             0x30
+
+/* PRECKR_CTL (0x28) */
+#define TWL4030_PRECKR_GAIN             0x30
+
 /* HFL_CTL (0x29, 0x2A) Fields */
 #define TWL4030_HF_CTL_HB_EN            0x04
 #define TWL4030_HF_CTL_LOOP_EN          0x08