diff options
author | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
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committer | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
commit | c71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch) | |
tree | ecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /sound/soc/codecs/tlv320aic3x.h | |
parent | ea53c912f8a86a8567697115b6a0d8152beee5c8 (diff) | |
parent | 6a00f206debf8a5c8899055726ad127dbeeed098 (diff) |
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts:
litmus/sched_cedf.c
Diffstat (limited to 'sound/soc/codecs/tlv320aic3x.h')
-rw-r--r-- | sound/soc/codecs/tlv320aic3x.h | 100 |
1 files changed, 35 insertions, 65 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h index 9af1c886213c..06a19784b162 100644 --- a/sound/soc/codecs/tlv320aic3x.h +++ b/sound/soc/codecs/tlv320aic3x.h | |||
@@ -81,50 +81,63 @@ | |||
81 | /* DAC Digital control registers */ | 81 | /* DAC Digital control registers */ |
82 | #define LDAC_VOL 43 | 82 | #define LDAC_VOL 43 |
83 | #define RDAC_VOL 44 | 83 | #define RDAC_VOL 44 |
84 | /* High Power Output control registers */ | 84 | /* Left High Power Output control registers */ |
85 | #define LINE2L_2_HPLOUT_VOL 45 | 85 | #define LINE2L_2_HPLOUT_VOL 45 |
86 | #define LINE2R_2_HPROUT_VOL 62 | ||
87 | #define PGAL_2_HPLOUT_VOL 46 | 86 | #define PGAL_2_HPLOUT_VOL 46 |
88 | #define PGAL_2_HPROUT_VOL 60 | ||
89 | #define PGAR_2_HPLOUT_VOL 49 | ||
90 | #define PGAR_2_HPROUT_VOL 63 | ||
91 | #define DACL1_2_HPLOUT_VOL 47 | 87 | #define DACL1_2_HPLOUT_VOL 47 |
92 | #define DACR1_2_HPROUT_VOL 64 | 88 | #define LINE2R_2_HPLOUT_VOL 48 |
89 | #define PGAR_2_HPLOUT_VOL 49 | ||
90 | #define DACR1_2_HPLOUT_VOL 50 | ||
93 | #define HPLOUT_CTRL 51 | 91 | #define HPLOUT_CTRL 51 |
94 | #define HPROUT_CTRL 65 | 92 | /* Left High Power COM control registers */ |
95 | /* High Power COM control registers */ | ||
96 | #define LINE2L_2_HPLCOM_VOL 52 | 93 | #define LINE2L_2_HPLCOM_VOL 52 |
97 | #define LINE2R_2_HPRCOM_VOL 69 | ||
98 | #define PGAL_2_HPLCOM_VOL 53 | 94 | #define PGAL_2_HPLCOM_VOL 53 |
95 | #define DACL1_2_HPLCOM_VOL 54 | ||
96 | #define LINE2R_2_HPLCOM_VOL 55 | ||
99 | #define PGAR_2_HPLCOM_VOL 56 | 97 | #define PGAR_2_HPLCOM_VOL 56 |
98 | #define DACR1_2_HPLCOM_VOL 57 | ||
99 | #define HPLCOM_CTRL 58 | ||
100 | /* Right High Power Output control registers */ | ||
101 | #define LINE2L_2_HPROUT_VOL 59 | ||
102 | #define PGAL_2_HPROUT_VOL 60 | ||
103 | #define DACL1_2_HPROUT_VOL 61 | ||
104 | #define LINE2R_2_HPROUT_VOL 62 | ||
105 | #define PGAR_2_HPROUT_VOL 63 | ||
106 | #define DACR1_2_HPROUT_VOL 64 | ||
107 | #define HPROUT_CTRL 65 | ||
108 | /* Right High Power COM control registers */ | ||
109 | #define LINE2L_2_HPRCOM_VOL 66 | ||
100 | #define PGAL_2_HPRCOM_VOL 67 | 110 | #define PGAL_2_HPRCOM_VOL 67 |
111 | #define DACL1_2_HPRCOM_VOL 68 | ||
112 | #define LINE2R_2_HPRCOM_VOL 69 | ||
101 | #define PGAR_2_HPRCOM_VOL 70 | 113 | #define PGAR_2_HPRCOM_VOL 70 |
102 | #define DACL1_2_HPLCOM_VOL 54 | ||
103 | #define DACR1_2_HPRCOM_VOL 71 | 114 | #define DACR1_2_HPRCOM_VOL 71 |
104 | #define HPLCOM_CTRL 58 | ||
105 | #define HPRCOM_CTRL 72 | 115 | #define HPRCOM_CTRL 72 |
106 | /* Mono Line Output Plus/Minus control registers */ | 116 | /* Mono Line Output Plus/Minus control registers */ |
107 | #define LINE2L_2_MONOLOPM_VOL 73 | 117 | #define LINE2L_2_MONOLOPM_VOL 73 |
108 | #define LINE2R_2_MONOLOPM_VOL 76 | ||
109 | #define PGAL_2_MONOLOPM_VOL 74 | 118 | #define PGAL_2_MONOLOPM_VOL 74 |
110 | #define PGAR_2_MONOLOPM_VOL 77 | ||
111 | #define DACL1_2_MONOLOPM_VOL 75 | 119 | #define DACL1_2_MONOLOPM_VOL 75 |
120 | #define LINE2R_2_MONOLOPM_VOL 76 | ||
121 | #define PGAR_2_MONOLOPM_VOL 77 | ||
112 | #define DACR1_2_MONOLOPM_VOL 78 | 122 | #define DACR1_2_MONOLOPM_VOL 78 |
113 | #define MONOLOPM_CTRL 79 | 123 | #define MONOLOPM_CTRL 79 |
114 | /* Line Output Plus/Minus control registers */ | 124 | /* Class-D speaker driver on tlv320aic3007 */ |
125 | #define CLASSD_CTRL 73 | ||
126 | /* Left Line Output Plus/Minus control registers */ | ||
115 | #define LINE2L_2_LLOPM_VOL 80 | 127 | #define LINE2L_2_LLOPM_VOL 80 |
116 | #define LINE2L_2_RLOPM_VOL 87 | ||
117 | #define LINE2R_2_LLOPM_VOL 83 | ||
118 | #define LINE2R_2_RLOPM_VOL 90 | ||
119 | #define PGAL_2_LLOPM_VOL 81 | 128 | #define PGAL_2_LLOPM_VOL 81 |
120 | #define PGAL_2_RLOPM_VOL 88 | ||
121 | #define PGAR_2_LLOPM_VOL 84 | ||
122 | #define PGAR_2_RLOPM_VOL 91 | ||
123 | #define DACL1_2_LLOPM_VOL 82 | 129 | #define DACL1_2_LLOPM_VOL 82 |
124 | #define DACL1_2_RLOPM_VOL 89 | 130 | #define LINE2R_2_LLOPM_VOL 83 |
125 | #define DACR1_2_RLOPM_VOL 92 | 131 | #define PGAR_2_LLOPM_VOL 84 |
126 | #define DACR1_2_LLOPM_VOL 85 | 132 | #define DACR1_2_LLOPM_VOL 85 |
127 | #define LLOPM_CTRL 86 | 133 | #define LLOPM_CTRL 86 |
134 | /* Right Line Output Plus/Minus control registers */ | ||
135 | #define LINE2L_2_RLOPM_VOL 87 | ||
136 | #define PGAL_2_RLOPM_VOL 88 | ||
137 | #define DACL1_2_RLOPM_VOL 89 | ||
138 | #define LINE2R_2_RLOPM_VOL 90 | ||
139 | #define PGAR_2_RLOPM_VOL 91 | ||
140 | #define DACR1_2_RLOPM_VOL 92 | ||
128 | #define RLOPM_CTRL 93 | 141 | #define RLOPM_CTRL 93 |
129 | /* GPIO/IRQ registers */ | 142 | /* GPIO/IRQ registers */ |
130 | #define AIC3X_STICKY_IRQ_FLAGS_REG 96 | 143 | #define AIC3X_STICKY_IRQ_FLAGS_REG 96 |
@@ -199,42 +212,6 @@ | |||
199 | /* Default input volume */ | 212 | /* Default input volume */ |
200 | #define DEFAULT_GAIN 0x20 | 213 | #define DEFAULT_GAIN 0x20 |
201 | 214 | ||
202 | /* GPIO API */ | ||
203 | enum { | ||
204 | AIC3X_GPIO1_FUNC_DISABLED = 0, | ||
205 | AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1, | ||
206 | AIC3X_GPIO1_FUNC_CLOCK_MUX = 2, | ||
207 | AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3, | ||
208 | AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4, | ||
209 | AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5, | ||
210 | AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6, | ||
211 | AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7, | ||
212 | AIC3X_GPIO1_FUNC_INPUT = 8, | ||
213 | AIC3X_GPIO1_FUNC_OUTPUT = 9, | ||
214 | AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10, | ||
215 | AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11, | ||
216 | AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12, | ||
217 | AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13, | ||
218 | AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14, | ||
219 | AIC3X_GPIO1_FUNC_ALL_IRQ = 16 | ||
220 | }; | ||
221 | |||
222 | enum { | ||
223 | AIC3X_GPIO2_FUNC_DISABLED = 0, | ||
224 | AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2, | ||
225 | AIC3X_GPIO2_FUNC_INPUT = 3, | ||
226 | AIC3X_GPIO2_FUNC_OUTPUT = 4, | ||
227 | AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5, | ||
228 | AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8, | ||
229 | AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9, | ||
230 | AIC3X_GPIO2_FUNC_ALL_IRQ = 10, | ||
231 | AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11, | ||
232 | AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12, | ||
233 | AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13, | ||
234 | AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14, | ||
235 | AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15 | ||
236 | }; | ||
237 | |||
238 | void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state); | 215 | void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state); |
239 | int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio); | 216 | int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio); |
240 | 217 | ||
@@ -281,11 +258,4 @@ void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect, | |||
281 | int aic3x_headset_detected(struct snd_soc_codec *codec); | 258 | int aic3x_headset_detected(struct snd_soc_codec *codec); |
282 | int aic3x_button_pressed(struct snd_soc_codec *codec); | 259 | int aic3x_button_pressed(struct snd_soc_codec *codec); |
283 | 260 | ||
284 | struct aic3x_setup_data { | ||
285 | unsigned int gpio_func[2]; | ||
286 | }; | ||
287 | |||
288 | extern struct snd_soc_dai aic3x_dai; | ||
289 | extern struct snd_soc_codec_device soc_codec_dev_aic3x; | ||
290 | |||
291 | #endif /* _AIC3X_H */ | 261 | #endif /* _AIC3X_H */ |