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authorJarkko Nikula <jhnikula@gmail.com>2010-08-27 09:56:49 -0400
committerLiam Girdwood <lrg@slimlogic.co.uk>2010-08-28 05:57:58 -0400
commitc3b79e05b4d9ab2e7c3ba281261ea87ab5b71a92 (patch)
tree33e5e39f866365eb4cb90faee09ccd32ad35c72d /sound/soc/codecs/tlv320aic3x.h
parentb2eaac203a04362e9ccae7ba36aef0a9f2486547 (diff)
ASoC: tlv320aic3x: Reimplement output mixers
It turned out that the output mixers and their routes were misdefined: They are not mixing output pins to internal signals but opposite. This has worked for direct left-to-left and right-to-right routes since for those there are complete routes. For swapped left-to-right and right-to-left routes this is not working since there are no routes defined between them. Another consequence is that those misdefined mixers are incorrectly routed to several output pins leading unnecessary pin powerings even if there is no route active to them. Fix these by reimplementing the output mixers and routes as they are in hardware. For completeness add also a few missing links between internal signals and outputs. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'sound/soc/codecs/tlv320aic3x.h')
-rw-r--r--sound/soc/codecs/tlv320aic3x.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h
index 20d8cac2637c..06a19784b162 100644
--- a/sound/soc/codecs/tlv320aic3x.h
+++ b/sound/soc/codecs/tlv320aic3x.h
@@ -85,22 +85,30 @@
85#define LINE2L_2_HPLOUT_VOL 45 85#define LINE2L_2_HPLOUT_VOL 45
86#define PGAL_2_HPLOUT_VOL 46 86#define PGAL_2_HPLOUT_VOL 46
87#define DACL1_2_HPLOUT_VOL 47 87#define DACL1_2_HPLOUT_VOL 47
88#define LINE2R_2_HPLOUT_VOL 48
88#define PGAR_2_HPLOUT_VOL 49 89#define PGAR_2_HPLOUT_VOL 49
90#define DACR1_2_HPLOUT_VOL 50
89#define HPLOUT_CTRL 51 91#define HPLOUT_CTRL 51
90/* Left High Power COM control registers */ 92/* Left High Power COM control registers */
91#define LINE2L_2_HPLCOM_VOL 52 93#define LINE2L_2_HPLCOM_VOL 52
92#define PGAL_2_HPLCOM_VOL 53 94#define PGAL_2_HPLCOM_VOL 53
93#define DACL1_2_HPLCOM_VOL 54 95#define DACL1_2_HPLCOM_VOL 54
96#define LINE2R_2_HPLCOM_VOL 55
94#define PGAR_2_HPLCOM_VOL 56 97#define PGAR_2_HPLCOM_VOL 56
98#define DACR1_2_HPLCOM_VOL 57
95#define HPLCOM_CTRL 58 99#define HPLCOM_CTRL 58
96/* Right High Power Output control registers */ 100/* Right High Power Output control registers */
101#define LINE2L_2_HPROUT_VOL 59
97#define PGAL_2_HPROUT_VOL 60 102#define PGAL_2_HPROUT_VOL 60
103#define DACL1_2_HPROUT_VOL 61
98#define LINE2R_2_HPROUT_VOL 62 104#define LINE2R_2_HPROUT_VOL 62
99#define PGAR_2_HPROUT_VOL 63 105#define PGAR_2_HPROUT_VOL 63
100#define DACR1_2_HPROUT_VOL 64 106#define DACR1_2_HPROUT_VOL 64
101#define HPROUT_CTRL 65 107#define HPROUT_CTRL 65
102/* Right High Power COM control registers */ 108/* Right High Power COM control registers */
109#define LINE2L_2_HPRCOM_VOL 66
103#define PGAL_2_HPRCOM_VOL 67 110#define PGAL_2_HPRCOM_VOL 67
111#define DACL1_2_HPRCOM_VOL 68
104#define LINE2R_2_HPRCOM_VOL 69 112#define LINE2R_2_HPRCOM_VOL 69
105#define PGAR_2_HPRCOM_VOL 70 113#define PGAR_2_HPRCOM_VOL 70
106#define DACR1_2_HPRCOM_VOL 71 114#define DACR1_2_HPRCOM_VOL 71