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authorJarkko Nikula <jhnikula@gmail.com>2010-08-27 09:56:48 -0400
committerLiam Girdwood <lrg@slimlogic.co.uk>2010-08-28 05:57:58 -0400
commitb2eaac203a04362e9ccae7ba36aef0a9f2486547 (patch)
tree2d5d85e3870306fced4972ebae5d45b351af9b1b /sound/soc/codecs/tlv320aic3x.h
parentf9bc02974d931cb424cd1979526ce9c208122bd2 (diff)
ASoC: tlv320aic3x: Sort output pin control registers in header file
Each output pin has 7 consecutive control registers in tlv320aic3x register map. First 6 of them control the signal mixing and one is for output level and power control. Sort these registers as they are sorted clearly in hardware, it makes also definitions more readable and easier to pinpoint missing register definitions. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'sound/soc/codecs/tlv320aic3x.h')
-rw-r--r--sound/soc/codecs/tlv320aic3x.h47
1 files changed, 25 insertions, 22 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h
index 98e44395b662..20d8cac2637c 100644
--- a/sound/soc/codecs/tlv320aic3x.h
+++ b/sound/soc/codecs/tlv320aic3x.h
@@ -81,52 +81,55 @@
81/* DAC Digital control registers */ 81/* DAC Digital control registers */
82#define LDAC_VOL 43 82#define LDAC_VOL 43
83#define RDAC_VOL 44 83#define RDAC_VOL 44
84/* High Power Output control registers */ 84/* Left High Power Output control registers */
85#define LINE2L_2_HPLOUT_VOL 45 85#define LINE2L_2_HPLOUT_VOL 45
86#define LINE2R_2_HPROUT_VOL 62
87#define PGAL_2_HPLOUT_VOL 46 86#define PGAL_2_HPLOUT_VOL 46
88#define PGAL_2_HPROUT_VOL 60
89#define PGAR_2_HPLOUT_VOL 49
90#define PGAR_2_HPROUT_VOL 63
91#define DACL1_2_HPLOUT_VOL 47 87#define DACL1_2_HPLOUT_VOL 47
92#define DACR1_2_HPROUT_VOL 64 88#define PGAR_2_HPLOUT_VOL 49
93#define HPLOUT_CTRL 51 89#define HPLOUT_CTRL 51
94#define HPROUT_CTRL 65 90/* Left High Power COM control registers */
95/* High Power COM control registers */
96#define LINE2L_2_HPLCOM_VOL 52 91#define LINE2L_2_HPLCOM_VOL 52
97#define LINE2R_2_HPRCOM_VOL 69
98#define PGAL_2_HPLCOM_VOL 53 92#define PGAL_2_HPLCOM_VOL 53
93#define DACL1_2_HPLCOM_VOL 54
99#define PGAR_2_HPLCOM_VOL 56 94#define PGAR_2_HPLCOM_VOL 56
95#define HPLCOM_CTRL 58
96/* Right High Power Output control registers */
97#define PGAL_2_HPROUT_VOL 60
98#define LINE2R_2_HPROUT_VOL 62
99#define PGAR_2_HPROUT_VOL 63
100#define DACR1_2_HPROUT_VOL 64
101#define HPROUT_CTRL 65
102/* Right High Power COM control registers */
100#define PGAL_2_HPRCOM_VOL 67 103#define PGAL_2_HPRCOM_VOL 67
104#define LINE2R_2_HPRCOM_VOL 69
101#define PGAR_2_HPRCOM_VOL 70 105#define PGAR_2_HPRCOM_VOL 70
102#define DACL1_2_HPLCOM_VOL 54
103#define DACR1_2_HPRCOM_VOL 71 106#define DACR1_2_HPRCOM_VOL 71
104#define HPLCOM_CTRL 58
105#define HPRCOM_CTRL 72 107#define HPRCOM_CTRL 72
106/* Mono Line Output Plus/Minus control registers */ 108/* Mono Line Output Plus/Minus control registers */
107#define LINE2L_2_MONOLOPM_VOL 73 109#define LINE2L_2_MONOLOPM_VOL 73
108#define LINE2R_2_MONOLOPM_VOL 76
109#define PGAL_2_MONOLOPM_VOL 74 110#define PGAL_2_MONOLOPM_VOL 74
110#define PGAR_2_MONOLOPM_VOL 77
111#define DACL1_2_MONOLOPM_VOL 75 111#define DACL1_2_MONOLOPM_VOL 75
112#define LINE2R_2_MONOLOPM_VOL 76
113#define PGAR_2_MONOLOPM_VOL 77
112#define DACR1_2_MONOLOPM_VOL 78 114#define DACR1_2_MONOLOPM_VOL 78
113#define MONOLOPM_CTRL 79 115#define MONOLOPM_CTRL 79
114/* Class-D speaker driver on tlv320aic3007 */ 116/* Class-D speaker driver on tlv320aic3007 */
115#define CLASSD_CTRL 73 117#define CLASSD_CTRL 73
116/* Line Output Plus/Minus control registers */ 118/* Left Line Output Plus/Minus control registers */
117#define LINE2L_2_LLOPM_VOL 80 119#define LINE2L_2_LLOPM_VOL 80
118#define LINE2L_2_RLOPM_VOL 87
119#define LINE2R_2_LLOPM_VOL 83
120#define LINE2R_2_RLOPM_VOL 90
121#define PGAL_2_LLOPM_VOL 81 120#define PGAL_2_LLOPM_VOL 81
122#define PGAL_2_RLOPM_VOL 88
123#define PGAR_2_LLOPM_VOL 84
124#define PGAR_2_RLOPM_VOL 91
125#define DACL1_2_LLOPM_VOL 82 121#define DACL1_2_LLOPM_VOL 82
126#define DACL1_2_RLOPM_VOL 89 122#define LINE2R_2_LLOPM_VOL 83
127#define DACR1_2_RLOPM_VOL 92 123#define PGAR_2_LLOPM_VOL 84
128#define DACR1_2_LLOPM_VOL 85 124#define DACR1_2_LLOPM_VOL 85
129#define LLOPM_CTRL 86 125#define LLOPM_CTRL 86
126/* Right Line Output Plus/Minus control registers */
127#define LINE2L_2_RLOPM_VOL 87
128#define PGAL_2_RLOPM_VOL 88
129#define DACL1_2_RLOPM_VOL 89
130#define LINE2R_2_RLOPM_VOL 90
131#define PGAR_2_RLOPM_VOL 91
132#define DACR1_2_RLOPM_VOL 92
130#define RLOPM_CTRL 93 133#define RLOPM_CTRL 93
131/* GPIO/IRQ registers */ 134/* GPIO/IRQ registers */
132#define AIC3X_STICKY_IRQ_FLAGS_REG 96 135#define AIC3X_STICKY_IRQ_FLAGS_REG 96