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authorJarkko Nikula <jhnikula@gmail.com>2010-08-27 09:56:50 -0400
committerLiam Girdwood <lrg@slimlogic.co.uk>2010-08-28 05:57:58 -0400
commit098b1718230466b48f2027eb26cdc921760ae5da (patch)
tree3be1963f746845ea2b9be9df61e2fe8eb8338410 /sound/soc/codecs/tlv320aic3x.c
parentc3b79e05b4d9ab2e7c3ba281261ea87ab5b71a92 (diff)
ASoC: tlv320aic3x: Sanitize output controls
Currently output controls are not uniform. Some routes are adjusted by mono controls that don't match to associated mixer switch, many routes are not covered at all and stereo controls have following variants: - L-to-L & R-to-R - R-to-L & R-to-R - L-to-L & R-to-L This patch attempts to fix these issues. First, for the convenience, only direct L-to-L, R-to-R and [L | R]-to-Mono routes are controlled by the stereo controls. This logic is also used with the output pin mute controls so all of them except mono output are controlled by stereo switches. Then rest of the swapped L-to-R and R-to-L routes are controlled by the mono controls that map to mixer switches with a same name. Mixers can then associate these switches and volumes together. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'sound/soc/codecs/tlv320aic3x.c')
-rw-r--r--sound/soc/codecs/tlv320aic3x.c114
1 files changed, 76 insertions, 38 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 0a3b98c097bb..8577c50d8d22 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -292,64 +292,102 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = {
292 SOC_DOUBLE_R_TLV("PCM Playback Volume", 292 SOC_DOUBLE_R_TLV("PCM Playback Volume",
293 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 293 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
294 294
295 /*
296 * Output controls that map to output mixer switches. Note these are
297 * only for swapped L-to-R and R-to-L routes. See below stereo controls
298 * for direct L-to-L and R-to-R routes.
299 */
300 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
301 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
302 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
303 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
304 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
305 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
306
307 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
308 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
309 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
310 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
311 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
312 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
313
314 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
315 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
316 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
317 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
318 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
319 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
320
321 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
322 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
323 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
324 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
325 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
326 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
327
328 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
329 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
330 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
331 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
332 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
333 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
334
335 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
336 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
337 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
338 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
340 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
341
342 /* Stereo output controls for direct L-to-L and R-to-R routes */
343 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
344 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
345 0, 118, 1, output_stage_tlv),
346 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
347 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
348 0, 118, 1, output_stage_tlv),
295 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 349 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
296 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 350 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
297 0, 118, 1, output_stage_tlv), 351 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0), 352
299 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0), 353 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
300 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume", 354 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
301 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
302 0, 118, 1, output_stage_tlv),
303 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
304 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
305 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
306 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
307 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
308 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
309 0, 118, 1, output_stage_tlv), 355 0, 118, 1, output_stage_tlv),
310 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume", 356 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
311 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL, 357 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
312 0, 118, 1, output_stage_tlv), 358 0, 118, 1, output_stage_tlv),
313
314 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 359 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
315 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 360 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
316 0, 118, 1, output_stage_tlv), 361 0, 118, 1, output_stage_tlv),
317 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 362
318 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume", 363 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
319 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 364 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
320 0, 118, 1, output_stage_tlv), 365 0, 118, 1, output_stage_tlv),
321 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume", 366 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
322 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 367 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
323 0, 118, 1, output_stage_tlv), 368 0, 118, 1, output_stage_tlv),
324
325 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 369 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
326 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 370 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
327 0, 118, 1, output_stage_tlv), 371 0, 118, 1, output_stage_tlv),
328 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 372
329 0x01, 0), 373 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
330 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume", 374 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
331 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
332 0, 118, 1, output_stage_tlv), 375 0, 118, 1, output_stage_tlv),
333 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume", 376 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
334 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 377 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
335 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
336 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
337 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
338 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
339 0, 118, 1, output_stage_tlv), 378 0, 118, 1, output_stage_tlv),
340
341 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 379 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
342 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 380 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
343 0, 118, 1, output_stage_tlv), 381 0, 118, 1, output_stage_tlv),
382
383 /* Output pin mute controls */
384 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
385 0x01, 0),
386 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
387 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
388 0x01, 0),
344 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 389 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
345 0x01, 0), 390 0x01, 0),
346 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
347 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
348 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
349 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
350 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
351 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
352 0, 118, 1, output_stage_tlv),
353 391
354 /* 392 /*
355 * Note: enable Automatic input Gain Controller with care. It can 393 * Note: enable Automatic input Gain Controller with care. It can