diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-08-08 01:56:19 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-08-08 01:56:19 -0400 |
commit | 18d4ed4342c14ebeebe60d267b171053efcdfa87 (patch) | |
tree | f315e77f66cbb70869e2f80cde5c18380a80901e /sound/soc/codecs/sgtl5000.c | |
parent | 722d0daf2b607a32dad1357bf797e3803484af0a (diff) | |
parent | 22de4534ae12d61257fc0e53d2571686b03305bc (diff) |
Merge branch 'for-3.1' into for-3.2
Conflict due to the fix for the register map failure - taken the for-3.1
version.
Conflicts:
sound/soc/codecs/sgtl5000.c
Diffstat (limited to 'sound/soc/codecs/sgtl5000.c')
-rw-r--r-- | sound/soc/codecs/sgtl5000.c | 129 |
1 files changed, 35 insertions, 94 deletions
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index d9f8becafbf6..666fae6e148d 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c | |||
@@ -34,74 +34,31 @@ | |||
34 | #define SGTL5000_DAP_REG_OFFSET 0x0100 | 34 | #define SGTL5000_DAP_REG_OFFSET 0x0100 |
35 | #define SGTL5000_MAX_REG_OFFSET 0x013A | 35 | #define SGTL5000_MAX_REG_OFFSET 0x013A |
36 | 36 | ||
37 | /* default value of sgtl5000 registers except DAP */ | 37 | /* default value of sgtl5000 registers */ |
38 | static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET >> 1] = { | 38 | static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = { |
39 | 0xa011, /* 0x0000, CHIP_ID. 11 stand for revison 17 */ | 39 | [SGTL5000_CHIP_CLK_CTRL] = 0x0008, |
40 | 0x0000, /* 0x0002, CHIP_DIG_POWER. */ | 40 | [SGTL5000_CHIP_I2S_CTRL] = 0x0010, |
41 | 0x0008, /* 0x0004, CHIP_CKL_CTRL */ | 41 | [SGTL5000_CHIP_SSS_CTRL] = 0x0008, |
42 | 0x0010, /* 0x0006, CHIP_I2S_CTRL */ | 42 | [SGTL5000_CHIP_DAC_VOL] = 0x3c3c, |
43 | 0x0000, /* 0x0008, reserved */ | 43 | [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f, |
44 | 0x0008, /* 0x000A, CHIP_SSS_CTRL */ | 44 | [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818, |
45 | 0x0000, /* 0x000C, reserved */ | 45 | [SGTL5000_CHIP_ANA_CTRL] = 0x0111, |
46 | 0x020c, /* 0x000E, CHIP_ADCDAC_CTRL */ | 46 | [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404, |
47 | 0x3c3c, /* 0x0010, CHIP_DAC_VOL */ | 47 | [SGTL5000_CHIP_ANA_POWER] = 0x7060, |
48 | 0x0000, /* 0x0012, reserved */ | 48 | [SGTL5000_CHIP_PLL_CTRL] = 0x5000, |
49 | 0x015f, /* 0x0014, CHIP_PAD_STRENGTH */ | 49 | [SGTL5000_DAP_BASS_ENHANCE] = 0x0040, |
50 | 0x0000, /* 0x0016, reserved */ | 50 | [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f, |
51 | 0x0000, /* 0x0018, reserved */ | 51 | [SGTL5000_DAP_SURROUND] = 0x0040, |
52 | 0x0000, /* 0x001A, reserved */ | 52 | [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f, |
53 | 0x0000, /* 0x001C, reserved */ | 53 | [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f, |
54 | 0x0000, /* 0x001E, reserved */ | 54 | [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f, |
55 | 0x0000, /* 0x0020, CHIP_ANA_ADC_CTRL */ | 55 | [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f, |
56 | 0x1818, /* 0x0022, CHIP_ANA_HP_CTRL */ | 56 | [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f, |
57 | 0x0111, /* 0x0024, CHIP_ANN_CTRL */ | 57 | [SGTL5000_DAP_MAIN_CHAN] = 0x8000, |
58 | 0x0000, /* 0x0026, CHIP_LINREG_CTRL */ | 58 | [SGTL5000_DAP_AVC_CTRL] = 0x0510, |
59 | 0x0000, /* 0x0028, CHIP_REF_CTRL */ | 59 | [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473, |
60 | 0x0000, /* 0x002A, CHIP_MIC_CTRL */ | 60 | [SGTL5000_DAP_AVC_ATTACK] = 0x0028, |
61 | 0x0000, /* 0x002C, CHIP_LINE_OUT_CTRL */ | 61 | [SGTL5000_DAP_AVC_DECAY] = 0x0050, |
62 | 0x0404, /* 0x002E, CHIP_LINE_OUT_VOL */ | ||
63 | 0x7060, /* 0x0030, CHIP_ANA_POWER */ | ||
64 | 0x5000, /* 0x0032, CHIP_PLL_CTRL */ | ||
65 | 0x0000, /* 0x0034, CHIP_CLK_TOP_CTRL */ | ||
66 | 0x0000, /* 0x0036, CHIP_ANA_STATUS */ | ||
67 | 0x0000, /* 0x0038, reserved */ | ||
68 | 0x0000, /* 0x003A, CHIP_ANA_TEST2 */ | ||
69 | 0x0000, /* 0x003C, CHIP_SHORT_CTRL */ | ||
70 | 0x0000, /* reserved */ | ||
71 | }; | ||
72 | |||
73 | /* default value of dap registers */ | ||
74 | static const u16 sgtl5000_dap_regs[] = { | ||
75 | 0x0000, /* 0x0100, DAP_CONTROL */ | ||
76 | 0x0000, /* 0x0102, DAP_PEQ */ | ||
77 | 0x0040, /* 0x0104, DAP_BASS_ENHANCE */ | ||
78 | 0x051f, /* 0x0106, DAP_BASS_ENHANCE_CTRL */ | ||
79 | 0x0000, /* 0x0108, DAP_AUDIO_EQ */ | ||
80 | 0x0040, /* 0x010A, DAP_SGTL_SURROUND */ | ||
81 | 0x0000, /* 0x010C, DAP_FILTER_COEF_ACCESS */ | ||
82 | 0x0000, /* 0x010E, DAP_COEF_WR_B0_MSB */ | ||
83 | 0x0000, /* 0x0110, DAP_COEF_WR_B0_LSB */ | ||
84 | 0x0000, /* 0x0112, reserved */ | ||
85 | 0x0000, /* 0x0114, reserved */ | ||
86 | 0x002f, /* 0x0116, DAP_AUDIO_EQ_BASS_BAND0 */ | ||
87 | 0x002f, /* 0x0118, DAP_AUDIO_EQ_BAND0 */ | ||
88 | 0x002f, /* 0x011A, DAP_AUDIO_EQ_BAND2 */ | ||
89 | 0x002f, /* 0x011C, DAP_AUDIO_EQ_BAND3 */ | ||
90 | 0x002f, /* 0x011E, DAP_AUDIO_EQ_TREBLE_BAND4 */ | ||
91 | 0x8000, /* 0x0120, DAP_MAIN_CHAN */ | ||
92 | 0x0000, /* 0x0122, DAP_MIX_CHAN */ | ||
93 | 0x0510, /* 0x0124, DAP_AVC_CTRL */ | ||
94 | 0x1473, /* 0x0126, DAP_AVC_THRESHOLD */ | ||
95 | 0x0028, /* 0x0128, DAP_AVC_ATTACK */ | ||
96 | 0x0050, /* 0x012A, DAP_AVC_DECAY */ | ||
97 | 0x0000, /* 0x012C, DAP_COEF_WR_B1_MSB */ | ||
98 | 0x0000, /* 0x012E, DAP_COEF_WR_B1_LSB */ | ||
99 | 0x0000, /* 0x0130, DAP_COEF_WR_B2_MSB */ | ||
100 | 0x0000, /* 0x0132, DAP_COEF_WR_B2_LSB */ | ||
101 | 0x0000, /* 0x0134, DAP_COEF_WR_A1_MSB */ | ||
102 | 0x0000, /* 0x0136, DAP_COEF_WR_A1_LSB */ | ||
103 | 0x0000, /* 0x0138, DAP_COEF_WR_A2_MSB */ | ||
104 | 0x0000, /* 0x013A, DAP_COEF_WR_A2_LSB */ | ||
105 | }; | 62 | }; |
106 | 63 | ||
107 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ | 64 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ |
@@ -1025,12 +982,10 @@ static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state) | |||
1025 | static int sgtl5000_restore_regs(struct snd_soc_codec *codec) | 982 | static int sgtl5000_restore_regs(struct snd_soc_codec *codec) |
1026 | { | 983 | { |
1027 | u16 *cache = codec->reg_cache; | 984 | u16 *cache = codec->reg_cache; |
1028 | int i; | 985 | u16 reg; |
1029 | int regular_regs = SGTL5000_CHIP_SHORT_CTRL >> 1; | ||
1030 | 986 | ||
1031 | /* restore regular registers */ | 987 | /* restore regular registers */ |
1032 | for (i = 0; i < regular_regs; i++) { | 988 | for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { |
1033 | int reg = i << 1; | ||
1034 | 989 | ||
1035 | /* this regs depends on the others */ | 990 | /* this regs depends on the others */ |
1036 | if (reg == SGTL5000_CHIP_ANA_POWER || | 991 | if (reg == SGTL5000_CHIP_ANA_POWER || |
@@ -1040,35 +995,31 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec) | |||
1040 | reg == SGTL5000_CHIP_CLK_CTRL) | 995 | reg == SGTL5000_CHIP_CLK_CTRL) |
1041 | continue; | 996 | continue; |
1042 | 997 | ||
1043 | snd_soc_write(codec, reg, cache[i]); | 998 | snd_soc_write(codec, reg, cache[reg]); |
1044 | } | 999 | } |
1045 | 1000 | ||
1046 | /* restore dap registers */ | 1001 | /* restore dap registers */ |
1047 | for (i = SGTL5000_DAP_REG_OFFSET >> 1; | 1002 | for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2) |
1048 | i < SGTL5000_MAX_REG_OFFSET >> 1; i++) { | 1003 | snd_soc_write(codec, reg, cache[reg]); |
1049 | int reg = i << 1; | ||
1050 | |||
1051 | snd_soc_write(codec, reg, cache[i]); | ||
1052 | } | ||
1053 | 1004 | ||
1054 | /* | 1005 | /* |
1055 | * restore power and other regs according | 1006 | * restore power and other regs according |
1056 | * to set_power() and set_clock() | 1007 | * to set_power() and set_clock() |
1057 | */ | 1008 | */ |
1058 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, | 1009 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, |
1059 | cache[SGTL5000_CHIP_LINREG_CTRL >> 1]); | 1010 | cache[SGTL5000_CHIP_LINREG_CTRL]); |
1060 | 1011 | ||
1061 | snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, | 1012 | snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, |
1062 | cache[SGTL5000_CHIP_ANA_POWER >> 1]); | 1013 | cache[SGTL5000_CHIP_ANA_POWER]); |
1063 | 1014 | ||
1064 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, | 1015 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, |
1065 | cache[SGTL5000_CHIP_CLK_CTRL >> 1]); | 1016 | cache[SGTL5000_CHIP_CLK_CTRL]); |
1066 | 1017 | ||
1067 | snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, | 1018 | snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, |
1068 | cache[SGTL5000_CHIP_REF_CTRL >> 1]); | 1019 | cache[SGTL5000_CHIP_REF_CTRL]); |
1069 | 1020 | ||
1070 | snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, | 1021 | snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, |
1071 | cache[SGTL5000_CHIP_LINE_OUT_CTRL >> 1]); | 1022 | cache[SGTL5000_CHIP_LINE_OUT_CTRL]); |
1072 | return 0; | 1023 | return 0; |
1073 | } | 1024 | } |
1074 | 1025 | ||
@@ -1456,16 +1407,6 @@ static __devinit int sgtl5000_i2c_probe(struct i2c_client *client, | |||
1456 | if (!sgtl5000) | 1407 | if (!sgtl5000) |
1457 | return -ENOMEM; | 1408 | return -ENOMEM; |
1458 | 1409 | ||
1459 | /* | ||
1460 | * copy DAP default values to default value array. | ||
1461 | * sgtl5000 register space has a big hole, merge it | ||
1462 | * at init phase makes life easy. | ||
1463 | * FIXME: should we drop 'const' of sgtl5000_regs? | ||
1464 | */ | ||
1465 | memcpy((void *)(&sgtl5000_regs[0] + (SGTL5000_DAP_REG_OFFSET >> 1)), | ||
1466 | sgtl5000_dap_regs, | ||
1467 | SGTL5000_MAX_REG_OFFSET - SGTL5000_DAP_REG_OFFSET); | ||
1468 | |||
1469 | i2c_set_clientdata(client, sgtl5000); | 1410 | i2c_set_clientdata(client, sgtl5000); |
1470 | 1411 | ||
1471 | ret = snd_soc_register_codec(&client->dev, | 1412 | ret = snd_soc_register_codec(&client->dev, |