diff options
author | Zeng Zhaoming <zengzm.kernel@gmail.com> | 2012-01-18 00:58:07 -0500 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2012-01-20 08:54:32 -0500 |
commit | bb362e2e4f4874f3fd4cbc2497385b9bceb3a08a (patch) | |
tree | b70cec68252f8dee5953713c842f5b426cf2eb9c /sound/soc/codecs/sgtl5000.c | |
parent | dcd6c92267155e70a94b3927bce681ce74b80d1f (diff) |
ASoC: sgtl5000: Fix wrong register name in restore
Correct SGTL5000_CHIP_CLK_CTRL to SGTL5000_CHIP_REF_CTRL in
sgtl5000_restore_regs(), and add comment to explain the
restore order.
Reported-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Zeng Zhaoming <zengzm.kernel@gmail.com>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/sgtl5000.c')
-rw-r--r-- | sound/soc/codecs/sgtl5000.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index f8863ebb4304..7f4ba819a9f6 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c | |||
@@ -987,12 +987,12 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec) | |||
987 | /* restore regular registers */ | 987 | /* restore regular registers */ |
988 | for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { | 988 | for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { |
989 | 989 | ||
990 | /* this regs depends on the others */ | 990 | /* These regs should restore in particular order */ |
991 | if (reg == SGTL5000_CHIP_ANA_POWER || | 991 | if (reg == SGTL5000_CHIP_ANA_POWER || |
992 | reg == SGTL5000_CHIP_CLK_CTRL || | 992 | reg == SGTL5000_CHIP_CLK_CTRL || |
993 | reg == SGTL5000_CHIP_LINREG_CTRL || | 993 | reg == SGTL5000_CHIP_LINREG_CTRL || |
994 | reg == SGTL5000_CHIP_LINE_OUT_CTRL || | 994 | reg == SGTL5000_CHIP_LINE_OUT_CTRL || |
995 | reg == SGTL5000_CHIP_CLK_CTRL) | 995 | reg == SGTL5000_CHIP_REF_CTRL) |
996 | continue; | 996 | continue; |
997 | 997 | ||
998 | snd_soc_write(codec, reg, cache[reg]); | 998 | snd_soc_write(codec, reg, cache[reg]); |
@@ -1003,8 +1003,17 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec) | |||
1003 | snd_soc_write(codec, reg, cache[reg]); | 1003 | snd_soc_write(codec, reg, cache[reg]); |
1004 | 1004 | ||
1005 | /* | 1005 | /* |
1006 | * restore power and other regs according | 1006 | * restore these regs according to the power setting sequence in |
1007 | * to set_power() and set_clock() | 1007 | * sgtl5000_set_power_regs() and clock setting sequence in |
1008 | * sgtl5000_set_clock(). | ||
1009 | * | ||
1010 | * The order of restore is: | ||
1011 | * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after | ||
1012 | * SGTL5000_CHIP_ANA_POWER PLL bits set | ||
1013 | * 2. SGTL5000_CHIP_LINREG_CTRL should be set before | ||
1014 | * SGTL5000_CHIP_ANA_POWER LINREG_D restored | ||
1015 | * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage, | ||
1016 | * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored | ||
1008 | */ | 1017 | */ |
1009 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, | 1018 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, |
1010 | cache[SGTL5000_CHIP_LINREG_CTRL]); | 1019 | cache[SGTL5000_CHIP_LINREG_CTRL]); |