ASoC: max98090: Add master clock handling

If master clock is provided through device tree, then update
the master clock frequency during set_sysclk.

Documentation has been updated to reflect the change.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>

1 files changed, 23 insertions, 0 deletions

diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index 4ee1f88760c4..8857be798f3b 100644
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
@@ -16,6 +16,7 @@
 #include <linux/regmap.h>
 #include <linux/slab.h>
 #include <linux/acpi.h>
+#include <linux/clk.h>
 #include <sound/jack.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -1798,6 +1799,19 @@ static int max98090_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_PREPARE:
+                /*
+                 * SND_SOC_BIAS_PREPARE is called while preparing for a
+                 * transition to ON or away from ON. If current bias_level
+                 * is SND_SOC_BIAS_ON, then it is preparing for a transition
+                 * away from ON. Disable the clock in that case, otherwise
+                 * enable it.
+                 */
+                if (!IS_ERR(max98090->mclk)) {
+                        if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
+                                clk_disable_unprepare(max98090->mclk);
+                        else
+                                clk_prepare_enable(max98090->mclk);
+                }
                 break;
 
         case SND_SOC_BIAS_STANDBY:
@@ -1927,6 +1941,11 @@ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
         if (freq == max98090->sysclk)
                 return 0;
 
+        if (!IS_ERR(max98090->mclk)) {
+                freq = clk_round_rate(max98090->mclk, freq);
+                clk_set_rate(max98090->mclk, freq);
+        }
+
         /* Setup clocks for slave mode, and using the PLL
          * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
          *               0x02 (when master clk is 20MHz to 40MHz)..
@@ -2211,6 +2230,10 @@ static int max98090_probe(struct snd_soc_codec *codec)
 
         dev_dbg(codec->dev, "max98090_probe\n");
 
+        max98090->mclk = devm_clk_get(codec->dev, "mclk");
+        if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
+                return -EPROBE_DEFER;
+
         max98090->codec = codec;
 
         /* Reset the codec, the DSP core, and disable all interrupts */