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authorAshish Chavan <ashish.chavan@kpitcummins.com>2012-09-21 10:46:17 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-09-28 09:21:54 -0400
commit9911f7f7562a25381eff93fdc660a4a3b4c0f6e0 (patch)
treebe43efe4c9efbeb9d2ac4a1ec90fb13a5be13301 /sound/soc/codecs/da9055.c
parentda75c924878c48b3ee6ce21579bbf679f93ce40c (diff)
ASoC: codecs: Add DA9055 codec driver
This patch adds support for Dialog semiconductor's DA9055 audio codec. This has been tested on DA9055 EVB with Samsung SMDK6410 board. Signed-off-by: Ashish Chavan <ashish.chavan@kpitcummins.com> Signed-off-by: David Dajun Chen <david.chen@diasemi.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/da9055.c')
-rw-r--r--sound/soc/codecs/da9055.c1510
1 files changed, 1510 insertions, 0 deletions
diff --git a/sound/soc/codecs/da9055.c b/sound/soc/codecs/da9055.c
new file mode 100644
index 000000000000..185d8dd36399
--- /dev/null
+++ b/sound/soc/codecs/da9055.c
@@ -0,0 +1,1510 @@
1/*
2 * DA9055 ALSA Soc codec driver
3 *
4 * Copyright (c) 2012 Dialog Semiconductor
5 *
6 * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
7 * Written by David Chen <david.chen@diasemi.com> and
8 * Ashish Chavan <ashish.chavan@kpitcummins.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/delay.h>
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19#include <linux/slab.h>
20#include <linux/module.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/soc.h>
24#include <sound/initval.h>
25#include <sound/tlv.h>
26#include <sound/da9055.h>
27
28/* DA9055 register space */
29
30/* Status Registers */
31#define DA9055_STATUS1 0x02
32#define DA9055_PLL_STATUS 0x03
33#define DA9055_AUX_L_GAIN_STATUS 0x04
34#define DA9055_AUX_R_GAIN_STATUS 0x05
35#define DA9055_MIC_L_GAIN_STATUS 0x06
36#define DA9055_MIC_R_GAIN_STATUS 0x07
37#define DA9055_MIXIN_L_GAIN_STATUS 0x08
38#define DA9055_MIXIN_R_GAIN_STATUS 0x09
39#define DA9055_ADC_L_GAIN_STATUS 0x0A
40#define DA9055_ADC_R_GAIN_STATUS 0x0B
41#define DA9055_DAC_L_GAIN_STATUS 0x0C
42#define DA9055_DAC_R_GAIN_STATUS 0x0D
43#define DA9055_HP_L_GAIN_STATUS 0x0E
44#define DA9055_HP_R_GAIN_STATUS 0x0F
45#define DA9055_LINE_GAIN_STATUS 0x10
46
47/* System Initialisation Registers */
48#define DA9055_CIF_CTRL 0x20
49#define DA9055_DIG_ROUTING_AIF 0X21
50#define DA9055_SR 0x22
51#define DA9055_REFERENCES 0x23
52#define DA9055_PLL_FRAC_TOP 0x24
53#define DA9055_PLL_FRAC_BOT 0x25
54#define DA9055_PLL_INTEGER 0x26
55#define DA9055_PLL_CTRL 0x27
56#define DA9055_AIF_CLK_MODE 0x28
57#define DA9055_AIF_CTRL 0x29
58#define DA9055_DIG_ROUTING_DAC 0x2A
59#define DA9055_ALC_CTRL1 0x2B
60
61/* Input - Gain, Select and Filter Registers */
62#define DA9055_AUX_L_GAIN 0x30
63#define DA9055_AUX_R_GAIN 0x31
64#define DA9055_MIXIN_L_SELECT 0x32
65#define DA9055_MIXIN_R_SELECT 0x33
66#define DA9055_MIXIN_L_GAIN 0x34
67#define DA9055_MIXIN_R_GAIN 0x35
68#define DA9055_ADC_L_GAIN 0x36
69#define DA9055_ADC_R_GAIN 0x37
70#define DA9055_ADC_FILTERS1 0x38
71#define DA9055_MIC_L_GAIN 0x39
72#define DA9055_MIC_R_GAIN 0x3A
73
74/* Output - Gain, Select and Filter Registers */
75#define DA9055_DAC_FILTERS5 0x40
76#define DA9055_DAC_FILTERS2 0x41
77#define DA9055_DAC_FILTERS3 0x42
78#define DA9055_DAC_FILTERS4 0x43
79#define DA9055_DAC_FILTERS1 0x44
80#define DA9055_DAC_L_GAIN 0x45
81#define DA9055_DAC_R_GAIN 0x46
82#define DA9055_CP_CTRL 0x47
83#define DA9055_HP_L_GAIN 0x48
84#define DA9055_HP_R_GAIN 0x49
85#define DA9055_LINE_GAIN 0x4A
86#define DA9055_MIXOUT_L_SELECT 0x4B
87#define DA9055_MIXOUT_R_SELECT 0x4C
88
89/* System Controller Registers */
90#define DA9055_SYSTEM_MODES_INPUT 0x50
91#define DA9055_SYSTEM_MODES_OUTPUT 0x51
92
93/* Control Registers */
94#define DA9055_AUX_L_CTRL 0x60
95#define DA9055_AUX_R_CTRL 0x61
96#define DA9055_MIC_BIAS_CTRL 0x62
97#define DA9055_MIC_L_CTRL 0x63
98#define DA9055_MIC_R_CTRL 0x64
99#define DA9055_MIXIN_L_CTRL 0x65
100#define DA9055_MIXIN_R_CTRL 0x66
101#define DA9055_ADC_L_CTRL 0x67
102#define DA9055_ADC_R_CTRL 0x68
103#define DA9055_DAC_L_CTRL 0x69
104#define DA9055_DAC_R_CTRL 0x6A
105#define DA9055_HP_L_CTRL 0x6B
106#define DA9055_HP_R_CTRL 0x6C
107#define DA9055_LINE_CTRL 0x6D
108#define DA9055_MIXOUT_L_CTRL 0x6E
109#define DA9055_MIXOUT_R_CTRL 0x6F
110
111/* Configuration Registers */
112#define DA9055_LDO_CTRL 0x90
113#define DA9055_IO_CTRL 0x91
114#define DA9055_GAIN_RAMP_CTRL 0x92
115#define DA9055_MIC_CONFIG 0x93
116#define DA9055_PC_COUNT 0x94
117#define DA9055_CP_VOL_THRESHOLD1 0x95
118#define DA9055_CP_DELAY 0x96
119#define DA9055_CP_DETECTOR 0x97
120#define DA9055_AIF_OFFSET 0x98
121#define DA9055_DIG_CTRL 0x99
122#define DA9055_ALC_CTRL2 0x9A
123#define DA9055_ALC_CTRL3 0x9B
124#define DA9055_ALC_NOISE 0x9C
125#define DA9055_ALC_TARGET_MIN 0x9D
126#define DA9055_ALC_TARGET_MAX 0x9E
127#define DA9055_ALC_GAIN_LIMITS 0x9F
128#define DA9055_ALC_ANA_GAIN_LIMITS 0xA0
129#define DA9055_ALC_ANTICLIP_CTRL 0xA1
130#define DA9055_ALC_ANTICLIP_LEVEL 0xA2
131#define DA9055_ALC_OFFSET_OP2M_L 0xA6
132#define DA9055_ALC_OFFSET_OP2U_L 0xA7
133#define DA9055_ALC_OFFSET_OP2M_R 0xAB
134#define DA9055_ALC_OFFSET_OP2U_R 0xAC
135#define DA9055_ALC_CIC_OP_LVL_CTRL 0xAD
136#define DA9055_ALC_CIC_OP_LVL_DATA 0xAE
137#define DA9055_DAC_NG_SETUP_TIME 0xAF
138#define DA9055_DAC_NG_OFF_THRESHOLD 0xB0
139#define DA9055_DAC_NG_ON_THRESHOLD 0xB1
140#define DA9055_DAC_NG_CTRL 0xB2
141
142/* SR bit fields */
143#define DA9055_SR_8000 (0x1 << 0)
144#define DA9055_SR_11025 (0x2 << 0)
145#define DA9055_SR_12000 (0x3 << 0)
146#define DA9055_SR_16000 (0x5 << 0)
147#define DA9055_SR_22050 (0x6 << 0)
148#define DA9055_SR_24000 (0x7 << 0)
149#define DA9055_SR_32000 (0x9 << 0)
150#define DA9055_SR_44100 (0xA << 0)
151#define DA9055_SR_48000 (0xB << 0)
152#define DA9055_SR_88200 (0xE << 0)
153#define DA9055_SR_96000 (0xF << 0)
154
155/* REFERENCES bit fields */
156#define DA9055_BIAS_EN (1 << 3)
157#define DA9055_VMID_EN (1 << 7)
158
159/* PLL_CTRL bit fields */
160#define DA9055_PLL_INDIV_10_20_MHZ (1 << 2)
161#define DA9055_PLL_SRM_EN (1 << 6)
162#define DA9055_PLL_EN (1 << 7)
163
164/* AIF_CLK_MODE bit fields */
165#define DA9055_AIF_BCLKS_PER_WCLK_32 (0 << 0)
166#define DA9055_AIF_BCLKS_PER_WCLK_64 (1 << 0)
167#define DA9055_AIF_BCLKS_PER_WCLK_128 (2 << 0)
168#define DA9055_AIF_BCLKS_PER_WCLK_256 (3 << 0)
169#define DA9055_AIF_CLK_EN_SLAVE_MODE (0 << 7)
170#define DA9055_AIF_CLK_EN_MASTER_MODE (1 << 7)
171
172/* AIF_CTRL bit fields */
173#define DA9055_AIF_FORMAT_I2S_MODE (0 << 0)
174#define DA9055_AIF_FORMAT_LEFT_J (1 << 0)
175#define DA9055_AIF_FORMAT_RIGHT_J (2 << 0)
176#define DA9055_AIF_WORD_S16_LE (0 << 2)
177#define DA9055_AIF_WORD_S20_3LE (1 << 2)
178#define DA9055_AIF_WORD_S24_LE (2 << 2)
179#define DA9055_AIF_WORD_S32_LE (3 << 2)
180
181/* MIXIN_L_CTRL bit fields */
182#define DA9055_MIXIN_L_MIX_EN (1 << 3)
183
184/* MIXIN_R_CTRL bit fields */
185#define DA9055_MIXIN_R_MIX_EN (1 << 3)
186
187/* ADC_L_CTRL bit fields */
188#define DA9055_ADC_L_EN (1 << 7)
189
190/* ADC_R_CTRL bit fields */
191#define DA9055_ADC_R_EN (1 << 7)
192
193/* DAC_L_CTRL bit fields */
194#define DA9055_DAC_L_MUTE_EN (1 << 6)
195
196/* DAC_R_CTRL bit fields */
197#define DA9055_DAC_R_MUTE_EN (1 << 6)
198
199/* HP_L_CTRL bit fields */
200#define DA9055_HP_L_AMP_OE (1 << 3)
201
202/* HP_R_CTRL bit fields */
203#define DA9055_HP_R_AMP_OE (1 << 3)
204
205/* LINE_CTRL bit fields */
206#define DA9055_LINE_AMP_OE (1 << 3)
207
208/* MIXOUT_L_CTRL bit fields */
209#define DA9055_MIXOUT_L_MIX_EN (1 << 3)
210
211/* MIXOUT_R_CTRL bit fields */
212#define DA9055_MIXOUT_R_MIX_EN (1 << 3)
213
214/* MIC bias select bit fields */
215#define DA9055_MICBIAS2_EN (1 << 6)
216
217/* ALC_CIC_OP_LEVEL_CTRL bit fields */
218#define DA9055_ALC_DATA_MIDDLE (2 << 0)
219#define DA9055_ALC_DATA_TOP (3 << 0)
220#define DA9055_ALC_CIC_OP_CHANNEL_LEFT (0 << 7)
221#define DA9055_ALC_CIC_OP_CHANNEL_RIGHT (1 << 7)
222
223#define DA9055_AIF_BCLK_MASK (3 << 0)
224#define DA9055_AIF_CLK_MODE_MASK (1 << 7)
225#define DA9055_AIF_FORMAT_MASK (3 << 0)
226#define DA9055_AIF_WORD_LENGTH_MASK (3 << 2)
227#define DA9055_GAIN_RAMPING_EN (1 << 5)
228#define DA9055_MICBIAS_LEVEL_MASK (3 << 4)
229
230#define DA9055_ALC_OFFSET_15_8 0x00FF00
231#define DA9055_ALC_OFFSET_17_16 0x030000
232#define DA9055_ALC_AVG_ITERATIONS 5
233
234struct pll_div {
235 int fref;
236 int fout;
237 u8 frac_top;
238 u8 frac_bot;
239 u8 integer;
240 u8 mode; /* 0 = slave, 1 = master */
241};
242
243/* PLL divisor table */
244static const struct pll_div da9055_pll_div[] = {
245 /* for MASTER mode, fs = 44.1Khz and its harmonics */
246 {11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */
247 {12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */
248 {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */
249 {13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */
250 {13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */
251 {14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */
252 {19200000, 2822400, 0x1A, 0x1C, 0x12, 1}, /* MCLK=19.2Mhz */
253 {19680000, 2822400, 0x0B, 0x6D, 0x12, 1}, /* MCLK=19.68Mhz */
254 {19800000, 2822400, 0x07, 0xDD, 0x12, 1}, /* MCLK=19.8Mhz */
255 /* for MASTER mode, fs = 48Khz and its harmonics */
256 {11289600, 3072000, 0x1A, 0x8E, 0x22, 1}, /* MCLK=11.2896Mhz */
257 {12000000, 3072000, 0x18, 0x93, 0x20, 1}, /* MCLK=12Mhz */
258 {12288000, 3072000, 0x00, 0x00, 0x20, 1}, /* MCLK=12.288Mhz */
259 {13000000, 3072000, 0x07, 0xEA, 0x1E, 1}, /* MCLK=13Mhz */
260 {13500000, 3072000, 0x04, 0x11, 0x1D, 1}, /* MCLK=13.5Mhz */
261 {14400000, 3072000, 0x09, 0xD0, 0x1B, 1}, /* MCLK=14.4Mhz */
262 {19200000, 3072000, 0x0F, 0x5C, 0x14, 1}, /* MCLK=19.2Mhz */
263 {19680000, 3072000, 0x1F, 0x60, 0x13, 1}, /* MCLK=19.68Mhz */
264 {19800000, 3072000, 0x1B, 0x80, 0x13, 1}, /* MCLK=19.8Mhz */
265 /* for SLAVE mode with SRM */
266 {11289600, 2822400, 0x0D, 0x47, 0x21, 0}, /* MCLK=11.2896Mhz */
267 {12000000, 2822400, 0x0D, 0xFA, 0x1F, 0}, /* MCLK=12Mhz */
268 {12288000, 2822400, 0x16, 0x66, 0x1E, 0}, /* MCLK=12.288Mhz */
269 {13000000, 2822400, 0x00, 0x98, 0x1D, 0}, /* MCLK=13Mhz */
270 {13500000, 2822400, 0x1E, 0x33, 0x1B, 0}, /* MCLK=13.5Mhz */
271 {14400000, 2822400, 0x06, 0x50, 0x1A, 0}, /* MCLK=14.4Mhz */
272 {19200000, 2822400, 0x14, 0xBC, 0x13, 0}, /* MCLK=19.2Mhz */
273 {19680000, 2822400, 0x05, 0x66, 0x13, 0}, /* MCLK=19.68Mhz */
274 {19800000, 2822400, 0x01, 0xAE, 0x13, 0}, /* MCLK=19.8Mhz */
275};
276
277enum clk_src {
278 DA9055_CLKSRC_MCLK
279};
280
281/* Gain and Volume */
282
283static const unsigned int aux_vol_tlv[] = {
284 TLV_DB_RANGE_HEAD(2),
285 0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
286 /* -54dB to 15dB */
287 0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
288};
289
290static const unsigned int digital_gain_tlv[] = {
291 TLV_DB_RANGE_HEAD(2),
292 0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
293 /* -78dB to 12dB */
294 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
295};
296
297static const unsigned int alc_analog_gain_tlv[] = {
298 TLV_DB_RANGE_HEAD(2),
299 0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
300 /* 0dB to 36dB */
301 0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0)
302};
303
304static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
305static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
306static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
307static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
308static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
309static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
310static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0);
311
312/* ADC and DAC high pass filter cutoff value */
313static const char * const da9055_hpf_cutoff_txt[] = {
314 "Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
315};
316
317static const struct soc_enum da9055_dac_hpf_cutoff =
318 SOC_ENUM_SINGLE(DA9055_DAC_FILTERS1, 4, 4, da9055_hpf_cutoff_txt);
319
320static const struct soc_enum da9055_adc_hpf_cutoff =
321 SOC_ENUM_SINGLE(DA9055_ADC_FILTERS1, 4, 4, da9055_hpf_cutoff_txt);
322
323/* ADC and DAC voice mode (8kHz) high pass cutoff value */
324static const char * const da9055_vf_cutoff_txt[] = {
325 "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
326};
327
328static const struct soc_enum da9055_dac_vf_cutoff =
329 SOC_ENUM_SINGLE(DA9055_DAC_FILTERS1, 0, 8, da9055_vf_cutoff_txt);
330
331static const struct soc_enum da9055_adc_vf_cutoff =
332 SOC_ENUM_SINGLE(DA9055_ADC_FILTERS1, 0, 8, da9055_vf_cutoff_txt);
333
334/* Gain ramping rate value */
335static const char * const da9055_gain_ramping_txt[] = {
336 "nominal rate", "nominal rate * 4", "nominal rate * 8",
337 "nominal rate / 8"
338};
339
340static const struct soc_enum da9055_gain_ramping_rate =
341 SOC_ENUM_SINGLE(DA9055_GAIN_RAMP_CTRL, 0, 4, da9055_gain_ramping_txt);
342
343/* DAC noise gate setup time value */
344static const char * const da9055_dac_ng_setup_time_txt[] = {
345 "256 samples", "512 samples", "1024 samples", "2048 samples"
346};
347
348static const struct soc_enum da9055_dac_ng_setup_time =
349 SOC_ENUM_SINGLE(DA9055_DAC_NG_SETUP_TIME, 0, 4,
350 da9055_dac_ng_setup_time_txt);
351
352/* DAC noise gate rampup rate value */
353static const char * const da9055_dac_ng_rampup_txt[] = {
354 "0.02 ms/dB", "0.16 ms/dB"
355};
356
357static const struct soc_enum da9055_dac_ng_rampup_rate =
358 SOC_ENUM_SINGLE(DA9055_DAC_NG_SETUP_TIME, 2, 2,
359 da9055_dac_ng_rampup_txt);
360
361/* DAC noise gate rampdown rate value */
362static const char * const da9055_dac_ng_rampdown_txt[] = {
363 "0.64 ms/dB", "20.48 ms/dB"
364};
365
366static const struct soc_enum da9055_dac_ng_rampdown_rate =
367 SOC_ENUM_SINGLE(DA9055_DAC_NG_SETUP_TIME, 3, 2,
368 da9055_dac_ng_rampdown_txt);
369
370/* DAC soft mute rate value */
371static const char * const da9055_dac_soft_mute_rate_txt[] = {
372 "1", "2", "4", "8", "16", "32", "64"
373};
374
375static const struct soc_enum da9055_dac_soft_mute_rate =
376 SOC_ENUM_SINGLE(DA9055_DAC_FILTERS5, 4, 7,
377 da9055_dac_soft_mute_rate_txt);
378
379/* DAC routing select */
380static const char * const da9055_dac_src_txt[] = {
381 "ADC output left", "ADC output right", "AIF input left",
382 "AIF input right"
383};
384
385static const struct soc_enum da9055_dac_l_src =
386 SOC_ENUM_SINGLE(DA9055_DIG_ROUTING_DAC, 0, 4, da9055_dac_src_txt);
387
388static const struct soc_enum da9055_dac_r_src =
389 SOC_ENUM_SINGLE(DA9055_DIG_ROUTING_DAC, 4, 4, da9055_dac_src_txt);
390
391/* MIC PGA Left source select */
392static const char * const da9055_mic_l_src_txt[] = {
393 "MIC1_P_N", "MIC1_P", "MIC1_N", "MIC2_L"
394};
395
396static const struct soc_enum da9055_mic_l_src =
397 SOC_ENUM_SINGLE(DA9055_MIXIN_L_SELECT, 4, 4, da9055_mic_l_src_txt);
398
399/* MIC PGA Right source select */
400static const char * const da9055_mic_r_src_txt[] = {
401 "MIC2_R_L", "MIC2_R", "MIC2_L"
402};
403
404static const struct soc_enum da9055_mic_r_src =
405 SOC_ENUM_SINGLE(DA9055_MIXIN_R_SELECT, 4, 3, da9055_mic_r_src_txt);
406
407/* ALC Input Signal Tracking rate select */
408static const char * const da9055_signal_tracking_rate_txt[] = {
409 "1/4", "1/16", "1/256", "1/65536"
410};
411
412static const struct soc_enum da9055_integ_attack_rate =
413 SOC_ENUM_SINGLE(DA9055_ALC_CTRL3, 4, 4,
414 da9055_signal_tracking_rate_txt);
415
416static const struct soc_enum da9055_integ_release_rate =
417 SOC_ENUM_SINGLE(DA9055_ALC_CTRL3, 6, 4,
418 da9055_signal_tracking_rate_txt);
419
420/* ALC Attack Rate select */
421static const char * const da9055_attack_rate_txt[] = {
422 "44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
423 "5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
424};
425
426static const struct soc_enum da9055_attack_rate =
427 SOC_ENUM_SINGLE(DA9055_ALC_CTRL2, 0, 13, da9055_attack_rate_txt);
428
429/* ALC Release Rate select */
430static const char * const da9055_release_rate_txt[] = {
431 "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
432 "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
433};
434
435static const struct soc_enum da9055_release_rate =
436 SOC_ENUM_SINGLE(DA9055_ALC_CTRL2, 4, 11, da9055_release_rate_txt);
437
438/* ALC Hold Time select */
439static const char * const da9055_hold_time_txt[] = {
440 "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
441 "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
442 "253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
443};
444
445static const struct soc_enum da9055_hold_time =
446 SOC_ENUM_SINGLE(DA9055_ALC_CTRL3, 0, 16, da9055_hold_time_txt);
447
448static int da9055_get_alc_data(struct snd_soc_codec *codec, u8 reg_val)
449{
450 int mid_data, top_data;
451 int sum = 0;
452 u8 iteration;
453
454 for (iteration = 0; iteration < DA9055_ALC_AVG_ITERATIONS;
455 iteration++) {
456 /* Select the left or right channel and capture data */
457 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val);
458
459 /* Select middle 8 bits for read back from data register */
460 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL,
461 reg_val | DA9055_ALC_DATA_MIDDLE);
462 mid_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA);
463
464 /* Select top 8 bits for read back from data register */
465 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL,
466 reg_val | DA9055_ALC_DATA_TOP);
467 top_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA);
468
469 sum += ((mid_data << 8) | (top_data << 16));
470 }
471
472 return sum / DA9055_ALC_AVG_ITERATIONS;
473}
474
475static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol,
476 struct snd_ctl_elem_value *ucontrol)
477{
478 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
479 u8 reg_val, adc_left, adc_right;
480 int avg_left_data, avg_right_data, offset_l, offset_r;
481
482 if (ucontrol->value.integer.value[0]) {
483 /*
484 * While enabling ALC (or ALC sync mode), calibration of the DC
485 * offsets must be done first
486 */
487
488 /* Save current values from ADC control registers */
489 adc_left = snd_soc_read(codec, DA9055_ADC_L_CTRL);
490 adc_right = snd_soc_read(codec, DA9055_ADC_R_CTRL);
491
492 /* Enable ADC Left and Right */
493 snd_soc_update_bits(codec, DA9055_ADC_L_CTRL,
494 DA9055_ADC_L_EN, DA9055_ADC_L_EN);
495 snd_soc_update_bits(codec, DA9055_ADC_R_CTRL,
496 DA9055_ADC_R_EN, DA9055_ADC_R_EN);
497
498 /* Calculate average for Left and Right data */
499 /* Left Data */
500 avg_left_data = da9055_get_alc_data(codec,
501 DA9055_ALC_CIC_OP_CHANNEL_LEFT);
502 /* Right Data */
503 avg_right_data = da9055_get_alc_data(codec,
504 DA9055_ALC_CIC_OP_CHANNEL_RIGHT);
505
506 /* Calculate DC offset */
507 offset_l = -avg_left_data;
508 offset_r = -avg_right_data;
509
510 reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8;
511 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_L, reg_val);
512 reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16;
513 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_L, reg_val);
514
515 reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8;
516 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_R, reg_val);
517 reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16;
518 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_R, reg_val);
519
520 /* Restore original values of ADC control registers */
521 snd_soc_write(codec, DA9055_ADC_L_CTRL, adc_left);
522 snd_soc_write(codec, DA9055_ADC_R_CTRL, adc_right);
523 }
524
525 return snd_soc_put_volsw(kcontrol, ucontrol);
526}
527
528static const struct snd_kcontrol_new da9055_snd_controls[] = {
529
530 /* Volume controls */
531 SOC_DOUBLE_R_TLV("Mic Volume",
532 DA9055_MIC_L_GAIN, DA9055_MIC_R_GAIN,
533 0, 0x7, 0, mic_vol_tlv),
534 SOC_DOUBLE_R_TLV("Aux Volume",
535 DA9055_AUX_L_GAIN, DA9055_AUX_R_GAIN,
536 0, 0x3f, 0, aux_vol_tlv),
537 SOC_DOUBLE_R_TLV("Mixin PGA Volume",
538 DA9055_MIXIN_L_GAIN, DA9055_MIXIN_R_GAIN,
539 0, 0xf, 0, mixin_gain_tlv),
540 SOC_DOUBLE_R_TLV("ADC Volume",
541 DA9055_ADC_L_GAIN, DA9055_ADC_R_GAIN,
542 0, 0x7f, 0, digital_gain_tlv),
543
544 SOC_DOUBLE_R_TLV("DAC Volume",
545 DA9055_DAC_L_GAIN, DA9055_DAC_R_GAIN,
546 0, 0x7f, 0, digital_gain_tlv),
547 SOC_DOUBLE_R_TLV("Headphone Volume",
548 DA9055_HP_L_GAIN, DA9055_HP_R_GAIN,
549 0, 0x3f, 0, hp_vol_tlv),
550 SOC_SINGLE_TLV("Lineout Volume", DA9055_LINE_GAIN, 0, 0x3f, 0,
551 lineout_vol_tlv),
552
553 /* DAC Equalizer controls */
554 SOC_SINGLE("DAC EQ Switch", DA9055_DAC_FILTERS4, 7, 1, 0),
555 SOC_SINGLE_TLV("DAC EQ1 Volume", DA9055_DAC_FILTERS2, 0, 0xf, 0,
556 eq_gain_tlv),
557 SOC_SINGLE_TLV("DAC EQ2 Volume", DA9055_DAC_FILTERS2, 4, 0xf, 0,
558 eq_gain_tlv),
559 SOC_SINGLE_TLV("DAC EQ3 Volume", DA9055_DAC_FILTERS3, 0, 0xf, 0,
560 eq_gain_tlv),
561 SOC_SINGLE_TLV("DAC EQ4 Volume", DA9055_DAC_FILTERS3, 4, 0xf, 0,
562 eq_gain_tlv),
563 SOC_SINGLE_TLV("DAC EQ5 Volume", DA9055_DAC_FILTERS4, 0, 0xf, 0,
564 eq_gain_tlv),
565
566 /* High Pass Filter and Voice Mode controls */
567 SOC_SINGLE("ADC HPF Switch", DA9055_ADC_FILTERS1, 7, 1, 0),
568 SOC_ENUM("ADC HPF Cutoff", da9055_adc_hpf_cutoff),
569 SOC_SINGLE("ADC Voice Mode Switch", DA9055_ADC_FILTERS1, 3, 1, 0),
570 SOC_ENUM("ADC Voice Cutoff", da9055_adc_vf_cutoff),
571
572 SOC_SINGLE("DAC HPF Switch", DA9055_DAC_FILTERS1, 7, 1, 0),
573 SOC_ENUM("DAC HPF Cutoff", da9055_dac_hpf_cutoff),
574 SOC_SINGLE("DAC Voice Mode Switch", DA9055_DAC_FILTERS1, 3, 1, 0),
575 SOC_ENUM("DAC Voice Cutoff", da9055_dac_vf_cutoff),
576
577 /* Mute controls */
578 SOC_DOUBLE_R("Mic Switch", DA9055_MIC_L_CTRL,
579 DA9055_MIC_R_CTRL, 6, 1, 0),
580 SOC_DOUBLE_R("Aux Switch", DA9055_AUX_L_CTRL,
581 DA9055_AUX_R_CTRL, 6, 1, 0),
582 SOC_DOUBLE_R("Mixin PGA Switch", DA9055_MIXIN_L_CTRL,
583 DA9055_MIXIN_R_CTRL, 6, 1, 0),
584 SOC_DOUBLE_R("ADC Switch", DA9055_ADC_L_CTRL,
585 DA9055_ADC_R_CTRL, 6, 1, 0),
586 SOC_DOUBLE_R("Headphone Switch", DA9055_HP_L_CTRL,
587 DA9055_HP_R_CTRL, 6, 1, 0),
588 SOC_SINGLE("Lineout Switch", DA9055_LINE_CTRL, 6, 1, 0),
589 SOC_SINGLE("DAC Soft Mute Switch", DA9055_DAC_FILTERS5, 7, 1, 0),
590 SOC_ENUM("DAC Soft Mute Rate", da9055_dac_soft_mute_rate),
591
592 /* Zero Cross controls */
593 SOC_DOUBLE_R("Aux ZC Switch", DA9055_AUX_L_CTRL,
594 DA9055_AUX_R_CTRL, 4, 1, 0),
595 SOC_DOUBLE_R("Mixin PGA ZC Switch", DA9055_MIXIN_L_CTRL,
596 DA9055_MIXIN_R_CTRL, 4, 1, 0),
597 SOC_DOUBLE_R("Headphone ZC Switch", DA9055_HP_L_CTRL,
598 DA9055_HP_R_CTRL, 4, 1, 0),
599 SOC_SINGLE("Lineout ZC Switch", DA9055_LINE_CTRL, 4, 1, 0),
600
601 /* Gain Ramping controls */
602 SOC_DOUBLE_R("Aux Gain Ramping Switch", DA9055_AUX_L_CTRL,
603 DA9055_AUX_R_CTRL, 5, 1, 0),
604 SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA9055_MIXIN_L_CTRL,
605 DA9055_MIXIN_R_CTRL, 5, 1, 0),
606 SOC_DOUBLE_R("ADC Gain Ramping Switch", DA9055_ADC_L_CTRL,
607 DA9055_ADC_R_CTRL, 5, 1, 0),
608 SOC_DOUBLE_R("DAC Gain Ramping Switch", DA9055_DAC_L_CTRL,
609 DA9055_DAC_R_CTRL, 5, 1, 0),
610 SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA9055_HP_L_CTRL,
611 DA9055_HP_R_CTRL, 5, 1, 0),
612 SOC_SINGLE("Lineout Gain Ramping Switch", DA9055_LINE_CTRL, 5, 1, 0),
613 SOC_ENUM("Gain Ramping Rate", da9055_gain_ramping_rate),
614
615 /* DAC Noise Gate controls */
616 SOC_SINGLE("DAC NG Switch", DA9055_DAC_NG_CTRL, 7, 1, 0),
617 SOC_SINGLE("DAC NG ON Threshold", DA9055_DAC_NG_ON_THRESHOLD,
618 0, 0x7, 0),
619 SOC_SINGLE("DAC NG OFF Threshold", DA9055_DAC_NG_OFF_THRESHOLD,
620 0, 0x7, 0),
621 SOC_ENUM("DAC NG Setup Time", da9055_dac_ng_setup_time),
622 SOC_ENUM("DAC NG Rampup Rate", da9055_dac_ng_rampup_rate),
623 SOC_ENUM("DAC NG Rampdown Rate", da9055_dac_ng_rampdown_rate),
624
625 /* DAC Invertion control */
626 SOC_SINGLE("DAC Left Invert", DA9055_DIG_CTRL, 3, 1, 0),
627 SOC_SINGLE("DAC Right Invert", DA9055_DIG_CTRL, 7, 1, 0),
628
629 /* DMIC controls */
630 SOC_DOUBLE_R("DMIC Switch", DA9055_MIXIN_L_SELECT,
631 DA9055_MIXIN_R_SELECT, 7, 1, 0),
632
633 /* ALC Controls */
634 SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0,
635 snd_soc_get_volsw, da9055_put_alc_sw),
636 SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0,
637 snd_soc_get_volsw, da9055_put_alc_sw),
638 SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0),
639 SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL,
640 7, 1, 0),
641 SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL,
642 0, 0x7f, 0),
643 SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN,
644 0, 0x3f, 1, alc_threshold_tlv),
645 SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX,
646 0, 0x3f, 1, alc_threshold_tlv),
647 SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE,
648 0, 0x3f, 1, alc_threshold_tlv),
649 SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS,
650 4, 0xf, 0, alc_gain_tlv),
651 SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS,
652 0, 0xf, 0, alc_gain_tlv),
653 SOC_SINGLE_TLV("ALC Min Analog Gain Volume",
654 DA9055_ALC_ANA_GAIN_LIMITS,
655 0, 0x7, 0, alc_analog_gain_tlv),
656 SOC_SINGLE_TLV("ALC Max Analog Gain Volume",
657 DA9055_ALC_ANA_GAIN_LIMITS,
658 4, 0x7, 0, alc_analog_gain_tlv),
659 SOC_ENUM("ALC Attack Rate", da9055_attack_rate),
660 SOC_ENUM("ALC Release Rate", da9055_release_rate),
661 SOC_ENUM("ALC Hold Time", da9055_hold_time),
662 /*
663 * Rate at which input signal envelope is tracked as the signal gets
664 * larger
665 */
666 SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate),
667 /*
668 * Rate at which input signal envelope is tracked as the signal gets
669 * smaller
670 */
671 SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate),
672};
673
674/* DAPM Controls */
675
676/* Mic PGA Left Source */
677static const struct snd_kcontrol_new da9055_mic_l_mux_controls =
678SOC_DAPM_ENUM("Route", da9055_mic_l_src);
679
680/* Mic PGA Right Source */
681static const struct snd_kcontrol_new da9055_mic_r_mux_controls =
682SOC_DAPM_ENUM("Route", da9055_mic_r_src);
683
684/* In Mixer Left */
685static const struct snd_kcontrol_new da9055_dapm_mixinl_controls[] = {
686 SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXIN_L_SELECT, 0, 1, 0),
687 SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_L_SELECT, 1, 1, 0),
688 SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_L_SELECT, 2, 1, 0),
689};
690
691/* In Mixer Right */
692static const struct snd_kcontrol_new da9055_dapm_mixinr_controls[] = {
693 SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXIN_R_SELECT, 0, 1, 0),
694 SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_R_SELECT, 1, 1, 0),
695 SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_R_SELECT, 2, 1, 0),
696 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXIN_R_SELECT, 3, 1, 0),
697};
698
699/* DAC Left Source */
700static const struct snd_kcontrol_new da9055_dac_l_mux_controls =
701SOC_DAPM_ENUM("Route", da9055_dac_l_src);
702
703/* DAC Right Source */
704static const struct snd_kcontrol_new da9055_dac_r_mux_controls =
705SOC_DAPM_ENUM("Route", da9055_dac_r_src);
706
707/* Out Mixer Left */
708static const struct snd_kcontrol_new da9055_dapm_mixoutl_controls[] = {
709 SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXOUT_L_SELECT, 0, 1, 0),
710 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_L_SELECT, 1, 1, 0),
711 SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_L_SELECT, 2, 1, 0),
712 SOC_DAPM_SINGLE("DAC Left Switch", DA9055_MIXOUT_L_SELECT, 3, 1, 0),
713 SOC_DAPM_SINGLE("Aux Left Invert Switch", DA9055_MIXOUT_L_SELECT,
714 4, 1, 0),
715 SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_L_SELECT,
716 5, 1, 0),
717 SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_L_SELECT,
718 6, 1, 0),
719};
720
721/* Out Mixer Right */
722static const struct snd_kcontrol_new da9055_dapm_mixoutr_controls[] = {
723 SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXOUT_R_SELECT, 0, 1, 0),
724 SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_R_SELECT, 1, 1, 0),
725 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_R_SELECT, 2, 1, 0),
726 SOC_DAPM_SINGLE("DAC Right Switch", DA9055_MIXOUT_R_SELECT, 3, 1, 0),
727 SOC_DAPM_SINGLE("Aux Right Invert Switch", DA9055_MIXOUT_R_SELECT,
728 4, 1, 0),
729 SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_R_SELECT,
730 5, 1, 0),
731 SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_R_SELECT,
732 6, 1, 0),
733};
734
735/* DAPM widgets */
736static const struct snd_soc_dapm_widget da9055_dapm_widgets[] = {
737 /* Input Side */
738
739 /* Input Lines */
740 SND_SOC_DAPM_INPUT("MIC1"),
741 SND_SOC_DAPM_INPUT("MIC2"),
742 SND_SOC_DAPM_INPUT("AUXL"),
743 SND_SOC_DAPM_INPUT("AUXR"),
744
745 /* MUXs for Mic PGA source selection */
746 SND_SOC_DAPM_MUX("Mic Left Source", SND_SOC_NOPM, 0, 0,
747 &da9055_mic_l_mux_controls),
748 SND_SOC_DAPM_MUX("Mic Right Source", SND_SOC_NOPM, 0, 0,
749 &da9055_mic_r_mux_controls),
750
751 /* Input PGAs */
752 SND_SOC_DAPM_PGA("Mic Left", DA9055_MIC_L_CTRL, 7, 0, NULL, 0),
753 SND_SOC_DAPM_PGA("Mic Right", DA9055_MIC_R_CTRL, 7, 0, NULL, 0),
754 SND_SOC_DAPM_PGA("Aux Left", DA9055_AUX_L_CTRL, 7, 0, NULL, 0),
755 SND_SOC_DAPM_PGA("Aux Right", DA9055_AUX_R_CTRL, 7, 0, NULL, 0),
756 SND_SOC_DAPM_PGA("MIXIN Left", DA9055_MIXIN_L_CTRL, 7, 0, NULL, 0),
757 SND_SOC_DAPM_PGA("MIXIN Right", DA9055_MIXIN_R_CTRL, 7, 0, NULL, 0),
758
759 SND_SOC_DAPM_SUPPLY("Mic Bias", DA9055_MIC_BIAS_CTRL, 7, 0, NULL, 0),
760 SND_SOC_DAPM_SUPPLY("AIF", DA9055_AIF_CTRL, 7, 0, NULL, 0),
761 SND_SOC_DAPM_SUPPLY("Charge Pump", DA9055_CP_CTRL, 7, 0, NULL, 0),
762
763 /* Input Mixers */
764 SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0,
765 &da9055_dapm_mixinl_controls[0],
766 ARRAY_SIZE(da9055_dapm_mixinl_controls)),
767 SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0,
768 &da9055_dapm_mixinr_controls[0],
769 ARRAY_SIZE(da9055_dapm_mixinr_controls)),
770
771 /* ADCs */
772 SND_SOC_DAPM_ADC("ADC Left", "Capture", DA9055_ADC_L_CTRL, 7, 0),
773 SND_SOC_DAPM_ADC("ADC Right", "Capture", DA9055_ADC_R_CTRL, 7, 0),
774
775 /* Output Side */
776
777 /* MUXs for DAC source selection */
778 SND_SOC_DAPM_MUX("DAC Left Source", SND_SOC_NOPM, 0, 0,
779 &da9055_dac_l_mux_controls),
780 SND_SOC_DAPM_MUX("DAC Right Source", SND_SOC_NOPM, 0, 0,
781 &da9055_dac_r_mux_controls),
782
783 /* AIF input */
784 SND_SOC_DAPM_AIF_IN("AIFIN Left", "Playback", 0, SND_SOC_NOPM, 0, 0),
785 SND_SOC_DAPM_AIF_IN("AIFIN Right", "Playback", 0, SND_SOC_NOPM, 0, 0),
786
787 /* DACs */
788 SND_SOC_DAPM_DAC("DAC Left", "Playback", DA9055_DAC_L_CTRL, 7, 0),
789 SND_SOC_DAPM_DAC("DAC Right", "Playback", DA9055_DAC_R_CTRL, 7, 0),
790
791 /* Output Mixers */
792 SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0,
793 &da9055_dapm_mixoutl_controls[0],
794 ARRAY_SIZE(da9055_dapm_mixoutl_controls)),
795 SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0,
796 &da9055_dapm_mixoutr_controls[0],
797 ARRAY_SIZE(da9055_dapm_mixoutr_controls)),
798
799 /* Output PGAs */
800 SND_SOC_DAPM_PGA("MIXOUT Left", DA9055_MIXOUT_L_CTRL, 7, 0, NULL, 0),
801 SND_SOC_DAPM_PGA("MIXOUT Right", DA9055_MIXOUT_R_CTRL, 7, 0, NULL, 0),
802 SND_SOC_DAPM_PGA("Lineout", DA9055_LINE_CTRL, 7, 0, NULL, 0),
803 SND_SOC_DAPM_PGA("Headphone Left", DA9055_HP_L_CTRL, 7, 0, NULL, 0),
804 SND_SOC_DAPM_PGA("Headphone Right", DA9055_HP_R_CTRL, 7, 0, NULL, 0),
805
806 /* Output Lines */
807 SND_SOC_DAPM_OUTPUT("HPL"),
808 SND_SOC_DAPM_OUTPUT("HPR"),
809 SND_SOC_DAPM_OUTPUT("LINE"),
810};
811
812/* DAPM audio route definition */
813static const struct snd_soc_dapm_route da9055_audio_map[] = {
814 /* Dest Connecting Widget source */
815
816 /* Input path */
817 {"Mic Left Source", "MIC1_P_N", "MIC1"},
818 {"Mic Left Source", "MIC1_P", "MIC1"},
819 {"Mic Left Source", "MIC1_N", "MIC1"},
820 {"Mic Left Source", "MIC2_L", "MIC2"},
821
822 {"Mic Right Source", "MIC2_R_L", "MIC2"},
823 {"Mic Right Source", "MIC2_R", "MIC2"},
824 {"Mic Right Source", "MIC2_L", "MIC2"},
825
826 {"Mic Left", NULL, "Mic Left Source"},
827 {"Mic Right", NULL, "Mic Right Source"},
828
829 {"Aux Left", NULL, "AUXL"},
830 {"Aux Right", NULL, "AUXR"},
831
832 {"In Mixer Left", "Mic Left Switch", "Mic Left"},
833 {"In Mixer Left", "Mic Right Switch", "Mic Right"},
834 {"In Mixer Left", "Aux Left Switch", "Aux Left"},
835
836 {"In Mixer Right", "Mic Right Switch", "Mic Right"},
837 {"In Mixer Right", "Mic Left Switch", "Mic Left"},
838 {"In Mixer Right", "Aux Right Switch", "Aux Right"},
839 {"In Mixer Right", "Mixin Left Switch", "MIXIN Left"},
840
841 {"MIXIN Left", NULL, "In Mixer Left"},
842 {"ADC Left", NULL, "MIXIN Left"},
843
844 {"MIXIN Right", NULL, "In Mixer Right"},
845 {"ADC Right", NULL, "MIXIN Right"},
846
847 {"ADC Left", NULL, "AIF"},
848 {"ADC Right", NULL, "AIF"},
849
850 /* Output path */
851 {"AIFIN Left", NULL, "AIF"},
852 {"AIFIN Right", NULL, "AIF"},
853
854 {"DAC Left Source", "ADC output left", "ADC Left"},
855 {"DAC Left Source", "ADC output right", "ADC Right"},
856 {"DAC Left Source", "AIF input left", "AIFIN Left"},
857 {"DAC Left Source", "AIF input right", "AIFIN Right"},
858
859 {"DAC Right Source", "ADC output left", "ADC Left"},
860 {"DAC Right Source", "ADC output right", "ADC Right"},
861 {"DAC Right Source", "AIF input left", "AIFIN Left"},
862 {"DAC Right Source", "AIF input right", "AIFIN Right"},
863
864 {"DAC Left", NULL, "DAC Left Source"},
865 {"DAC Right", NULL, "DAC Right Source"},
866
867 {"Out Mixer Left", "Aux Left Switch", "Aux Left"},
868 {"Out Mixer Left", "Mixin Left Switch", "MIXIN Left"},
869 {"Out Mixer Left", "Mixin Right Switch", "MIXIN Right"},
870 {"Out Mixer Left", "Aux Left Invert Switch", "Aux Left"},
871 {"Out Mixer Left", "Mixin Left Invert Switch", "MIXIN Left"},
872 {"Out Mixer Left", "Mixin Right Invert Switch", "MIXIN Right"},
873 {"Out Mixer Left", "DAC Left Switch", "DAC Left"},
874
875 {"Out Mixer Right", "Aux Right Switch", "Aux Right"},
876 {"Out Mixer Right", "Mixin Right Switch", "MIXIN Right"},
877 {"Out Mixer Right", "Mixin Left Switch", "MIXIN Left"},
878 {"Out Mixer Right", "Aux Right Invert Switch", "Aux Right"},
879 {"Out Mixer Right", "Mixin Right Invert Switch", "MIXIN Right"},
880 {"Out Mixer Right", "Mixin Left Invert Switch", "MIXIN Left"},
881 {"Out Mixer Right", "DAC Right Switch", "DAC Right"},
882
883 {"MIXOUT Left", NULL, "Out Mixer Left"},
884 {"Headphone Left", NULL, "MIXOUT Left"},
885 {"Headphone Left", NULL, "Charge Pump"},
886 {"HPL", NULL, "Headphone Left"},
887
888 {"MIXOUT Right", NULL, "Out Mixer Right"},
889 {"Headphone Right", NULL, "MIXOUT Right"},
890 {"Headphone Right", NULL, "Charge Pump"},
891 {"HPR", NULL, "Headphone Right"},
892
893 {"MIXOUT Right", NULL, "Out Mixer Right"},
894 {"Lineout", NULL, "MIXOUT Right"},
895 {"LINE", NULL, "Lineout"},
896};
897
898/* Codec private data */
899struct da9055_priv {
900 struct regmap *regmap;
901 unsigned int mclk_rate;
902 int master;
903 struct da9055_platform_data *pdata;
904};
905
906static struct reg_default da9055_reg_defaults[] = {
907 { 0x21, 0x10 },
908 { 0x22, 0x0A },
909 { 0x23, 0x00 },
910 { 0x24, 0x00 },
911 { 0x25, 0x00 },
912 { 0x26, 0x00 },
913 { 0x27, 0x0C },
914 { 0x28, 0x01 },
915 { 0x29, 0x08 },
916 { 0x2A, 0x32 },
917 { 0x2B, 0x00 },
918 { 0x30, 0x35 },
919 { 0x31, 0x35 },
920 { 0x32, 0x00 },
921 { 0x33, 0x00 },
922 { 0x34, 0x03 },
923 { 0x35, 0x03 },
924 { 0x36, 0x6F },
925 { 0x37, 0x6F },
926 { 0x38, 0x80 },
927 { 0x39, 0x01 },
928 { 0x3A, 0x01 },
929 { 0x40, 0x00 },
930 { 0x41, 0x88 },
931 { 0x42, 0x88 },
932 { 0x43, 0x08 },
933 { 0x44, 0x80 },
934 { 0x45, 0x6F },
935 { 0x46, 0x6F },
936 { 0x47, 0x61 },
937 { 0x48, 0x35 },
938 { 0x49, 0x35 },
939 { 0x4A, 0x35 },
940 { 0x4B, 0x00 },
941 { 0x4C, 0x00 },
942 { 0x60, 0x44 },
943 { 0x61, 0x44 },
944 { 0x62, 0x00 },
945 { 0x63, 0x40 },
946 { 0x64, 0x40 },
947 { 0x65, 0x40 },
948 { 0x66, 0x40 },
949 { 0x67, 0x40 },
950 { 0x68, 0x40 },
951 { 0x69, 0x48 },
952 { 0x6A, 0x40 },
953 { 0x6B, 0x41 },
954 { 0x6C, 0x40 },
955 { 0x6D, 0x40 },
956 { 0x6E, 0x10 },
957 { 0x6F, 0x10 },
958 { 0x90, 0x80 },
959 { 0x92, 0x02 },
960 { 0x93, 0x00 },
961 { 0x99, 0x00 },
962 { 0x9A, 0x00 },
963 { 0x9B, 0x00 },
964 { 0x9C, 0x3F },
965 { 0x9D, 0x00 },
966 { 0x9E, 0x3F },
967 { 0x9F, 0xFF },
968 { 0xA0, 0x71 },
969 { 0xA1, 0x00 },
970 { 0xA2, 0x00 },
971 { 0xA6, 0x00 },
972 { 0xA7, 0x00 },
973 { 0xAB, 0x00 },
974 { 0xAC, 0x00 },
975 { 0xAD, 0x00 },
976 { 0xAF, 0x08 },
977 { 0xB0, 0x00 },
978 { 0xB1, 0x00 },
979 { 0xB2, 0x00 },
980};
981
982static bool da9055_volatile_register(struct device *dev,
983 unsigned int reg)
984{
985 switch (reg) {
986 case DA9055_STATUS1:
987 case DA9055_PLL_STATUS:
988 case DA9055_AUX_L_GAIN_STATUS:
989 case DA9055_AUX_R_GAIN_STATUS:
990 case DA9055_MIC_L_GAIN_STATUS:
991 case DA9055_MIC_R_GAIN_STATUS:
992 case DA9055_MIXIN_L_GAIN_STATUS:
993 case DA9055_MIXIN_R_GAIN_STATUS:
994 case DA9055_ADC_L_GAIN_STATUS:
995 case DA9055_ADC_R_GAIN_STATUS:
996 case DA9055_DAC_L_GAIN_STATUS:
997 case DA9055_DAC_R_GAIN_STATUS:
998 case DA9055_HP_L_GAIN_STATUS:
999 case DA9055_HP_R_GAIN_STATUS:
1000 case DA9055_LINE_GAIN_STATUS:
1001 case DA9055_ALC_CIC_OP_LVL_DATA:
1002 return 1;
1003 default:
1004 return 0;
1005 }
1006}
1007
1008/* Set DAI word length */
1009static int da9055_hw_params(struct snd_pcm_substream *substream,
1010 struct snd_pcm_hw_params *params,
1011 struct snd_soc_dai *dai)
1012{
1013 struct snd_soc_codec *codec = dai->codec;
1014 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1015 u8 aif_ctrl, fs;
1016 u32 sysclk;
1017
1018 switch (params_format(params)) {
1019 case SNDRV_PCM_FORMAT_S16_LE:
1020 aif_ctrl = DA9055_AIF_WORD_S16_LE;
1021 break;
1022 case SNDRV_PCM_FORMAT_S20_3LE:
1023 aif_ctrl = DA9055_AIF_WORD_S20_3LE;
1024 break;
1025 case SNDRV_PCM_FORMAT_S24_LE:
1026 aif_ctrl = DA9055_AIF_WORD_S24_LE;
1027 break;
1028 case SNDRV_PCM_FORMAT_S32_LE:
1029 aif_ctrl = DA9055_AIF_WORD_S32_LE;
1030 break;
1031 default:
1032 return -EINVAL;
1033 }
1034
1035 /* Set AIF format */
1036 snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_WORD_LENGTH_MASK,
1037 aif_ctrl);
1038
1039 switch (params_rate(params)) {
1040 case 8000:
1041 fs = DA9055_SR_8000;
1042 sysclk = 3072000;
1043 break;
1044 case 11025:
1045 fs = DA9055_SR_11025;
1046 sysclk = 2822400;
1047 break;
1048 case 12000:
1049 fs = DA9055_SR_12000;
1050 sysclk = 3072000;
1051 break;
1052 case 16000:
1053 fs = DA9055_SR_16000;
1054 sysclk = 3072000;
1055 break;
1056 case 22050:
1057 fs = DA9055_SR_22050;
1058 sysclk = 2822400;
1059 break;
1060 case 32000:
1061 fs = DA9055_SR_32000;
1062 sysclk = 3072000;
1063 break;
1064 case 44100:
1065 fs = DA9055_SR_44100;
1066 sysclk = 2822400;
1067 break;
1068 case 48000:
1069 fs = DA9055_SR_48000;
1070 sysclk = 3072000;
1071 break;
1072 case 88200:
1073 fs = DA9055_SR_88200;
1074 sysclk = 2822400;
1075 break;
1076 case 96000:
1077 fs = DA9055_SR_96000;
1078 sysclk = 3072000;
1079 break;
1080 default:
1081 return -EINVAL;
1082 }
1083
1084 if (da9055->mclk_rate) {
1085 /* PLL Mode, Write actual FS */
1086 snd_soc_write(codec, DA9055_SR, fs);
1087 } else {
1088 /*
1089 * Non-PLL Mode
1090 * When PLL is bypassed, chip assumes constant MCLK of
1091 * 12.288MHz and uses sample rate value to divide this MCLK
1092 * to derive its sys clk. As sys clk has to be 256 * Fs, we
1093 * need to write constant sample rate i.e. 48KHz.
1094 */
1095 snd_soc_write(codec, DA9055_SR, DA9055_SR_48000);
1096 }
1097
1098 if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) {
1099 /* PLL Mode */
1100 if (!da9055->master) {
1101 /* PLL slave mode, enable PLL and also SRM */
1102 snd_soc_update_bits(codec, DA9055_PLL_CTRL,
1103 DA9055_PLL_EN | DA9055_PLL_SRM_EN,
1104 DA9055_PLL_EN | DA9055_PLL_SRM_EN);
1105 } else {
1106 /* PLL master mode, only enable PLL */
1107 snd_soc_update_bits(codec, DA9055_PLL_CTRL,
1108 DA9055_PLL_EN, DA9055_PLL_EN);
1109 }
1110 } else {
1111 /* Non PLL Mode, disable PLL */
1112 snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1113 }
1114
1115 return 0;
1116}
1117
1118/* Set DAI mode and Format */
1119static int da9055_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1120{
1121 struct snd_soc_codec *codec = codec_dai->codec;
1122 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1123 u8 aif_clk_mode, aif_ctrl, mode;
1124
1125 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1126 case SND_SOC_DAIFMT_CBM_CFM:
1127 /* DA9055 in I2S Master Mode */
1128 mode = 1;
1129 aif_clk_mode = DA9055_AIF_CLK_EN_MASTER_MODE;
1130 break;
1131 case SND_SOC_DAIFMT_CBS_CFS:
1132 /* DA9055 in I2S Slave Mode */
1133 mode = 0;
1134 aif_clk_mode = DA9055_AIF_CLK_EN_SLAVE_MODE;
1135 break;
1136 default:
1137 return -EINVAL;
1138 }
1139
1140 /* Don't allow change of mode if PLL is enabled */
1141 if ((snd_soc_read(codec, DA9055_PLL_CTRL) & DA9055_PLL_EN) &&
1142 (da9055->master != mode))
1143 return -EINVAL;
1144
1145 da9055->master = mode;
1146
1147 /* Only I2S is supported */
1148 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1149 case SND_SOC_DAIFMT_I2S:
1150 aif_ctrl = DA9055_AIF_FORMAT_I2S_MODE;
1151 break;
1152 case SND_SOC_DAIFMT_LEFT_J:
1153 aif_ctrl = DA9055_AIF_FORMAT_LEFT_J;
1154 break;
1155 case SND_SOC_DAIFMT_RIGHT_J:
1156 aif_ctrl = DA9055_AIF_FORMAT_RIGHT_J;
1157 break;
1158 default:
1159 return -EINVAL;
1160 }
1161
1162 /* By default only 32 BCLK per WCLK is supported */
1163 aif_clk_mode |= DA9055_AIF_BCLKS_PER_WCLK_32;
1164
1165 snd_soc_update_bits(codec, DA9055_AIF_CLK_MODE,
1166 (DA9055_AIF_CLK_MODE_MASK | DA9055_AIF_BCLK_MASK),
1167 aif_clk_mode);
1168 snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_FORMAT_MASK,
1169 aif_ctrl);
1170 return 0;
1171}
1172
1173static int da9055_mute(struct snd_soc_dai *dai, int mute)
1174{
1175 struct snd_soc_codec *codec = dai->codec;
1176
1177 if (mute) {
1178 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL,
1179 DA9055_DAC_L_MUTE_EN, DA9055_DAC_L_MUTE_EN);
1180 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL,
1181 DA9055_DAC_R_MUTE_EN, DA9055_DAC_R_MUTE_EN);
1182 } else {
1183 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL,
1184 DA9055_DAC_L_MUTE_EN, 0);
1185 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL,
1186 DA9055_DAC_R_MUTE_EN, 0);
1187 }
1188
1189 return 0;
1190}
1191
1192#define DA9055_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1193 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1194
1195static int da9055_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1196 int clk_id, unsigned int freq, int dir)
1197{
1198 struct snd_soc_codec *codec = codec_dai->codec;
1199 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1200
1201 switch (clk_id) {
1202 case DA9055_CLKSRC_MCLK:
1203 switch (freq) {
1204 case 11289600:
1205 case 12000000:
1206 case 12288000:
1207 case 13000000:
1208 case 13500000:
1209 case 14400000:
1210 case 19200000:
1211 case 19680000:
1212 case 19800000:
1213 da9055->mclk_rate = freq;
1214 return 0;
1215 default:
1216 dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
1217 freq);
1218 return -EINVAL;
1219 }
1220 break;
1221 default:
1222 dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
1223 return -EINVAL;
1224 }
1225}
1226
1227/*
1228 * da9055_set_dai_pll : Configure the codec PLL
1229 * @param codec_dai : Pointer to codec DAI
1230 * @param pll_id : da9055 has only one pll, so pll_id is always zero
1231 * @param fref : Input MCLK frequency
1232 * @param fout : FsDM value
1233 * @return int : Zero for success, negative error code for error
1234 *
1235 * Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz,
1236 * 13MHz, 13.5MHz, 14.4MHz, 19.2MHz, 19.6MHz and 19.8MHz
1237 */
1238static int da9055_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1239 int source, unsigned int fref, unsigned int fout)
1240{
1241 struct snd_soc_codec *codec = codec_dai->codec;
1242 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1243
1244 u8 pll_frac_top, pll_frac_bot, pll_integer, cnt;
1245
1246 /* Disable PLL before setting the divisors */
1247 snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1248
1249 /* In slave mode, there is only one set of divisors */
1250 if (!da9055->master && (fout != 2822400))
1251 goto pll_err;
1252
1253 /* Search pll div array for correct divisors */
1254 for (cnt = 0; cnt < ARRAY_SIZE(da9055_pll_div); cnt++) {
1255 /* Check fref, mode and fout */
1256 if ((fref == da9055_pll_div[cnt].fref) &&
1257 (da9055->master == da9055_pll_div[cnt].mode) &&
1258 (fout == da9055_pll_div[cnt].fout)) {
1259 /* All match, pick up divisors */
1260 pll_frac_top = da9055_pll_div[cnt].frac_top;
1261 pll_frac_bot = da9055_pll_div[cnt].frac_bot;
1262 pll_integer = da9055_pll_div[cnt].integer;
1263 break;
1264 }
1265 }
1266 if (cnt >= ARRAY_SIZE(da9055_pll_div))
1267 goto pll_err;
1268
1269 /* Write PLL dividers */
1270 snd_soc_write(codec, DA9055_PLL_FRAC_TOP, pll_frac_top);
1271 snd_soc_write(codec, DA9055_PLL_FRAC_BOT, pll_frac_bot);
1272 snd_soc_write(codec, DA9055_PLL_INTEGER, pll_integer);
1273
1274 return 0;
1275pll_err:
1276 dev_err(codec_dai->dev, "Error in setting up PLL\n");
1277 return -EINVAL;
1278}
1279
1280/* DAI operations */
1281static const struct snd_soc_dai_ops da9055_dai_ops = {
1282 .hw_params = da9055_hw_params,
1283 .set_fmt = da9055_set_dai_fmt,
1284 .set_sysclk = da9055_set_dai_sysclk,
1285 .set_pll = da9055_set_dai_pll,
1286 .digital_mute = da9055_mute,
1287};
1288
1289static struct snd_soc_dai_driver da9055_dai = {
1290 .name = "da9055-hifi",
1291 /* Playback Capabilities */
1292 .playback = {
1293 .stream_name = "Playback",
1294 .channels_min = 1,
1295 .channels_max = 2,
1296 .rates = SNDRV_PCM_RATE_8000_96000,
1297 .formats = DA9055_FORMATS,
1298 },
1299 /* Capture Capabilities */
1300 .capture = {
1301 .stream_name = "Capture",
1302 .channels_min = 1,
1303 .channels_max = 2,
1304 .rates = SNDRV_PCM_RATE_8000_96000,
1305 .formats = DA9055_FORMATS,
1306 },
1307 .ops = &da9055_dai_ops,
1308 .symmetric_rates = 1,
1309};
1310
1311static int da9055_set_bias_level(struct snd_soc_codec *codec,
1312 enum snd_soc_bias_level level)
1313{
1314 switch (level) {
1315 case SND_SOC_BIAS_ON:
1316 case SND_SOC_BIAS_PREPARE:
1317 break;
1318 case SND_SOC_BIAS_STANDBY:
1319 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1320 /* Enable VMID reference & master bias */
1321 snd_soc_update_bits(codec, DA9055_REFERENCES,
1322 DA9055_VMID_EN | DA9055_BIAS_EN,
1323 DA9055_VMID_EN | DA9055_BIAS_EN);
1324 }
1325 break;
1326 case SND_SOC_BIAS_OFF:
1327 /* Disable VMID reference & master bias */
1328 snd_soc_update_bits(codec, DA9055_REFERENCES,
1329 DA9055_VMID_EN | DA9055_BIAS_EN, 0);
1330 break;
1331 }
1332 codec->dapm.bias_level = level;
1333 return 0;
1334}
1335
1336static int da9055_probe(struct snd_soc_codec *codec)
1337{
1338 int ret;
1339 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1340
1341 codec->control_data = da9055->regmap;
1342 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1343 if (ret < 0) {
1344 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1345 return ret;
1346 }
1347
1348 /* Enable all Gain Ramps */
1349 snd_soc_update_bits(codec, DA9055_AUX_L_CTRL,
1350 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1351 snd_soc_update_bits(codec, DA9055_AUX_R_CTRL,
1352 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1353 snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL,
1354 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1355 snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL,
1356 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1357 snd_soc_update_bits(codec, DA9055_ADC_L_CTRL,
1358 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1359 snd_soc_update_bits(codec, DA9055_ADC_R_CTRL,
1360 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1361 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL,
1362 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1363 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL,
1364 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1365 snd_soc_update_bits(codec, DA9055_HP_L_CTRL,
1366 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1367 snd_soc_update_bits(codec, DA9055_HP_R_CTRL,
1368 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1369 snd_soc_update_bits(codec, DA9055_LINE_CTRL,
1370 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1371
1372 /*
1373 * There are two separate control bits for input and output mixers as
1374 * well as headphone and line outs.
1375 * One to enable corresponding amplifier and other to enable its
1376 * output. As amplifier bits are related to power control, they are
1377 * being managed by DAPM while other (non power related) bits are
1378 * enabled here
1379 */
1380 snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL,
1381 DA9055_MIXIN_L_MIX_EN, DA9055_MIXIN_L_MIX_EN);
1382 snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL,
1383 DA9055_MIXIN_R_MIX_EN, DA9055_MIXIN_R_MIX_EN);
1384
1385 snd_soc_update_bits(codec, DA9055_MIXOUT_L_CTRL,
1386 DA9055_MIXOUT_L_MIX_EN, DA9055_MIXOUT_L_MIX_EN);
1387 snd_soc_update_bits(codec, DA9055_MIXOUT_R_CTRL,
1388 DA9055_MIXOUT_R_MIX_EN, DA9055_MIXOUT_R_MIX_EN);
1389
1390 snd_soc_update_bits(codec, DA9055_HP_L_CTRL,
1391 DA9055_HP_L_AMP_OE, DA9055_HP_L_AMP_OE);
1392 snd_soc_update_bits(codec, DA9055_HP_R_CTRL,
1393 DA9055_HP_R_AMP_OE, DA9055_HP_R_AMP_OE);
1394
1395 snd_soc_update_bits(codec, DA9055_LINE_CTRL,
1396 DA9055_LINE_AMP_OE, DA9055_LINE_AMP_OE);
1397
1398 /* Set this as per your system configuration */
1399 snd_soc_write(codec, DA9055_PLL_CTRL, DA9055_PLL_INDIV_10_20_MHZ);
1400
1401 /* Set platform data values */
1402 if (da9055->pdata) {
1403 /* set mic bias source */
1404 if (da9055->pdata->micbias_source) {
1405 snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT,
1406 DA9055_MICBIAS2_EN,
1407 DA9055_MICBIAS2_EN);
1408 } else {
1409 snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT,
1410 DA9055_MICBIAS2_EN, 0);
1411 }
1412 /* set mic bias voltage */
1413 switch (da9055->pdata->micbias) {
1414 case DA9055_MICBIAS_2_2V:
1415 case DA9055_MICBIAS_2_1V:
1416 case DA9055_MICBIAS_1_8V:
1417 case DA9055_MICBIAS_1_6V:
1418 snd_soc_update_bits(codec, DA9055_MIC_CONFIG,
1419 DA9055_MICBIAS_LEVEL_MASK,
1420 (da9055->pdata->micbias) << 4);
1421 break;
1422 }
1423 }
1424 return 0;
1425}
1426
1427static struct snd_soc_codec_driver soc_codec_dev_da9055 = {
1428 .probe = da9055_probe,
1429 .set_bias_level = da9055_set_bias_level,
1430
1431 .controls = da9055_snd_controls,
1432 .num_controls = ARRAY_SIZE(da9055_snd_controls),
1433
1434 .dapm_widgets = da9055_dapm_widgets,
1435 .num_dapm_widgets = ARRAY_SIZE(da9055_dapm_widgets),
1436 .dapm_routes = da9055_audio_map,
1437 .num_dapm_routes = ARRAY_SIZE(da9055_audio_map),
1438};
1439
1440static const struct regmap_config da9055_regmap_config = {
1441 .reg_bits = 8,
1442 .val_bits = 8,
1443
1444 .reg_defaults = da9055_reg_defaults,
1445 .num_reg_defaults = ARRAY_SIZE(da9055_reg_defaults),
1446 .volatile_reg = da9055_volatile_register,
1447 .cache_type = REGCACHE_RBTREE,
1448};
1449
1450static int __devinit da9055_i2c_probe(struct i2c_client *i2c,
1451 const struct i2c_device_id *id)
1452{
1453 struct da9055_priv *da9055;
1454 struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev);
1455 int ret;
1456
1457 da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv),
1458 GFP_KERNEL);
1459 if (!da9055)
1460 return -ENOMEM;
1461
1462 if (pdata)
1463 da9055->pdata = pdata;
1464
1465 i2c_set_clientdata(i2c, da9055);
1466
1467 da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);
1468 if (IS_ERR(da9055->regmap)) {
1469 ret = PTR_ERR(da9055->regmap);
1470 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1471 return ret;
1472 }
1473
1474 ret = snd_soc_register_codec(&i2c->dev,
1475 &soc_codec_dev_da9055, &da9055_dai, 1);
1476 if (ret < 0) {
1477 dev_err(&i2c->dev, "Failed to register da9055 codec: %d\n",
1478 ret);
1479 }
1480 return ret;
1481}
1482
1483static int __devexit da9055_remove(struct i2c_client *client)
1484{
1485 snd_soc_unregister_codec(&client->dev);
1486 return 0;
1487}
1488
1489static const struct i2c_device_id da9055_i2c_id[] = {
1490 { "da9055", 0 },
1491 { }
1492};
1493MODULE_DEVICE_TABLE(i2c, da9055_i2c_id);
1494
1495/* I2C codec control layer */
1496static struct i2c_driver da9055_i2c_driver = {
1497 .driver = {
1498 .name = "da9055",
1499 .owner = THIS_MODULE,
1500 },
1501 .probe = da9055_i2c_probe,
1502 .remove = __devexit_p(da9055_remove),
1503 .id_table = da9055_i2c_id,
1504};
1505
1506module_i2c_driver(da9055_i2c_driver);
1507
1508MODULE_DESCRIPTION("ASoC DA9055 Codec driver");
1509MODULE_AUTHOR("David Chen, Ashish Chavan");
1510MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 05:00:13 -0500