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authorJonas Andersson <jonas@microbit.se>2009-03-04 02:24:26 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-03-04 09:47:39 -0500
commit86027ae78c9294bb450b76eec28cfb431a8fb3ee (patch)
tree4e2634b23e5f050f0065ad4ff2a6845409f1e532 /sound/soc/atmel
parentec67624d33d5639bcc6ee6918cb1fc0bd1bac3a8 (diff)
ASoC: wm8510 pll settings
When setting WM8510_MCLKDIV the pll was turned off. When setting pll frequency you got twice the expected freq, because the code calculated with postscaler of 8, but the hardware divide by 4. Signed-off-by: Jonas Andersson <jonas@microbit.se> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/atmel')
-rw-r--r--sound/soc/atmel/playpaq_wm8510.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/sound/soc/atmel/playpaq_wm8510.c b/sound/soc/atmel/playpaq_wm8510.c
index 43dd8cee83c6..70657534e6b1 100644
--- a/sound/soc/atmel/playpaq_wm8510.c
+++ b/sound/soc/atmel/playpaq_wm8510.c
@@ -164,38 +164,38 @@ static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
164 */ 164 */
165 switch (params_rate(params)) { 165 switch (params_rate(params)) {
166 case 48000: 166 case 48000:
167 pll_out = 12288000; 167 pll_out = 24576000;
168 mclk_div = WM8510_MCLKDIV_1; 168 mclk_div = WM8510_MCLKDIV_2;
169 bclk = WM8510_BCLKDIV_8; 169 bclk = WM8510_BCLKDIV_8;
170 break; 170 break;
171 171
172 case 44100: 172 case 44100:
173 pll_out = 11289600; 173 pll_out = 22579200;
174 mclk_div = WM8510_MCLKDIV_1; 174 mclk_div = WM8510_MCLKDIV_2;
175 bclk = WM8510_BCLKDIV_8; 175 bclk = WM8510_BCLKDIV_8;
176 break; 176 break;
177 177
178 case 22050: 178 case 22050:
179 pll_out = 11289600; 179 pll_out = 22579200;
180 mclk_div = WM8510_MCLKDIV_2; 180 mclk_div = WM8510_MCLKDIV_4;
181 bclk = WM8510_BCLKDIV_8; 181 bclk = WM8510_BCLKDIV_8;
182 break; 182 break;
183 183
184 case 16000: 184 case 16000:
185 pll_out = 12288000; 185 pll_out = 24576000;
186 mclk_div = WM8510_MCLKDIV_3; 186 mclk_div = WM8510_MCLKDIV_6;
187 bclk = WM8510_BCLKDIV_8; 187 bclk = WM8510_BCLKDIV_8;
188 break; 188 break;
189 189
190 case 11025: 190 case 11025:
191 pll_out = 11289600; 191 pll_out = 22579200;
192 mclk_div = WM8510_MCLKDIV_4; 192 mclk_div = WM8510_MCLKDIV_8;
193 bclk = WM8510_BCLKDIV_8; 193 bclk = WM8510_BCLKDIV_8;
194 break; 194 break;
195 195
196 case 8000: 196 case 8000:
197 pll_out = 12288000; 197 pll_out = 24576000;
198 mclk_div = WM8510_MCLKDIV_6; 198 mclk_div = WM8510_MCLKDIV_12;
199 bclk = WM8510_BCLKDIV_8; 199 bclk = WM8510_BCLKDIV_8;
200 break; 200 break;
201 201