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authorTakashi Iwai <tiwai@suse.de>2014-07-01 05:24:06 -0400
committerTakashi Iwai <tiwai@suse.de>2014-07-01 05:24:06 -0400
commit84526820c48ea7d8df40d661e46e41a04d8f3027 (patch)
tree1a01fe2936391677fee611f3bc334bd1bb0cf70d /sound/pci
parente8750940ce345bf15fa0756810ae9ac491e9e352 (diff)
parentfb1d8ac29971fc48144abe5bc760f9eb3e537b9f (diff)
Merge branch 'topic/hda-cleanup' into for-next
Diffstat (limited to 'sound/pci')
-rw-r--r--sound/pci/hda/hda_auto_parser.c2
-rw-r--r--sound/pci/hda/hda_controller.c200
-rw-r--r--sound/pci/hda/hda_controller.h9
-rw-r--r--sound/pci/hda/hda_intel.c321
-rw-r--r--sound/pci/hda/hda_priv.h253
-rw-r--r--sound/pci/hda/hda_tegra.c31
6 files changed, 422 insertions, 394 deletions
diff --git a/sound/pci/hda/hda_auto_parser.c b/sound/pci/hda/hda_auto_parser.c
index dabe41975a9d..a9790198aa17 100644
--- a/sound/pci/hda/hda_auto_parser.c
+++ b/sound/pci/hda/hda_auto_parser.c
@@ -17,8 +17,6 @@
17#include "hda_local.h" 17#include "hda_local.h"
18#include "hda_auto_parser.h" 18#include "hda_auto_parser.h"
19 19
20#define SFX "hda_codec: "
21
22/* 20/*
23 * Helper for automatic pin configuration 21 * Helper for automatic pin configuration
24 */ 22 */
diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c
index 875e0ebf56eb..06f39c126ba4 100644
--- a/sound/pci/hda/hda_controller.c
+++ b/sound/pci/hda/hda_controller.c
@@ -27,6 +27,7 @@
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/pm_runtime.h> 28#include <linux/pm_runtime.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/reboot.h>
30#include <sound/core.h> 31#include <sound/core.h>
31#include <sound/initval.h> 32#include <sound/initval.h>
32#include "hda_priv.h" 33#include "hda_priv.h"
@@ -152,11 +153,11 @@ static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
152 upper_32_bits(azx_dev->bdl.addr)); 153 upper_32_bits(azx_dev->bdl.addr));
153 154
154 /* enable the position buffer */ 155 /* enable the position buffer */
155 if (chip->position_fix[0] != POS_FIX_LPIB || 156 if (chip->get_position[0] != azx_get_pos_lpib ||
156 chip->position_fix[1] != POS_FIX_LPIB) { 157 chip->get_position[1] != azx_get_pos_lpib) {
157 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) 158 if (!(azx_readl(chip, DPLBASE) & AZX_DPLBASE_ENABLE))
158 azx_writel(chip, DPLBASE, 159 azx_writel(chip, DPLBASE,
159 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 160 (u32)chip->posbuf.addr | AZX_DPLBASE_ENABLE);
160 } 161 }
161 162
162 /* set the interrupt enable bits in the descriptor control register */ 163 /* set the interrupt enable bits in the descriptor control register */
@@ -673,125 +674,40 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
673 return 0; 674 return 0;
674} 675}
675 676
676/* get the current DMA position with correction on VIA chips */ 677unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
677static unsigned int azx_via_get_position(struct azx *chip,
678 struct azx_dev *azx_dev)
679{ 678{
680 unsigned int link_pos, mini_pos, bound_pos; 679 return azx_sd_readl(chip, azx_dev, SD_LPIB);
681 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 680}
682 unsigned int fifo_size; 681EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
683
684 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
685 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
686 /* Playback, no problem using link position */
687 return link_pos;
688 }
689
690 /* Capture */
691 /* For new chipset,
692 * use mod to get the DMA position just like old chipset
693 */
694 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
695 mod_dma_pos %= azx_dev->period_bytes;
696
697 /* azx_dev->fifo_size can't get FIFO size of in stream.
698 * Get from base address + offset.
699 */
700 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
701
702 if (azx_dev->insufficient) {
703 /* Link position never gather than FIFO size */
704 if (link_pos <= fifo_size)
705 return 0;
706
707 azx_dev->insufficient = 0;
708 }
709
710 if (link_pos <= fifo_size)
711 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
712 else
713 mini_pos = link_pos - fifo_size;
714
715 /* Find nearest previous boudary */
716 mod_mini_pos = mini_pos % azx_dev->period_bytes;
717 mod_link_pos = link_pos % azx_dev->period_bytes;
718 if (mod_link_pos >= fifo_size)
719 bound_pos = link_pos - mod_link_pos;
720 else if (mod_dma_pos >= mod_mini_pos)
721 bound_pos = mini_pos - mod_mini_pos;
722 else {
723 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
724 if (bound_pos >= azx_dev->bufsize)
725 bound_pos = 0;
726 }
727 682
728 /* Calculate real DMA position we want */ 683unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
729 return bound_pos + mod_dma_pos; 684{
685 return le32_to_cpu(*azx_dev->posbuf);
730} 686}
687EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
731 688
732unsigned int azx_get_position(struct azx *chip, 689unsigned int azx_get_position(struct azx *chip,
733 struct azx_dev *azx_dev, 690 struct azx_dev *azx_dev)
734 bool with_check)
735{ 691{
736 struct snd_pcm_substream *substream = azx_dev->substream; 692 struct snd_pcm_substream *substream = azx_dev->substream;
737 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
738 unsigned int pos; 693 unsigned int pos;
739 int stream = substream->stream; 694 int stream = substream->stream;
740 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
741 int delay = 0; 695 int delay = 0;
742 696
743 switch (chip->position_fix[stream]) { 697 if (chip->get_position[stream])
744 case POS_FIX_LPIB: 698 pos = chip->get_position[stream](chip, azx_dev);
745 /* read LPIB */ 699 else /* use the position buffer as default */
746 pos = azx_sd_readl(chip, azx_dev, SD_LPIB); 700 pos = azx_get_pos_posbuf(chip, azx_dev);
747 break;
748 case POS_FIX_VIACOMBO:
749 pos = azx_via_get_position(chip, azx_dev);
750 break;
751 default:
752 /* use the position buffer */
753 pos = le32_to_cpu(*azx_dev->posbuf);
754 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
755 if (!pos || pos == (u32)-1) {
756 dev_info(chip->card->dev,
757 "Invalid position buffer, using LPIB read method instead.\n");
758 chip->position_fix[stream] = POS_FIX_LPIB;
759 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
760 } else
761 chip->position_fix[stream] = POS_FIX_POSBUF;
762 }
763 break;
764 }
765 701
766 if (pos >= azx_dev->bufsize) 702 if (pos >= azx_dev->bufsize)
767 pos = 0; 703 pos = 0;
768 704
769 /* calculate runtime delay from LPIB */
770 if (substream->runtime &&
771 chip->position_fix[stream] == POS_FIX_POSBUF &&
772 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
773 unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
774 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
775 delay = pos - lpib_pos;
776 else
777 delay = lpib_pos - pos;
778 if (delay < 0) {
779 if (delay >= azx_dev->delay_negative_threshold)
780 delay = 0;
781 else
782 delay += azx_dev->bufsize;
783 }
784 if (delay >= azx_dev->period_bytes) {
785 dev_info(chip->card->dev,
786 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
787 delay, azx_dev->period_bytes);
788 delay = 0;
789 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
790 }
791 delay = bytes_to_frames(substream->runtime, delay);
792 }
793
794 if (substream->runtime) { 705 if (substream->runtime) {
706 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
707 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
708
709 if (chip->get_delay[stream])
710 delay += chip->get_delay[stream](chip, azx_dev, pos);
795 if (hinfo->ops.get_delay) 711 if (hinfo->ops.get_delay)
796 delay += hinfo->ops.get_delay(hinfo, apcm->codec, 712 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
797 substream); 713 substream);
@@ -809,7 +725,7 @@ static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
809 struct azx *chip = apcm->chip; 725 struct azx *chip = apcm->chip;
810 struct azx_dev *azx_dev = get_azx_dev(substream); 726 struct azx_dev *azx_dev = get_azx_dev(substream);
811 return bytes_to_frames(substream->runtime, 727 return bytes_to_frames(substream->runtime,
812 azx_get_position(chip, azx_dev, false)); 728 azx_get_position(chip, azx_dev));
813} 729}
814 730
815static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream, 731static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
@@ -1059,10 +975,10 @@ static void azx_init_cmd_io(struct azx *chip)
1059 azx_writew(chip, CORBWP, 0); 975 azx_writew(chip, CORBWP, 0);
1060 976
1061 /* reset the corb hw read pointer */ 977 /* reset the corb hw read pointer */
1062 azx_writew(chip, CORBRP, ICH6_CORBRP_RST); 978 azx_writew(chip, CORBRP, AZX_CORBRP_RST);
1063 if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) { 979 if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) {
1064 for (timeout = 1000; timeout > 0; timeout--) { 980 for (timeout = 1000; timeout > 0; timeout--) {
1065 if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST) 981 if ((azx_readw(chip, CORBRP) & AZX_CORBRP_RST) == AZX_CORBRP_RST)
1066 break; 982 break;
1067 udelay(1); 983 udelay(1);
1068 } 984 }
@@ -1082,7 +998,7 @@ static void azx_init_cmd_io(struct azx *chip)
1082 } 998 }
1083 999
1084 /* enable corb dma */ 1000 /* enable corb dma */
1085 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); 1001 azx_writeb(chip, CORBCTL, AZX_CORBCTL_RUN);
1086 1002
1087 /* RIRB set up */ 1003 /* RIRB set up */
1088 chip->rirb.addr = chip->rb.addr + 2048; 1004 chip->rirb.addr = chip->rb.addr + 2048;
@@ -1095,14 +1011,14 @@ static void azx_init_cmd_io(struct azx *chip)
1095 /* set the rirb size to 256 entries (ULI requires explicitly) */ 1011 /* set the rirb size to 256 entries (ULI requires explicitly) */
1096 azx_writeb(chip, RIRBSIZE, 0x02); 1012 azx_writeb(chip, RIRBSIZE, 0x02);
1097 /* reset the rirb hw write pointer */ 1013 /* reset the rirb hw write pointer */
1098 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); 1014 azx_writew(chip, RIRBWP, AZX_RIRBWP_RST);
1099 /* set N=1, get RIRB response interrupt for new entry */ 1015 /* set N=1, get RIRB response interrupt for new entry */
1100 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) 1016 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1101 azx_writew(chip, RINTCNT, 0xc0); 1017 azx_writew(chip, RINTCNT, 0xc0);
1102 else 1018 else
1103 azx_writew(chip, RINTCNT, 1); 1019 azx_writew(chip, RINTCNT, 1);
1104 /* enable rirb dma and response irq */ 1020 /* enable rirb dma and response irq */
1105 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); 1021 azx_writeb(chip, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
1106 spin_unlock_irq(&chip->reg_lock); 1022 spin_unlock_irq(&chip->reg_lock);
1107} 1023}
1108EXPORT_SYMBOL_GPL(azx_init_cmd_io); 1024EXPORT_SYMBOL_GPL(azx_init_cmd_io);
@@ -1146,7 +1062,7 @@ static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1146 return -EIO; 1062 return -EIO;
1147 } 1063 }
1148 wp++; 1064 wp++;
1149 wp %= ICH6_MAX_CORB_ENTRIES; 1065 wp %= AZX_MAX_CORB_ENTRIES;
1150 1066
1151 rp = azx_readw(chip, CORBRP); 1067 rp = azx_readw(chip, CORBRP);
1152 if (wp == rp) { 1068 if (wp == rp) {
@@ -1164,7 +1080,7 @@ static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1164 return 0; 1080 return 0;
1165} 1081}
1166 1082
1167#define ICH6_RIRB_EX_UNSOL_EV (1<<4) 1083#define AZX_RIRB_EX_UNSOL_EV (1<<4)
1168 1084
1169/* retrieve RIRB entry - called from interrupt handler */ 1085/* retrieve RIRB entry - called from interrupt handler */
1170static void azx_update_rirb(struct azx *chip) 1086static void azx_update_rirb(struct azx *chip)
@@ -1185,7 +1101,7 @@ static void azx_update_rirb(struct azx *chip)
1185 1101
1186 while (chip->rirb.rp != wp) { 1102 while (chip->rirb.rp != wp) {
1187 chip->rirb.rp++; 1103 chip->rirb.rp++;
1188 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; 1104 chip->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
1189 1105
1190 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 1106 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
1191 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); 1107 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
@@ -1196,8 +1112,7 @@ static void azx_update_rirb(struct azx *chip)
1196 res, res_ex, 1112 res, res_ex,
1197 chip->rirb.rp, wp); 1113 chip->rirb.rp, wp);
1198 snd_BUG(); 1114 snd_BUG();
1199 } 1115 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
1200 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
1201 snd_hda_queue_unsol_event(chip->bus, res, res_ex); 1116 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
1202 else if (chip->rirb.cmds[addr]) { 1117 else if (chip->rirb.cmds[addr]) {
1203 chip->rirb.res[addr] = res; 1118 chip->rirb.res[addr] = res;
@@ -1305,7 +1220,7 @@ static unsigned int azx_rirb_get_response(struct hda_bus *bus,
1305 /* release CORB/RIRB */ 1220 /* release CORB/RIRB */
1306 azx_free_cmd_io(chip); 1221 azx_free_cmd_io(chip);
1307 /* disable unsolicited responses */ 1222 /* disable unsolicited responses */
1308 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); 1223 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL);
1309 return -1; 1224 return -1;
1310} 1225}
1311 1226
@@ -1326,7 +1241,7 @@ static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1326 1241
1327 while (timeout--) { 1242 while (timeout--) {
1328 /* check IRV busy bit */ 1243 /* check IRV busy bit */
1329 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { 1244 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
1330 /* reuse rirb.res as the response return value */ 1245 /* reuse rirb.res as the response return value */
1331 chip->rirb.res[addr] = azx_readl(chip, IR); 1246 chip->rirb.res[addr] = azx_readl(chip, IR);
1332 return 0; 1247 return 0;
@@ -1350,13 +1265,13 @@ static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1350 bus->rirb_error = 0; 1265 bus->rirb_error = 0;
1351 while (timeout--) { 1266 while (timeout--) {
1352 /* check ICB busy bit */ 1267 /* check ICB busy bit */
1353 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { 1268 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
1354 /* Clear IRV valid bit */ 1269 /* Clear IRV valid bit */
1355 azx_writew(chip, IRS, azx_readw(chip, IRS) | 1270 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1356 ICH6_IRS_VALID); 1271 AZX_IRS_VALID);
1357 azx_writel(chip, IC, val); 1272 azx_writel(chip, IC, val);
1358 azx_writew(chip, IRS, azx_readw(chip, IRS) | 1273 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1359 ICH6_IRS_BUSY); 1274 AZX_IRS_BUSY);
1360 return azx_single_wait_for_response(chip, addr); 1275 return azx_single_wait_for_response(chip, addr);
1361 } 1276 }
1362 udelay(1); 1277 udelay(1);
@@ -1585,10 +1500,10 @@ void azx_enter_link_reset(struct azx *chip)
1585 unsigned long timeout; 1500 unsigned long timeout;
1586 1501
1587 /* reset controller */ 1502 /* reset controller */
1588 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); 1503 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_RESET);
1589 1504
1590 timeout = jiffies + msecs_to_jiffies(100); 1505 timeout = jiffies + msecs_to_jiffies(100);
1591 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) && 1506 while ((azx_readb(chip, GCTL) & AZX_GCTL_RESET) &&
1592 time_before(jiffies, timeout)) 1507 time_before(jiffies, timeout))
1593 usleep_range(500, 1000); 1508 usleep_range(500, 1000);
1594} 1509}
@@ -1599,7 +1514,7 @@ static void azx_exit_link_reset(struct azx *chip)
1599{ 1514{
1600 unsigned long timeout; 1515 unsigned long timeout;
1601 1516
1602 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); 1517 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | AZX_GCTL_RESET);
1603 1518
1604 timeout = jiffies + msecs_to_jiffies(100); 1519 timeout = jiffies + msecs_to_jiffies(100);
1605 while (!azx_readb(chip, GCTL) && 1520 while (!azx_readb(chip, GCTL) &&
@@ -1640,7 +1555,7 @@ static int azx_reset(struct azx *chip, bool full_reset)
1640 /* Accept unsolicited responses */ 1555 /* Accept unsolicited responses */
1641 if (!chip->single_cmd) 1556 if (!chip->single_cmd)
1642 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | 1557 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1643 ICH6_GCTL_UNSOL); 1558 AZX_GCTL_UNSOL);
1644 1559
1645 /* detect codecs */ 1560 /* detect codecs */
1646 if (!chip->codec_mask) { 1561 if (!chip->codec_mask) {
@@ -1657,7 +1572,7 @@ static void azx_int_enable(struct azx *chip)
1657{ 1572{
1658 /* enable controller CIE and GIE */ 1573 /* enable controller CIE and GIE */
1659 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | 1574 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1660 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); 1575 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
1661} 1576}
1662 1577
1663/* disable interrupts */ 1578/* disable interrupts */
@@ -1678,7 +1593,7 @@ static void azx_int_disable(struct azx *chip)
1678 1593
1679 /* disable controller CIE and GIE */ 1594 /* disable controller CIE and GIE */
1680 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & 1595 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1681 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); 1596 ~(AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN));
1682} 1597}
1683 1598
1684/* clear interrupts */ 1599/* clear interrupts */
@@ -1699,7 +1614,7 @@ static void azx_int_clear(struct azx *chip)
1699 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1614 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1700 1615
1701 /* clear int status */ 1616 /* clear int status */
1702 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 1617 azx_writel(chip, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
1703} 1618}
1704 1619
1705/* 1620/*
@@ -2031,5 +1946,30 @@ int azx_init_stream(struct azx *chip)
2031} 1946}
2032EXPORT_SYMBOL_GPL(azx_init_stream); 1947EXPORT_SYMBOL_GPL(azx_init_stream);
2033 1948
1949/*
1950 * reboot notifier for hang-up problem at power-down
1951 */
1952static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1953{
1954 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1955 snd_hda_bus_reboot_notify(chip->bus);
1956 azx_stop_chip(chip);
1957 return NOTIFY_OK;
1958}
1959
1960void azx_notifier_register(struct azx *chip)
1961{
1962 chip->reboot_notifier.notifier_call = azx_halt;
1963 register_reboot_notifier(&chip->reboot_notifier);
1964}
1965EXPORT_SYMBOL_GPL(azx_notifier_register);
1966
1967void azx_notifier_unregister(struct azx *chip)
1968{
1969 if (chip->reboot_notifier.notifier_call)
1970 unregister_reboot_notifier(&chip->reboot_notifier);
1971}
1972EXPORT_SYMBOL_GPL(azx_notifier_unregister);
1973
2034MODULE_LICENSE("GPL"); 1974MODULE_LICENSE("GPL");
2035MODULE_DESCRIPTION("Common HDA driver funcitons"); 1975MODULE_DESCRIPTION("Common HDA driver funcitons");
diff --git a/sound/pci/hda/hda_controller.h b/sound/pci/hda/hda_controller.h
index baf0e77330af..c90d10fd4d8f 100644
--- a/sound/pci/hda/hda_controller.h
+++ b/sound/pci/hda/hda_controller.h
@@ -25,9 +25,9 @@ static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
25{ 25{
26 return substream->runtime->private_data; 26 return substream->runtime->private_data;
27} 27}
28unsigned int azx_get_position(struct azx *chip, 28unsigned int azx_get_position(struct azx *chip, struct azx_dev *azx_dev);
29 struct azx_dev *azx_dev, 29unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev);
30 bool with_check); 30unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev);
31 31
32/* Stream control. */ 32/* Stream control. */
33void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev); 33void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev);
@@ -50,4 +50,7 @@ int azx_codec_configure(struct azx *chip);
50int azx_mixer_create(struct azx *chip); 50int azx_mixer_create(struct azx *chip);
51int azx_init_stream(struct azx *chip); 51int azx_init_stream(struct azx *chip);
52 52
53void azx_notifier_register(struct azx *chip);
54void azx_notifier_unregister(struct azx *chip);
55
53#endif /* __SOUND_HDA_CONTROLLER_H */ 56#endif /* __SOUND_HDA_CONTROLLER_H */
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 25753db97071..dc0c8dac1900 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -44,7 +44,6 @@
44#include <linux/slab.h> 44#include <linux/slab.h>
45#include <linux/pci.h> 45#include <linux/pci.h>
46#include <linux/mutex.h> 46#include <linux/mutex.h>
47#include <linux/reboot.h>
48#include <linux/io.h> 47#include <linux/io.h>
49#include <linux/pm_runtime.h> 48#include <linux/pm_runtime.h>
50#include <linux/clocksource.h> 49#include <linux/clocksource.h>
@@ -66,6 +65,52 @@
66#include "hda_controller.h" 65#include "hda_controller.h"
67#include "hda_priv.h" 66#include "hda_priv.h"
68 67
68/* position fix mode */
69enum {
70 POS_FIX_AUTO,
71 POS_FIX_LPIB,
72 POS_FIX_POSBUF,
73 POS_FIX_VIACOMBO,
74 POS_FIX_COMBO,
75};
76
77/* Defines for ATI HD Audio support in SB450 south bridge */
78#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
79#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
80
81/* Defines for Nvidia HDA support */
82#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
83#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
84#define NVIDIA_HDA_ISTRM_COH 0x4d
85#define NVIDIA_HDA_OSTRM_COH 0x4c
86#define NVIDIA_HDA_ENABLE_COHBIT 0x01
87
88/* Defines for Intel SCH HDA snoop control */
89#define INTEL_SCH_HDA_DEVC 0x78
90#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
91
92/* Define IN stream 0 FIFO size offset in VIA controller */
93#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
94/* Define VIA HD Audio Device ID*/
95#define VIA_HDAC_DEVICE_ID 0x3288
96
97/* max number of SDs */
98/* ICH, ATI and VIA have 4 playback and 4 capture */
99#define ICH6_NUM_CAPTURE 4
100#define ICH6_NUM_PLAYBACK 4
101
102/* ULI has 6 playback and 5 capture */
103#define ULI_NUM_CAPTURE 5
104#define ULI_NUM_PLAYBACK 6
105
106/* ATI HDMI may have up to 8 playbacks and 0 capture */
107#define ATIHDMI_NUM_CAPTURE 0
108#define ATIHDMI_NUM_PLAYBACK 8
109
110/* TERA has 4 playback and 3 capture */
111#define TERA_NUM_CAPTURE 3
112#define TERA_NUM_PLAYBACK 4
113
69 114
70static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 115static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 116static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
@@ -294,8 +339,8 @@ static char *driver_short_names[] = {
294 * Clock) to 24MHz BCLK: BCLK = CDCLK * M / N 339 * Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
295 * The values will be lost when the display power well is disabled. 340 * The values will be lost when the display power well is disabled.
296 */ 341 */
297#define ICH6_REG_EM4 0x100c 342#define AZX_REG_EM4 0x100c
298#define ICH6_REG_EM5 0x1010 343#define AZX_REG_EM5 0x1010
299 344
300struct hda_intel { 345struct hda_intel {
301 struct azx chip; 346 struct azx chip;
@@ -303,8 +348,28 @@ struct hda_intel {
303 /* HSW/BDW display HDA controller to restore BCLK from CDCLK */ 348 /* HSW/BDW display HDA controller to restore BCLK from CDCLK */
304 unsigned int bclk_m; 349 unsigned int bclk_m;
305 unsigned int bclk_n; 350 unsigned int bclk_n;
306};
307 351
352 /* for pending irqs */
353 struct work_struct irq_pending_work;
354
355 /* sync probing */
356 struct completion probe_wait;
357 struct work_struct probe_work;
358
359 /* card list (for power_save trigger) */
360 struct list_head list;
361
362 /* extra flags */
363 unsigned int irq_pending_warned:1;
364
365 /* VGA-switcheroo setup */
366 unsigned int use_vga_switcheroo:1;
367 unsigned int vga_switcheroo_registered:1;
368 unsigned int init_failed:1; /* delayed init failed */
369
370 /* secondary power domain for hdmi audio under vga device */
371 struct dev_pm_domain hdmi_pm_domain;
372};
308 373
309#ifdef CONFIG_X86 374#ifdef CONFIG_X86
310static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 375static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
@@ -386,7 +451,7 @@ static void azx_init_pci(struct azx *chip)
386 */ 451 */
387 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 452 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
388 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 453 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
389 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); 454 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
390 } 455 }
391 456
392 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 457 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
@@ -434,11 +499,44 @@ static void azx_init_pci(struct azx *chip)
434 } 499 }
435} 500}
436 501
502/* calculate runtime delay from LPIB */
503static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
504 unsigned int pos)
505{
506 struct snd_pcm_substream *substream = azx_dev->substream;
507 int stream = substream->stream;
508 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
509 int delay;
510
511 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
512 delay = pos - lpib_pos;
513 else
514 delay = lpib_pos - pos;
515 if (delay < 0) {
516 if (delay >= azx_dev->delay_negative_threshold)
517 delay = 0;
518 else
519 delay += azx_dev->bufsize;
520 }
521
522 if (delay >= azx_dev->period_bytes) {
523 dev_info(chip->card->dev,
524 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
525 delay, azx_dev->period_bytes);
526 delay = 0;
527 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
528 chip->get_delay[stream] = NULL;
529 }
530
531 return bytes_to_frames(substream->runtime, delay);
532}
533
437static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 534static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
438 535
439/* called from IRQ */ 536/* called from IRQ */
440static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 537static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
441{ 538{
539 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
442 int ok; 540 int ok;
443 541
444 ok = azx_position_ok(chip, azx_dev); 542 ok = azx_position_ok(chip, azx_dev);
@@ -448,7 +546,7 @@ static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
448 } else if (ok == 0 && chip->bus && chip->bus->workq) { 546 } else if (ok == 0 && chip->bus && chip->bus->workq) {
449 /* bogus IRQ, process it later */ 547 /* bogus IRQ, process it later */
450 azx_dev->irq_pending = 1; 548 azx_dev->irq_pending = 1;
451 queue_work(chip->bus->workq, &chip->irq_pending_work); 549 queue_work(chip->bus->workq, &hda->irq_pending_work);
452 } 550 }
453 return 0; 551 return 0;
454} 552}
@@ -464,6 +562,8 @@ static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
464 */ 562 */
465static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 563static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
466{ 564{
565 struct snd_pcm_substream *substream = azx_dev->substream;
566 int stream = substream->stream;
467 u32 wallclk; 567 u32 wallclk;
468 unsigned int pos; 568 unsigned int pos;
469 569
@@ -471,7 +571,25 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
471 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 571 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
472 return -1; /* bogus (too early) interrupt */ 572 return -1; /* bogus (too early) interrupt */
473 573
474 pos = azx_get_position(chip, azx_dev, true); 574 if (chip->get_position[stream])
575 pos = chip->get_position[stream](chip, azx_dev);
576 else { /* use the position buffer as default */
577 pos = azx_get_pos_posbuf(chip, azx_dev);
578 if (!pos || pos == (u32)-1) {
579 dev_info(chip->card->dev,
580 "Invalid position buffer, using LPIB read method instead.\n");
581 chip->get_position[stream] = azx_get_pos_lpib;
582 pos = azx_get_pos_lpib(chip, azx_dev);
583 chip->get_delay[stream] = NULL;
584 } else {
585 chip->get_position[stream] = azx_get_pos_posbuf;
586 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
587 chip->get_delay[stream] = azx_get_delay_from_lpib;
588 }
589 }
590
591 if (pos >= azx_dev->bufsize)
592 pos = 0;
475 593
476 if (WARN_ONCE(!azx_dev->period_bytes, 594 if (WARN_ONCE(!azx_dev->period_bytes,
477 "hda-intel: zero azx_dev->period_bytes")) 595 "hda-intel: zero azx_dev->period_bytes"))
@@ -489,14 +607,15 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
489 */ 607 */
490static void azx_irq_pending_work(struct work_struct *work) 608static void azx_irq_pending_work(struct work_struct *work)
491{ 609{
492 struct azx *chip = container_of(work, struct azx, irq_pending_work); 610 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
611 struct azx *chip = &hda->chip;
493 int i, pending, ok; 612 int i, pending, ok;
494 613
495 if (!chip->irq_pending_warned) { 614 if (!hda->irq_pending_warned) {
496 dev_info(chip->card->dev, 615 dev_info(chip->card->dev,
497 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 616 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
498 chip->card->number); 617 chip->card->number);
499 chip->irq_pending_warned = 1; 618 hda->irq_pending_warned = 1;
500 } 619 }
501 620
502 for (;;) { 621 for (;;) {
@@ -554,27 +673,86 @@ static int azx_acquire_irq(struct azx *chip, int do_disconnect)
554 return 0; 673 return 0;
555} 674}
556 675
676/* get the current DMA position with correction on VIA chips */
677static unsigned int azx_via_get_position(struct azx *chip,
678 struct azx_dev *azx_dev)
679{
680 unsigned int link_pos, mini_pos, bound_pos;
681 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
682 unsigned int fifo_size;
683
684 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
685 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
686 /* Playback, no problem using link position */
687 return link_pos;
688 }
689
690 /* Capture */
691 /* For new chipset,
692 * use mod to get the DMA position just like old chipset
693 */
694 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
695 mod_dma_pos %= azx_dev->period_bytes;
696
697 /* azx_dev->fifo_size can't get FIFO size of in stream.
698 * Get from base address + offset.
699 */
700 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
701
702 if (azx_dev->insufficient) {
703 /* Link position never gather than FIFO size */
704 if (link_pos <= fifo_size)
705 return 0;
706
707 azx_dev->insufficient = 0;
708 }
709
710 if (link_pos <= fifo_size)
711 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
712 else
713 mini_pos = link_pos - fifo_size;
714
715 /* Find nearest previous boudary */
716 mod_mini_pos = mini_pos % azx_dev->period_bytes;
717 mod_link_pos = link_pos % azx_dev->period_bytes;
718 if (mod_link_pos >= fifo_size)
719 bound_pos = link_pos - mod_link_pos;
720 else if (mod_dma_pos >= mod_mini_pos)
721 bound_pos = mini_pos - mod_mini_pos;
722 else {
723 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
724 if (bound_pos >= azx_dev->bufsize)
725 bound_pos = 0;
726 }
727
728 /* Calculate real DMA position we want */
729 return bound_pos + mod_dma_pos;
730}
731
557#ifdef CONFIG_PM 732#ifdef CONFIG_PM
558static DEFINE_MUTEX(card_list_lock); 733static DEFINE_MUTEX(card_list_lock);
559static LIST_HEAD(card_list); 734static LIST_HEAD(card_list);
560 735
561static void azx_add_card_list(struct azx *chip) 736static void azx_add_card_list(struct azx *chip)
562{ 737{
738 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
563 mutex_lock(&card_list_lock); 739 mutex_lock(&card_list_lock);
564 list_add(&chip->list, &card_list); 740 list_add(&hda->list, &card_list);
565 mutex_unlock(&card_list_lock); 741 mutex_unlock(&card_list_lock);
566} 742}
567 743
568static void azx_del_card_list(struct azx *chip) 744static void azx_del_card_list(struct azx *chip)
569{ 745{
746 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
570 mutex_lock(&card_list_lock); 747 mutex_lock(&card_list_lock);
571 list_del_init(&chip->list); 748 list_del_init(&hda->list);
572 mutex_unlock(&card_list_lock); 749 mutex_unlock(&card_list_lock);
573} 750}
574 751
575/* trigger power-save check at writing parameter */ 752/* trigger power-save check at writing parameter */
576static int param_set_xint(const char *val, const struct kernel_param *kp) 753static int param_set_xint(const char *val, const struct kernel_param *kp)
577{ 754{
755 struct hda_intel *hda;
578 struct azx *chip; 756 struct azx *chip;
579 struct hda_codec *c; 757 struct hda_codec *c;
580 int prev = power_save; 758 int prev = power_save;
@@ -584,7 +762,8 @@ static int param_set_xint(const char *val, const struct kernel_param *kp)
584 return ret; 762 return ret;
585 763
586 mutex_lock(&card_list_lock); 764 mutex_lock(&card_list_lock);
587 list_for_each_entry(chip, &card_list, list) { 765 list_for_each_entry(hda, &card_list, list) {
766 chip = &hda->chip;
588 if (!chip->bus || chip->disabled) 767 if (!chip->bus || chip->disabled)
589 continue; 768 continue;
590 list_for_each_entry(c, &chip->bus->codec_list, list) 769 list_for_each_entry(c, &chip->bus->codec_list, list)
@@ -789,29 +968,6 @@ static const struct dev_pm_ops azx_pm = {
789#endif /* CONFIG_PM */ 968#endif /* CONFIG_PM */
790 969
791 970
792/*
793 * reboot notifier for hang-up problem at power-down
794 */
795static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
796{
797 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
798 snd_hda_bus_reboot_notify(chip->bus);
799 azx_stop_chip(chip);
800 return NOTIFY_OK;
801}
802
803static void azx_notifier_register(struct azx *chip)
804{
805 chip->reboot_notifier.notifier_call = azx_halt;
806 register_reboot_notifier(&chip->reboot_notifier);
807}
808
809static void azx_notifier_unregister(struct azx *chip)
810{
811 if (chip->reboot_notifier.notifier_call)
812 unregister_reboot_notifier(&chip->reboot_notifier);
813}
814
815static int azx_probe_continue(struct azx *chip); 971static int azx_probe_continue(struct azx *chip);
816 972
817#ifdef SUPPORT_VGA_SWITCHEROO 973#ifdef SUPPORT_VGA_SWITCHEROO
@@ -822,10 +978,11 @@ static void azx_vs_set_state(struct pci_dev *pci,
822{ 978{
823 struct snd_card *card = pci_get_drvdata(pci); 979 struct snd_card *card = pci_get_drvdata(pci);
824 struct azx *chip = card->private_data; 980 struct azx *chip = card->private_data;
981 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
825 bool disabled; 982 bool disabled;
826 983
827 wait_for_completion(&chip->probe_wait); 984 wait_for_completion(&hda->probe_wait);
828 if (chip->init_failed) 985 if (hda->init_failed)
829 return; 986 return;
830 987
831 disabled = (state == VGA_SWITCHEROO_OFF); 988 disabled = (state == VGA_SWITCHEROO_OFF);
@@ -839,7 +996,7 @@ static void azx_vs_set_state(struct pci_dev *pci,
839 "Start delayed initialization\n"); 996 "Start delayed initialization\n");
840 if (azx_probe_continue(chip) < 0) { 997 if (azx_probe_continue(chip) < 0) {
841 dev_err(chip->card->dev, "initialization error\n"); 998 dev_err(chip->card->dev, "initialization error\n");
842 chip->init_failed = true; 999 hda->init_failed = true;
843 } 1000 }
844 } 1001 }
845 } else { 1002 } else {
@@ -869,9 +1026,10 @@ static bool azx_vs_can_switch(struct pci_dev *pci)
869{ 1026{
870 struct snd_card *card = pci_get_drvdata(pci); 1027 struct snd_card *card = pci_get_drvdata(pci);
871 struct azx *chip = card->private_data; 1028 struct azx *chip = card->private_data;
1029 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
872 1030
873 wait_for_completion(&chip->probe_wait); 1031 wait_for_completion(&hda->probe_wait);
874 if (chip->init_failed) 1032 if (hda->init_failed)
875 return false; 1033 return false;
876 if (chip->disabled || !chip->bus) 1034 if (chip->disabled || !chip->bus)
877 return true; 1035 return true;
@@ -883,11 +1041,12 @@ static bool azx_vs_can_switch(struct pci_dev *pci)
883 1041
884static void init_vga_switcheroo(struct azx *chip) 1042static void init_vga_switcheroo(struct azx *chip)
885{ 1043{
1044 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
886 struct pci_dev *p = get_bound_vga(chip->pci); 1045 struct pci_dev *p = get_bound_vga(chip->pci);
887 if (p) { 1046 if (p) {
888 dev_info(chip->card->dev, 1047 dev_info(chip->card->dev,
889 "Handle VGA-switcheroo audio client\n"); 1048 "Handle VGA-switcheroo audio client\n");
890 chip->use_vga_switcheroo = 1; 1049 hda->use_vga_switcheroo = 1;
891 pci_dev_put(p); 1050 pci_dev_put(p);
892 } 1051 }
893} 1052}
@@ -899,9 +1058,10 @@ static const struct vga_switcheroo_client_ops azx_vs_ops = {
899 1058
900static int register_vga_switcheroo(struct azx *chip) 1059static int register_vga_switcheroo(struct azx *chip)
901{ 1060{
1061 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
902 int err; 1062 int err;
903 1063
904 if (!chip->use_vga_switcheroo) 1064 if (!hda->use_vga_switcheroo)
905 return 0; 1065 return 0;
906 /* FIXME: currently only handling DIS controller 1066 /* FIXME: currently only handling DIS controller
907 * is there any machine with two switchable HDMI audio controllers? 1067 * is there any machine with two switchable HDMI audio controllers?
@@ -911,11 +1071,11 @@ static int register_vga_switcheroo(struct azx *chip)
911 chip->bus != NULL); 1071 chip->bus != NULL);
912 if (err < 0) 1072 if (err < 0)
913 return err; 1073 return err;
914 chip->vga_switcheroo_registered = 1; 1074 hda->vga_switcheroo_registered = 1;
915 1075
916 /* register as an optimus hdmi audio power domain */ 1076 /* register as an optimus hdmi audio power domain */
917 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1077 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
918 &chip->hdmi_pm_domain); 1078 &hda->hdmi_pm_domain);
919 return 0; 1079 return 0;
920} 1080}
921#else 1081#else
@@ -931,7 +1091,6 @@ static int azx_free(struct azx *chip)
931{ 1091{
932 struct pci_dev *pci = chip->pci; 1092 struct pci_dev *pci = chip->pci;
933 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1093 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
934
935 int i; 1094 int i;
936 1095
937 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) 1096 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
@@ -942,13 +1101,13 @@ static int azx_free(struct azx *chip)
942 1101
943 azx_notifier_unregister(chip); 1102 azx_notifier_unregister(chip);
944 1103
945 chip->init_failed = 1; /* to be sure */ 1104 hda->init_failed = 1; /* to be sure */
946 complete_all(&chip->probe_wait); 1105 complete_all(&hda->probe_wait);
947 1106
948 if (use_vga_switcheroo(chip)) { 1107 if (use_vga_switcheroo(hda)) {
949 if (chip->disabled && chip->bus) 1108 if (chip->disabled && chip->bus)
950 snd_hda_unlock_devices(chip->bus); 1109 snd_hda_unlock_devices(chip->bus);
951 if (chip->vga_switcheroo_registered) 1110 if (hda->vga_switcheroo_registered)
952 vga_switcheroo_unregister_client(chip->pci); 1111 vga_switcheroo_unregister_client(chip->pci);
953 } 1112 }
954 1113
@@ -1084,6 +1243,30 @@ static int check_position_fix(struct azx *chip, int fix)
1084 return POS_FIX_AUTO; 1243 return POS_FIX_AUTO;
1085} 1244}
1086 1245
1246static void assign_position_fix(struct azx *chip, int fix)
1247{
1248 static azx_get_pos_callback_t callbacks[] = {
1249 [POS_FIX_AUTO] = NULL,
1250 [POS_FIX_LPIB] = azx_get_pos_lpib,
1251 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1252 [POS_FIX_VIACOMBO] = azx_via_get_position,
1253 [POS_FIX_COMBO] = azx_get_pos_lpib,
1254 };
1255
1256 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1257
1258 /* combo mode uses LPIB only for playback */
1259 if (fix == POS_FIX_COMBO)
1260 chip->get_position[1] = NULL;
1261
1262 if (fix == POS_FIX_POSBUF &&
1263 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1264 chip->get_delay[0] = chip->get_delay[1] =
1265 azx_get_delay_from_lpib;
1266 }
1267
1268}
1269
1087/* 1270/*
1088 * black-lists for probe_mask 1271 * black-lists for probe_mask
1089 */ 1272 */
@@ -1209,7 +1392,8 @@ static void azx_check_snoop_available(struct azx *chip)
1209 1392
1210static void azx_probe_work(struct work_struct *work) 1393static void azx_probe_work(struct work_struct *work)
1211{ 1394{
1212 azx_probe_continue(container_of(work, struct azx, probe_work)); 1395 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1396 azx_probe_continue(&hda->chip);
1213} 1397}
1214 1398
1215/* 1399/*
@@ -1252,19 +1436,13 @@ static int azx_create(struct snd_card *card, struct pci_dev *pci,
1252 check_msi(chip); 1436 check_msi(chip);
1253 chip->dev_index = dev; 1437 chip->dev_index = dev;
1254 chip->jackpoll_ms = jackpoll_ms; 1438 chip->jackpoll_ms = jackpoll_ms;
1255 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1256 INIT_LIST_HEAD(&chip->pcm_list); 1439 INIT_LIST_HEAD(&chip->pcm_list);
1257 INIT_LIST_HEAD(&chip->list); 1440 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1441 INIT_LIST_HEAD(&hda->list);
1258 init_vga_switcheroo(chip); 1442 init_vga_switcheroo(chip);
1259 init_completion(&chip->probe_wait); 1443 init_completion(&hda->probe_wait);
1260 1444
1261 chip->position_fix[0] = chip->position_fix[1] = 1445 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1262 check_position_fix(chip, position_fix[dev]);
1263 /* combo mode uses LPIB for playback */
1264 if (chip->position_fix[0] == POS_FIX_COMBO) {
1265 chip->position_fix[0] = POS_FIX_LPIB;
1266 chip->position_fix[1] = POS_FIX_AUTO;
1267 }
1268 1446
1269 check_probe_mask(chip, dev); 1447 check_probe_mask(chip, dev);
1270 1448
@@ -1293,7 +1471,7 @@ static int azx_create(struct snd_card *card, struct pci_dev *pci,
1293 } 1471 }
1294 1472
1295 /* continue probing in work context as may trigger request module */ 1473 /* continue probing in work context as may trigger request module */
1296 INIT_WORK(&chip->probe_work, azx_probe_work); 1474 INIT_WORK(&hda->probe_work, azx_probe_work);
1297 1475
1298 *rchip = chip; 1476 *rchip = chip;
1299 1477
@@ -1351,7 +1529,7 @@ static int azx_first_init(struct azx *chip)
1351 NULL); 1529 NULL);
1352 if (p_smbus) { 1530 if (p_smbus) {
1353 if (p_smbus->revision < 0x30) 1531 if (p_smbus->revision < 0x30)
1354 gcap &= ~ICH6_GCAP_64OK; 1532 gcap &= ~AZX_GCAP_64OK;
1355 pci_dev_put(p_smbus); 1533 pci_dev_put(p_smbus);
1356 } 1534 }
1357 } 1535 }
@@ -1359,7 +1537,7 @@ static int azx_first_init(struct azx *chip)
1359 /* disable 64bit DMA address on some devices */ 1537 /* disable 64bit DMA address on some devices */
1360 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1538 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1361 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1539 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1362 gcap &= ~ICH6_GCAP_64OK; 1540 gcap &= ~AZX_GCAP_64OK;
1363 } 1541 }
1364 1542
1365 /* disable buffer size rounding to 128-byte multiples if supported */ 1543 /* disable buffer size rounding to 128-byte multiples if supported */
@@ -1375,7 +1553,7 @@ static int azx_first_init(struct azx *chip)
1375 } 1553 }
1376 1554
1377 /* allow 64bit DMA address if supported by H/W */ 1555 /* allow 64bit DMA address if supported by H/W */
1378 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) 1556 if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
1379 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); 1557 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
1380 else { 1558 else {
1381 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 1559 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
@@ -1615,6 +1793,7 @@ static int azx_probe(struct pci_dev *pci,
1615{ 1793{
1616 static int dev; 1794 static int dev;
1617 struct snd_card *card; 1795 struct snd_card *card;
1796 struct hda_intel *hda;
1618 struct azx *chip; 1797 struct azx *chip;
1619 bool schedule_probe; 1798 bool schedule_probe;
1620 int err; 1799 int err;
@@ -1638,6 +1817,7 @@ static int azx_probe(struct pci_dev *pci,
1638 if (err < 0) 1817 if (err < 0)
1639 goto out_free; 1818 goto out_free;
1640 card->private_data = chip; 1819 card->private_data = chip;
1820 hda = container_of(chip, struct hda_intel, chip);
1641 1821
1642 pci_set_drvdata(pci, card); 1822 pci_set_drvdata(pci, card);
1643 1823
@@ -1674,11 +1854,11 @@ static int azx_probe(struct pci_dev *pci,
1674#endif 1854#endif
1675 1855
1676 if (schedule_probe) 1856 if (schedule_probe)
1677 schedule_work(&chip->probe_work); 1857 schedule_work(&hda->probe_work);
1678 1858
1679 dev++; 1859 dev++;
1680 if (chip->disabled) 1860 if (chip->disabled)
1681 complete_all(&chip->probe_wait); 1861 complete_all(&hda->probe_wait);
1682 return 0; 1862 return 0;
1683 1863
1684out_free: 1864out_free:
@@ -1694,6 +1874,7 @@ static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1694 1874
1695static int azx_probe_continue(struct azx *chip) 1875static int azx_probe_continue(struct azx *chip)
1696{ 1876{
1877 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1697 struct pci_dev *pci = chip->pci; 1878 struct pci_dev *pci = chip->pci;
1698 int dev = chip->dev_index; 1879 int dev = chip->dev_index;
1699 int err; 1880 int err;
@@ -1767,13 +1948,13 @@ static int azx_probe_continue(struct azx *chip)
1767 power_down_all_codecs(chip); 1948 power_down_all_codecs(chip);
1768 azx_notifier_register(chip); 1949 azx_notifier_register(chip);
1769 azx_add_card_list(chip); 1950 azx_add_card_list(chip);
1770 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo) 1951 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo)
1771 pm_runtime_put_noidle(&pci->dev); 1952 pm_runtime_put_noidle(&pci->dev);
1772 1953
1773out_free: 1954out_free:
1774 if (err < 0) 1955 if (err < 0)
1775 chip->init_failed = 1; 1956 hda->init_failed = 1;
1776 complete_all(&chip->probe_wait); 1957 complete_all(&hda->probe_wait);
1777 return err; 1958 return err;
1778} 1959}
1779 1960
diff --git a/sound/pci/hda/hda_priv.h b/sound/pci/hda/hda_priv.h
index 4a7cb01fa912..33eb5d027d38 100644
--- a/sound/pci/hda/hda_priv.h
+++ b/sound/pci/hda/hda_priv.h
@@ -22,107 +22,87 @@
22/* 22/*
23 * registers 23 * registers
24 */ 24 */
25#define ICH6_REG_GCAP 0x00 25#define AZX_REG_GCAP 0x00
26#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ 26#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */
27#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ 27#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */
28#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ 28#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */
29#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ 29#define AZX_GCAP_ISS (15 << 8) /* # of input streams */
30#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ 30#define AZX_GCAP_OSS (15 << 12) /* # of output streams */
31#define ICH6_REG_VMIN 0x02 31#define AZX_REG_VMIN 0x02
32#define ICH6_REG_VMAJ 0x03 32#define AZX_REG_VMAJ 0x03
33#define ICH6_REG_OUTPAY 0x04 33#define AZX_REG_OUTPAY 0x04
34#define ICH6_REG_INPAY 0x06 34#define AZX_REG_INPAY 0x06
35#define ICH6_REG_GCTL 0x08 35#define AZX_REG_GCTL 0x08
36#define ICH6_GCTL_RESET (1 << 0) /* controller reset */ 36#define AZX_GCTL_RESET (1 << 0) /* controller reset */
37#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ 37#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */
38#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ 38#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
39#define ICH6_REG_WAKEEN 0x0c 39#define AZX_REG_WAKEEN 0x0c
40#define ICH6_REG_STATESTS 0x0e 40#define AZX_REG_STATESTS 0x0e
41#define ICH6_REG_GSTS 0x10 41#define AZX_REG_GSTS 0x10
42#define ICH6_GSTS_FSTS (1 << 1) /* flush status */ 42#define AZX_GSTS_FSTS (1 << 1) /* flush status */
43#define ICH6_REG_INTCTL 0x20 43#define AZX_REG_INTCTL 0x20
44#define ICH6_REG_INTSTS 0x24 44#define AZX_REG_INTSTS 0x24
45#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ 45#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */
46#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ 46#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
47#define ICH6_REG_SSYNC 0x38 47#define AZX_REG_SSYNC 0x38
48#define ICH6_REG_CORBLBASE 0x40 48#define AZX_REG_CORBLBASE 0x40
49#define ICH6_REG_CORBUBASE 0x44 49#define AZX_REG_CORBUBASE 0x44
50#define ICH6_REG_CORBWP 0x48 50#define AZX_REG_CORBWP 0x48
51#define ICH6_REG_CORBRP 0x4a 51#define AZX_REG_CORBRP 0x4a
52#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ 52#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */
53#define ICH6_REG_CORBCTL 0x4c 53#define AZX_REG_CORBCTL 0x4c
54#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ 54#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */
55#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ 55#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
56#define ICH6_REG_CORBSTS 0x4d 56#define AZX_REG_CORBSTS 0x4d
57#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ 57#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */
58#define ICH6_REG_CORBSIZE 0x4e 58#define AZX_REG_CORBSIZE 0x4e
59 59
60#define ICH6_REG_RIRBLBASE 0x50 60#define AZX_REG_RIRBLBASE 0x50
61#define ICH6_REG_RIRBUBASE 0x54 61#define AZX_REG_RIRBUBASE 0x54
62#define ICH6_REG_RIRBWP 0x58 62#define AZX_REG_RIRBWP 0x58
63#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ 63#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */
64#define ICH6_REG_RINTCNT 0x5a 64#define AZX_REG_RINTCNT 0x5a
65#define ICH6_REG_RIRBCTL 0x5c 65#define AZX_REG_RIRBCTL 0x5c
66#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ 66#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
67#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ 67#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */
68#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ 68#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
69#define ICH6_REG_RIRBSTS 0x5d 69#define AZX_REG_RIRBSTS 0x5d
70#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ 70#define AZX_RBSTS_IRQ (1 << 0) /* response irq */
71#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ 71#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */
72#define ICH6_REG_RIRBSIZE 0x5e 72#define AZX_REG_RIRBSIZE 0x5e
73 73
74#define ICH6_REG_IC 0x60 74#define AZX_REG_IC 0x60
75#define ICH6_REG_IR 0x64 75#define AZX_REG_IR 0x64
76#define ICH6_REG_IRS 0x68 76#define AZX_REG_IRS 0x68
77#define ICH6_IRS_VALID (1<<1) 77#define AZX_IRS_VALID (1<<1)
78#define ICH6_IRS_BUSY (1<<0) 78#define AZX_IRS_BUSY (1<<0)
79 79
80#define ICH6_REG_DPLBASE 0x70 80#define AZX_REG_DPLBASE 0x70
81#define ICH6_REG_DPUBASE 0x74 81#define AZX_REG_DPUBASE 0x74
82#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 82#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */
83 83
84/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 84/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
85enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 85enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
86 86
87/* stream register offsets from stream base */ 87/* stream register offsets from stream base */
88#define ICH6_REG_SD_CTL 0x00 88#define AZX_REG_SD_CTL 0x00
89#define ICH6_REG_SD_STS 0x03 89#define AZX_REG_SD_STS 0x03
90#define ICH6_REG_SD_LPIB 0x04 90#define AZX_REG_SD_LPIB 0x04
91#define ICH6_REG_SD_CBL 0x08 91#define AZX_REG_SD_CBL 0x08
92#define ICH6_REG_SD_LVI 0x0c 92#define AZX_REG_SD_LVI 0x0c
93#define ICH6_REG_SD_FIFOW 0x0e 93#define AZX_REG_SD_FIFOW 0x0e
94#define ICH6_REG_SD_FIFOSIZE 0x10 94#define AZX_REG_SD_FIFOSIZE 0x10
95#define ICH6_REG_SD_FORMAT 0x12 95#define AZX_REG_SD_FORMAT 0x12
96#define ICH6_REG_SD_BDLPL 0x18 96#define AZX_REG_SD_BDLPL 0x18
97#define ICH6_REG_SD_BDLPU 0x1c 97#define AZX_REG_SD_BDLPU 0x1c
98 98
99/* PCI space */ 99/* PCI space */
100#define ICH6_PCIREG_TCSEL 0x44 100#define AZX_PCIREG_TCSEL 0x44
101 101
102/* 102/*
103 * other constants 103 * other constants
104 */ 104 */
105 105
106/* max number of SDs */
107/* ICH, ATI and VIA have 4 playback and 4 capture */
108#define ICH6_NUM_CAPTURE 4
109#define ICH6_NUM_PLAYBACK 4
110
111/* ULI has 6 playback and 5 capture */
112#define ULI_NUM_CAPTURE 5
113#define ULI_NUM_PLAYBACK 6
114
115/* ATI HDMI may have up to 8 playbacks and 0 capture */
116#define ATIHDMI_NUM_CAPTURE 0
117#define ATIHDMI_NUM_PLAYBACK 8
118
119/* TERA has 4 playback and 3 capture */
120#define TERA_NUM_CAPTURE 3
121#define TERA_NUM_PLAYBACK 4
122
123/* this number is statically defined for simplicity */
124#define MAX_AZX_DEV 16
125
126/* max number of fragments - we may use more if allocating more pages for BDL */ 106/* max number of fragments - we may use more if allocating more pages for BDL */
127#define BDL_SIZE 4096 107#define BDL_SIZE 4096
128#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 108#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
@@ -160,13 +140,13 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
160#define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 140#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
161 141
162/* INTCTL and INTSTS */ 142/* INTCTL and INTSTS */
163#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ 143#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */
164#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 144#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
165#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 145#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
166 146
167/* below are so far hardcoded - should read registers in future */ 147/* below are so far hardcoded - should read registers in future */
168#define ICH6_MAX_CORB_ENTRIES 256 148#define AZX_MAX_CORB_ENTRIES 256
169#define ICH6_MAX_RIRB_ENTRIES 256 149#define AZX_MAX_RIRB_ENTRIES 256
170 150
171/* driver quirks (capabilities) */ 151/* driver quirks (capabilities) */
172/* bits 0-7 are used for indicating driver type */ 152/* bits 0-7 are used for indicating driver type */
@@ -191,35 +171,6 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
191#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */ 171#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
192#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */ 172#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
193 173
194/* position fix mode */
195enum {
196 POS_FIX_AUTO,
197 POS_FIX_LPIB,
198 POS_FIX_POSBUF,
199 POS_FIX_VIACOMBO,
200 POS_FIX_COMBO,
201};
202
203/* Defines for ATI HD Audio support in SB450 south bridge */
204#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
205#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
206
207/* Defines for Nvidia HDA support */
208#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
209#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
210#define NVIDIA_HDA_ISTRM_COH 0x4d
211#define NVIDIA_HDA_OSTRM_COH 0x4c
212#define NVIDIA_HDA_ENABLE_COHBIT 0x01
213
214/* Defines for Intel SCH HDA snoop control */
215#define INTEL_SCH_HDA_DEVC 0x78
216#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
217
218/* Define IN stream 0 FIFO size offset in VIA controller */
219#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
220/* Define VIA HD Audio Device ID*/
221#define VIA_HDAC_DEVICE_ID 0x3288
222
223/* HD Audio class code */ 174/* HD Audio class code */
224#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 175#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
225 176
@@ -324,6 +275,9 @@ struct azx_pcm {
324 struct list_head list; 275 struct list_head list;
325}; 276};
326 277
278typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
279typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
280
327struct azx { 281struct azx {
328 struct snd_card *card; 282 struct snd_card *card;
329 struct pci_dev *pci; 283 struct pci_dev *pci;
@@ -342,6 +296,10 @@ struct azx {
342 /* Register interaction. */ 296 /* Register interaction. */
343 const struct hda_controller_ops *ops; 297 const struct hda_controller_ops *ops;
344 298
299 /* position adjustment callbacks */
300 azx_get_pos_callback_t get_position[2];
301 azx_get_delay_callback_t get_delay[2];
302
345 /* pci resources */ 303 /* pci resources */
346 unsigned long addr; 304 unsigned long addr;
347 void __iomem *remap_addr; 305 void __iomem *remap_addr;
@@ -350,7 +308,6 @@ struct azx {
350 /* locks */ 308 /* locks */
351 spinlock_t reg_lock; 309 spinlock_t reg_lock;
352 struct mutex open_mutex; /* Prevents concurrent open/close operations */ 310 struct mutex open_mutex; /* Prevents concurrent open/close operations */
353 struct completion probe_wait;
354 311
355 /* streams (x num_streams) */ 312 /* streams (x num_streams) */
356 struct azx_dev *azx_dev; 313 struct azx_dev *azx_dev;
@@ -377,7 +334,6 @@ struct azx {
377#endif 334#endif
378 335
379 /* flags */ 336 /* flags */
380 int position_fix[2]; /* for both playback/capture streams */
381 const int *bdl_pos_adj; 337 const int *bdl_pos_adj;
382 int poll_count; 338 int poll_count;
383 unsigned int running:1; 339 unsigned int running:1;
@@ -385,46 +341,23 @@ struct azx {
385 unsigned int single_cmd:1; 341 unsigned int single_cmd:1;
386 unsigned int polling_mode:1; 342 unsigned int polling_mode:1;
387 unsigned int msi:1; 343 unsigned int msi:1;
388 unsigned int irq_pending_warned:1;
389 unsigned int probing:1; /* codec probing phase */ 344 unsigned int probing:1; /* codec probing phase */
390 unsigned int snoop:1; 345 unsigned int snoop:1;
391 unsigned int align_buffer_size:1; 346 unsigned int align_buffer_size:1;
392 unsigned int region_requested:1; 347 unsigned int region_requested:1;
393
394 /* VGA-switcheroo setup */
395 unsigned int use_vga_switcheroo:1;
396 unsigned int vga_switcheroo_registered:1;
397 unsigned int init_failed:1; /* delayed init failed */
398 unsigned int disabled:1; /* disabled by VGA-switcher */ 348 unsigned int disabled:1; /* disabled by VGA-switcher */
399 349
400 /* for debugging */ 350 /* for debugging */
401 unsigned int last_cmd[AZX_MAX_CODECS]; 351 unsigned int last_cmd[AZX_MAX_CODECS];
402 352
403 /* for pending irqs */
404 struct work_struct irq_pending_work;
405
406 struct work_struct probe_work;
407
408 /* reboot notifier (for mysterious hangup problem at power-down) */ 353 /* reboot notifier (for mysterious hangup problem at power-down) */
409 struct notifier_block reboot_notifier; 354 struct notifier_block reboot_notifier;
410 355
411 /* card list (for power_save trigger) */
412 struct list_head list;
413
414#ifdef CONFIG_SND_HDA_DSP_LOADER 356#ifdef CONFIG_SND_HDA_DSP_LOADER
415 struct azx_dev saved_azx_dev; 357 struct azx_dev saved_azx_dev;
416#endif 358#endif
417
418 /* secondary power domain for hdmi audio under vga device */
419 struct dev_pm_domain hdmi_pm_domain;
420}; 359};
421 360
422#ifdef CONFIG_SND_VERBOSE_PRINTK
423#define SFX /* nop */
424#else
425#define SFX "hda-intel "
426#endif
427
428#ifdef CONFIG_X86 361#ifdef CONFIG_X86
429#define azx_snoop(chip) ((chip)->snoop) 362#define azx_snoop(chip) ((chip)->snoop)
430#else 363#else
@@ -436,29 +369,29 @@ struct azx {
436 */ 369 */
437 370
438#define azx_writel(chip, reg, value) \ 371#define azx_writel(chip, reg, value) \
439 ((chip)->ops->reg_writel(value, (chip)->remap_addr + ICH6_REG_##reg)) 372 ((chip)->ops->reg_writel(value, (chip)->remap_addr + AZX_REG_##reg))
440#define azx_readl(chip, reg) \ 373#define azx_readl(chip, reg) \
441 ((chip)->ops->reg_readl((chip)->remap_addr + ICH6_REG_##reg)) 374 ((chip)->ops->reg_readl((chip)->remap_addr + AZX_REG_##reg))
442#define azx_writew(chip, reg, value) \ 375#define azx_writew(chip, reg, value) \
443 ((chip)->ops->reg_writew(value, (chip)->remap_addr + ICH6_REG_##reg)) 376 ((chip)->ops->reg_writew(value, (chip)->remap_addr + AZX_REG_##reg))
444#define azx_readw(chip, reg) \ 377#define azx_readw(chip, reg) \
445 ((chip)->ops->reg_readw((chip)->remap_addr + ICH6_REG_##reg)) 378 ((chip)->ops->reg_readw((chip)->remap_addr + AZX_REG_##reg))
446#define azx_writeb(chip, reg, value) \ 379#define azx_writeb(chip, reg, value) \
447 ((chip)->ops->reg_writeb(value, (chip)->remap_addr + ICH6_REG_##reg)) 380 ((chip)->ops->reg_writeb(value, (chip)->remap_addr + AZX_REG_##reg))
448#define azx_readb(chip, reg) \ 381#define azx_readb(chip, reg) \
449 ((chip)->ops->reg_readb((chip)->remap_addr + ICH6_REG_##reg)) 382 ((chip)->ops->reg_readb((chip)->remap_addr + AZX_REG_##reg))
450 383
451#define azx_sd_writel(chip, dev, reg, value) \ 384#define azx_sd_writel(chip, dev, reg, value) \
452 ((chip)->ops->reg_writel(value, (dev)->sd_addr + ICH6_REG_##reg)) 385 ((chip)->ops->reg_writel(value, (dev)->sd_addr + AZX_REG_##reg))
453#define azx_sd_readl(chip, dev, reg) \ 386#define azx_sd_readl(chip, dev, reg) \
454 ((chip)->ops->reg_readl((dev)->sd_addr + ICH6_REG_##reg)) 387 ((chip)->ops->reg_readl((dev)->sd_addr + AZX_REG_##reg))
455#define azx_sd_writew(chip, dev, reg, value) \ 388#define azx_sd_writew(chip, dev, reg, value) \
456 ((chip)->ops->reg_writew(value, (dev)->sd_addr + ICH6_REG_##reg)) 389 ((chip)->ops->reg_writew(value, (dev)->sd_addr + AZX_REG_##reg))
457#define azx_sd_readw(chip, dev, reg) \ 390#define azx_sd_readw(chip, dev, reg) \
458 ((chip)->ops->reg_readw((dev)->sd_addr + ICH6_REG_##reg)) 391 ((chip)->ops->reg_readw((dev)->sd_addr + AZX_REG_##reg))
459#define azx_sd_writeb(chip, dev, reg, value) \ 392#define azx_sd_writeb(chip, dev, reg, value) \
460 ((chip)->ops->reg_writeb(value, (dev)->sd_addr + ICH6_REG_##reg)) 393 ((chip)->ops->reg_writeb(value, (dev)->sd_addr + AZX_REG_##reg))
461#define azx_sd_readb(chip, dev, reg) \ 394#define azx_sd_readb(chip, dev, reg) \
462 ((chip)->ops->reg_readb((dev)->sd_addr + ICH6_REG_##reg)) 395 ((chip)->ops->reg_readb((dev)->sd_addr + AZX_REG_##reg))
463 396
464#endif /* __SOUND_HDA_PRIV_H */ 397#endif /* __SOUND_HDA_PRIV_H */
diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c
index a366ba9293a8..cf69dafa91c0 100644
--- a/sound/pci/hda/hda_tegra.c
+++ b/sound/pci/hda/hda_tegra.c
@@ -29,7 +29,6 @@
29#include <linux/moduleparam.h> 29#include <linux/moduleparam.h>
30#include <linux/mutex.h> 30#include <linux/mutex.h>
31#include <linux/of_device.h> 31#include <linux/of_device.h>
32#include <linux/reboot.h>
33#include <linux/slab.h> 32#include <linux/slab.h>
34#include <linux/time.h> 33#include <linux/time.h>
35 34
@@ -295,30 +294,6 @@ static const struct dev_pm_ops hda_tegra_pm = {
295}; 294};
296 295
297/* 296/*
298 * reboot notifier for hang-up problem at power-down
299 */
300static int hda_tegra_halt(struct notifier_block *nb, unsigned long event,
301 void *buf)
302{
303 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
304 snd_hda_bus_reboot_notify(chip->bus);
305 azx_stop_chip(chip);
306 return NOTIFY_OK;
307}
308
309static void hda_tegra_notifier_register(struct azx *chip)
310{
311 chip->reboot_notifier.notifier_call = hda_tegra_halt;
312 register_reboot_notifier(&chip->reboot_notifier);
313}
314
315static void hda_tegra_notifier_unregister(struct azx *chip)
316{
317 if (chip->reboot_notifier.notifier_call)
318 unregister_reboot_notifier(&chip->reboot_notifier);
319}
320
321/*
322 * destructor 297 * destructor
323 */ 298 */
324static int hda_tegra_dev_free(struct snd_device *device) 299static int hda_tegra_dev_free(struct snd_device *device)
@@ -326,7 +301,7 @@ static int hda_tegra_dev_free(struct snd_device *device)
326 int i; 301 int i;
327 struct azx *chip = device->device_data; 302 struct azx *chip = device->device_data;
328 303
329 hda_tegra_notifier_unregister(chip); 304 azx_notifier_unregister(chip);
330 305
331 if (chip->initialized) { 306 if (chip->initialized) {
332 for (i = 0; i < chip->num_streams; i++) 307 for (i = 0; i < chip->num_streams; i++)
@@ -480,8 +455,6 @@ static int hda_tegra_create(struct snd_card *card,
480 INIT_LIST_HEAD(&chip->pcm_list); 455 INIT_LIST_HEAD(&chip->pcm_list);
481 INIT_LIST_HEAD(&chip->list); 456 INIT_LIST_HEAD(&chip->list);
482 457
483 chip->position_fix[0] = POS_FIX_AUTO;
484 chip->position_fix[1] = POS_FIX_AUTO;
485 chip->codec_probe_mask = -1; 458 chip->codec_probe_mask = -1;
486 459
487 chip->single_cmd = false; 460 chip->single_cmd = false;
@@ -559,7 +532,7 @@ static int hda_tegra_probe(struct platform_device *pdev)
559 532
560 chip->running = 1; 533 chip->running = 1;
561 power_down_all_codecs(chip); 534 power_down_all_codecs(chip);
562 hda_tegra_notifier_register(chip); 535 azx_notifier_register(chip);
563 536
564 return 0; 537 return 0;
565 538
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 02:42:30 -0500