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authorClemens Ladisch <clemens@ladisch.de>2006-01-13 01:41:45 -0500
committerJaroslav Kysela <perex@suse.cz>2006-01-22 10:24:14 -0500
commitfc80a2027afc31e8447a0691ea1279166ce5d69f (patch)
treeab91a002bb35c88784c2df155569f35d0dfd9cc2 /sound/pci
parentda79e44df4fff22c7f815687ea210b2324b3507c (diff)
[ALSA] ymfpci: fix SPDIF sample rate information
Modules: YMFPCI driver Set the (read only) sample rate field in the IEC958 mixer controls to 48 kHz (instead of 44.1 kHz) because that is the rate actually supported by the hardware. Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
Diffstat (limited to 'sound/pci')
-rw-r--r--sound/pci/ymfpci/ymfpci_main.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/sound/pci/ymfpci/ymfpci_main.c b/sound/pci/ymfpci/ymfpci_main.c
index 1dfc7233c6a8..a1aa74b79b3d 100644
--- a/sound/pci/ymfpci/ymfpci_main.c
+++ b/sound/pci/ymfpci/ymfpci_main.c
@@ -1229,6 +1229,7 @@ static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
1229 spin_lock_irq(&chip->reg_lock); 1229 spin_lock_irq(&chip->reg_lock);
1230 ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff; 1230 ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
1231 ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff; 1231 ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
1232 ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
1232 spin_unlock_irq(&chip->reg_lock); 1233 spin_unlock_irq(&chip->reg_lock);
1233 return 0; 1234 return 0;
1234} 1235}
@@ -1303,6 +1304,7 @@ static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1303 spin_lock_irq(&chip->reg_lock); 1304 spin_lock_irq(&chip->reg_lock);
1304 ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff; 1305 ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
1305 ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff; 1306 ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
1307 ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
1306 spin_unlock_irq(&chip->reg_lock); 1308 spin_unlock_irq(&chip->reg_lock);
1307 return 0; 1309 return 0;
1308} 1310}