aboutsummaryrefslogtreecommitdiffstats
path: root/sound/pci/oxygen/xonar_pcm179x.c
diff options
context:
space:
mode:
authorClemens Ladisch <clemens@ladisch.de>2011-01-10 10:07:11 -0500
committerTakashi Iwai <tiwai@suse.de>2011-01-10 10:46:17 -0500
commitd353eaa9a8133cdad8c1da23c84f9f529a23f0c2 (patch)
tree12ce94153ebd6427da811575e353a0a259a58cfd /sound/pci/oxygen/xonar_pcm179x.c
parentdd203fa97bd5df18dbb0af5acf3e9a8beea33f74 (diff)
ALSA: virtuoso: configure correct master clock frequency on the CS2000
The clock output of the CS2000, which is used as master clock for the DACs, was using half the actual master clock frequency for some reason. Using the theoretically correct frequency seems also to work in practice. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci/oxygen/xonar_pcm179x.c')
-rw-r--r--sound/pci/oxygen/xonar_pcm179x.c25
1 files changed, 12 insertions, 13 deletions
diff --git a/sound/pci/oxygen/xonar_pcm179x.c b/sound/pci/oxygen/xonar_pcm179x.c
index 2e31b81fc49f..fce55fa5b0b0 100644
--- a/sound/pci/oxygen/xonar_pcm179x.c
+++ b/sound/pci/oxygen/xonar_pcm179x.c
@@ -467,7 +467,7 @@ static void xonar_st_init(struct oxygen *chip)
467 467
468 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 468 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
469 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_I2S | 469 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_I2S |
470 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 | 470 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
471 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); 471 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
472 472
473 xonar_st_init_i2c(chip); 473 xonar_st_init_i2c(chip);
@@ -635,41 +635,40 @@ static void update_cs2000_rate(struct oxygen *chip, unsigned int rate)
635 u8 rate_mclk, reg; 635 u8 rate_mclk, reg;
636 636
637 switch (rate) { 637 switch (rate) {
638 /* XXX Why is the I2S A MCLK half the actual I2S MCLK? */
639 case 32000: 638 case 32000:
640 rate_mclk = OXYGEN_RATE_32000 | OXYGEN_I2S_MCLK_256; 639 rate_mclk = OXYGEN_RATE_32000 | OXYGEN_I2S_MCLK_512;
641 break; 640 break;
642 case 44100: 641 case 44100:
643 if (data->os_128) 642 if (data->os_128)
644 rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_256; 643 rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_512;
645 else 644 else
646 rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_128; 645 rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_256;
647 break; 646 break;
648 default: /* 48000 */ 647 default: /* 48000 */
649 if (data->os_128) 648 if (data->os_128)
650 rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_256; 649 rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_512;
651 else 650 else
652 rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_128; 651 rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_256;
653 break; 652 break;
654 case 64000: 653 case 64000:
655 rate_mclk = OXYGEN_RATE_32000 | OXYGEN_I2S_MCLK_256; 654 rate_mclk = OXYGEN_RATE_32000 | OXYGEN_I2S_MCLK_512;
656 break; 655 break;
657 case 88200: 656 case 88200:
658 rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_256; 657 rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_512;
659 break; 658 break;
660 case 96000: 659 case 96000:
661 rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_256; 660 rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_512;
662 break; 661 break;
663 case 176400: 662 case 176400:
664 rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_256; 663 rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_512;
665 break; 664 break;
666 case 192000: 665 case 192000:
667 rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_256; 666 rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_512;
668 break; 667 break;
669 } 668 }
670 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT, rate_mclk, 669 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT, rate_mclk,
671 OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_MCLK_MASK); 670 OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_MCLK_MASK);
672 if ((rate_mclk & OXYGEN_I2S_MCLK_MASK) <= OXYGEN_I2S_MCLK_128) 671 if ((rate_mclk & OXYGEN_I2S_MCLK_MASK) <= OXYGEN_I2S_MCLK_256)
673 reg = CS2000_REF_CLK_DIV_1; 672 reg = CS2000_REF_CLK_DIV_1;
674 else 673 else
675 reg = CS2000_REF_CLK_DIV_2; 674 reg = CS2000_REF_CLK_DIV_2;