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authorDylan Reid <dgreid@chromium.org>2014-02-28 18:41:22 -0500
committerTakashi Iwai <tiwai@suse.de>2014-03-01 05:22:17 -0500
commit05e848788e30b2ee0b2736b99b6e458b6c7a4e7d (patch)
tree30d49442fcbcef20ec6327567e6f3e3c3ed315fd /sound/pci/hda
parent8769b278610c71a32ae9662219b2f450d48a828c (diff)
ALSA: hda - Add hda_controller.c and move pcm ops from hda_intel
Pull the pcm_ops and the functions they use into a new hda_controller file. This is done to allow for other hda implementations besides PCI to use the same ops. The hda_controller file will house functionality related to HDA but independent of the bus used to talk to the controller. This currently shares dsp locking across the two files. This will be remedied in a following commit. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci/hda')
-rw-r--r--sound/pci/hda/Makefile4
-rw-r--r--sound/pci/hda/hda_controller.c1018
-rw-r--r--sound/pci/hda/hda_controller.h57
-rw-r--r--sound/pci/hda/hda_intel.c999
4 files changed, 1078 insertions, 1000 deletions
diff --git a/sound/pci/hda/Makefile b/sound/pci/hda/Makefile
index 083b338e0783..5deef4febdea 100644
--- a/sound/pci/hda/Makefile
+++ b/sound/pci/hda/Makefile
@@ -1,4 +1,4 @@
1snd-hda-intel-objs := hda_intel.o 1snd-hda-intel-objs := hda_controller.o hda_intel.o
2# for haswell power well 2# for haswell power well
3snd-hda-intel-$(CONFIG_SND_HDA_I915) += hda_i915.o 3snd-hda-intel-$(CONFIG_SND_HDA_I915) += hda_i915.o
4 4
@@ -9,7 +9,7 @@ snd-hda-codec-$(CONFIG_SND_HDA_INPUT_BEEP) += hda_beep.o
9 9
10# for trace-points 10# for trace-points
11CFLAGS_hda_codec.o := -I$(src) 11CFLAGS_hda_codec.o := -I$(src)
12CFLAGS_hda_intel.o := -I$(src) 12CFLAGS_hda_controller.o := -I$(src)
13 13
14snd-hda-codec-generic-objs := hda_generic.o 14snd-hda-codec-generic-objs := hda_generic.o
15snd-hda-codec-realtek-objs := patch_realtek.o 15snd-hda-codec-realtek-objs := patch_realtek.o
diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c
new file mode 100644
index 000000000000..fcc5c3063967
--- /dev/null
+++ b/sound/pci/hda/hda_controller.c
@@ -0,0 +1,1018 @@
1/*
2 *
3 * Implementation of primary alsa driver code base for Intel HD Audio.
4 *
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
6 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 *
21 */
22
23#include <linux/clocksource.h>
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/slab.h>
28#include <sound/core.h>
29#include <sound/initval.h>
30#include "hda_priv.h"
31#include "hda_controller.h"
32
33#define CREATE_TRACE_POINTS
34#include "hda_intel_trace.h"
35
36/*
37 * AZX stream operations.
38 */
39
40/* start a stream */
41void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
42{
43 /*
44 * Before stream start, initialize parameter
45 */
46 azx_dev->insufficient = 1;
47
48 /* enable SIE */
49 azx_writel(chip, INTCTL,
50 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
51 /* set DMA start and interrupt mask */
52 azx_sd_writeb(chip, azx_dev, SD_CTL,
53 azx_sd_readb(chip, azx_dev, SD_CTL) |
54 SD_CTL_DMA_START | SD_INT_MASK);
55}
56EXPORT_SYMBOL_GPL(azx_stream_start);
57
58/* stop DMA */
59static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
60{
61 azx_sd_writeb(chip, azx_dev, SD_CTL,
62 azx_sd_readb(chip, azx_dev, SD_CTL) &
63 ~(SD_CTL_DMA_START | SD_INT_MASK));
64 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
65}
66
67/* stop a stream */
68void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
69{
70 azx_stream_clear(chip, azx_dev);
71 /* disable SIE */
72 azx_writel(chip, INTCTL,
73 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
74}
75EXPORT_SYMBOL_GPL(azx_stream_stop);
76
77/* reset stream */
78void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
79{
80 unsigned char val;
81 int timeout;
82
83 azx_stream_clear(chip, azx_dev);
84
85 azx_sd_writeb(chip, azx_dev, SD_CTL,
86 azx_sd_readb(chip, azx_dev, SD_CTL) |
87 SD_CTL_STREAM_RESET);
88 udelay(3);
89 timeout = 300;
90 while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
91 SD_CTL_STREAM_RESET) && --timeout)
92 ;
93 val &= ~SD_CTL_STREAM_RESET;
94 azx_sd_writeb(chip, azx_dev, SD_CTL, val);
95 udelay(3);
96
97 timeout = 300;
98 /* waiting for hardware to report that the stream is out of reset */
99 while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
100 SD_CTL_STREAM_RESET) && --timeout)
101 ;
102
103 /* reset first position - may not be synced with hw at this time */
104 *azx_dev->posbuf = 0;
105}
106EXPORT_SYMBOL_GPL(azx_stream_reset);
107
108/*
109 * set up the SD for streaming
110 */
111int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
112{
113 unsigned int val;
114 /* make sure the run bit is zero for SD */
115 azx_stream_clear(chip, azx_dev);
116 /* program the stream_tag */
117 val = azx_sd_readl(chip, azx_dev, SD_CTL);
118 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
119 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
120 if (!azx_snoop(chip))
121 val |= SD_CTL_TRAFFIC_PRIO;
122 azx_sd_writel(chip, azx_dev, SD_CTL, val);
123
124 /* program the length of samples in cyclic buffer */
125 azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
126
127 /* program the stream format */
128 /* this value needs to be the same as the one programmed */
129 azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
130
131 /* program the stream LVI (last valid index) of the BDL */
132 azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
133
134 /* program the BDL address */
135 /* lower BDL address */
136 azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
137 /* upper BDL address */
138 azx_sd_writel(chip, azx_dev, SD_BDLPU,
139 upper_32_bits(azx_dev->bdl.addr));
140
141 /* enable the position buffer */
142 if (chip->position_fix[0] != POS_FIX_LPIB ||
143 chip->position_fix[1] != POS_FIX_LPIB) {
144 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
145 azx_writel(chip, DPLBASE,
146 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
147 }
148
149 /* set the interrupt enable bits in the descriptor control register */
150 azx_sd_writel(chip, azx_dev, SD_CTL,
151 azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
152
153 return 0;
154}
155EXPORT_SYMBOL_GPL(azx_setup_controller);
156
157/* assign a stream for the PCM */
158static inline struct azx_dev *
159azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
160{
161 int dev, i, nums;
162 struct azx_dev *res = NULL;
163 /* make a non-zero unique key for the substream */
164 int key = (substream->pcm->device << 16) | (substream->number << 2) |
165 (substream->stream + 1);
166
167 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
168 dev = chip->playback_index_offset;
169 nums = chip->playback_streams;
170 } else {
171 dev = chip->capture_index_offset;
172 nums = chip->capture_streams;
173 }
174 for (i = 0; i < nums; i++, dev++) {
175 struct azx_dev *azx_dev = &chip->azx_dev[dev];
176 dsp_lock(azx_dev);
177 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
178 res = azx_dev;
179 if (res->assigned_key == key) {
180 res->opened = 1;
181 res->assigned_key = key;
182 dsp_unlock(azx_dev);
183 return azx_dev;
184 }
185 }
186 dsp_unlock(azx_dev);
187 }
188 if (res) {
189 dsp_lock(res);
190 res->opened = 1;
191 res->assigned_key = key;
192 dsp_unlock(res);
193 }
194 return res;
195}
196
197/* release the assigned stream */
198static inline void azx_release_device(struct azx_dev *azx_dev)
199{
200 azx_dev->opened = 0;
201}
202
203static cycle_t azx_cc_read(const struct cyclecounter *cc)
204{
205 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
206 struct snd_pcm_substream *substream = azx_dev->substream;
207 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
208 struct azx *chip = apcm->chip;
209
210 return azx_readl(chip, WALLCLK);
211}
212
213static void azx_timecounter_init(struct snd_pcm_substream *substream,
214 bool force, cycle_t last)
215{
216 struct azx_dev *azx_dev = get_azx_dev(substream);
217 struct timecounter *tc = &azx_dev->azx_tc;
218 struct cyclecounter *cc = &azx_dev->azx_cc;
219 u64 nsec;
220
221 cc->read = azx_cc_read;
222 cc->mask = CLOCKSOURCE_MASK(32);
223
224 /*
225 * Converting from 24 MHz to ns means applying a 125/3 factor.
226 * To avoid any saturation issues in intermediate operations,
227 * the 125 factor is applied first. The division is applied
228 * last after reading the timecounter value.
229 * Applying the 1/3 factor as part of the multiplication
230 * requires at least 20 bits for a decent precision, however
231 * overflows occur after about 4 hours or less, not a option.
232 */
233
234 cc->mult = 125; /* saturation after 195 years */
235 cc->shift = 0;
236
237 nsec = 0; /* audio time is elapsed time since trigger */
238 timecounter_init(tc, cc, nsec);
239 if (force)
240 /*
241 * force timecounter to use predefined value,
242 * used for synchronized starts
243 */
244 tc->cycle_last = last;
245}
246
247static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
248 u64 nsec)
249{
250 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
251 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
252 u64 codec_frames, codec_nsecs;
253
254 if (!hinfo->ops.get_delay)
255 return nsec;
256
257 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
258 codec_nsecs = div_u64(codec_frames * 1000000000LL,
259 substream->runtime->rate);
260
261 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
262 return nsec + codec_nsecs;
263
264 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
265}
266
267/*
268 * set up a BDL entry
269 */
270int setup_bdle(struct azx *chip,
271 struct snd_dma_buffer *dmab,
272 struct azx_dev *azx_dev, u32 **bdlp,
273 int ofs, int size, int with_ioc)
274{
275 u32 *bdl = *bdlp;
276
277 while (size > 0) {
278 dma_addr_t addr;
279 int chunk;
280
281 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
282 return -EINVAL;
283
284 addr = snd_sgbuf_get_addr(dmab, ofs);
285 /* program the address field of the BDL entry */
286 bdl[0] = cpu_to_le32((u32)addr);
287 bdl[1] = cpu_to_le32(upper_32_bits(addr));
288 /* program the size field of the BDL entry */
289 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
290 /* one BDLE cannot cross 4K boundary on CTHDA chips */
291 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
292 u32 remain = 0x1000 - (ofs & 0xfff);
293 if (chunk > remain)
294 chunk = remain;
295 }
296 bdl[2] = cpu_to_le32(chunk);
297 /* program the IOC to enable interrupt
298 * only when the whole fragment is processed
299 */
300 size -= chunk;
301 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
302 bdl += 4;
303 azx_dev->frags++;
304 ofs += chunk;
305 }
306 *bdlp = bdl;
307 return ofs;
308}
309EXPORT_SYMBOL_GPL(setup_bdle);
310
311/*
312 * set up BDL entries
313 */
314static int azx_setup_periods(struct azx *chip,
315 struct snd_pcm_substream *substream,
316 struct azx_dev *azx_dev)
317{
318 u32 *bdl;
319 int i, ofs, periods, period_bytes;
320 int pos_adj = 0;
321
322 /* reset BDL address */
323 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
324 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
325
326 period_bytes = azx_dev->period_bytes;
327 periods = azx_dev->bufsize / period_bytes;
328
329 /* program the initial BDL entries */
330 bdl = (u32 *)azx_dev->bdl.area;
331 ofs = 0;
332 azx_dev->frags = 0;
333
334 if (chip->bdl_pos_adj)
335 pos_adj = chip->bdl_pos_adj[chip->dev_index];
336 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
337 struct snd_pcm_runtime *runtime = substream->runtime;
338 int pos_align = pos_adj;
339 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
340 if (!pos_adj)
341 pos_adj = pos_align;
342 else
343 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
344 pos_align;
345 pos_adj = frames_to_bytes(runtime, pos_adj);
346 if (pos_adj >= period_bytes) {
347 dev_warn(chip->card->dev,"Too big adjustment %d\n",
348 pos_adj);
349 pos_adj = 0;
350 } else {
351 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
352 azx_dev,
353 &bdl, ofs, pos_adj, true);
354 if (ofs < 0)
355 goto error;
356 }
357 } else
358 pos_adj = 0;
359
360 for (i = 0; i < periods; i++) {
361 if (i == periods - 1 && pos_adj)
362 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
363 azx_dev, &bdl, ofs,
364 period_bytes - pos_adj, 0);
365 else
366 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
367 azx_dev, &bdl, ofs,
368 period_bytes,
369 !azx_dev->no_period_wakeup);
370 if (ofs < 0)
371 goto error;
372 }
373 return 0;
374
375 error:
376 dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
377 azx_dev->bufsize, period_bytes);
378 return -EINVAL;
379}
380
381/*
382 * PCM ops
383 */
384
385static int azx_pcm_close(struct snd_pcm_substream *substream)
386{
387 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
388 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
389 struct azx *chip = apcm->chip;
390 struct azx_dev *azx_dev = get_azx_dev(substream);
391 unsigned long flags;
392
393 mutex_lock(&chip->open_mutex);
394 spin_lock_irqsave(&chip->reg_lock, flags);
395 azx_dev->substream = NULL;
396 azx_dev->running = 0;
397 spin_unlock_irqrestore(&chip->reg_lock, flags);
398 azx_release_device(azx_dev);
399 hinfo->ops.close(hinfo, apcm->codec, substream);
400 snd_hda_power_down(apcm->codec);
401 mutex_unlock(&chip->open_mutex);
402 return 0;
403}
404
405static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
406 struct snd_pcm_hw_params *hw_params)
407{
408 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
409 struct azx *chip = apcm->chip;
410 int ret;
411
412 dsp_lock(get_azx_dev(substream));
413 if (dsp_is_locked(get_azx_dev(substream))) {
414 ret = -EBUSY;
415 goto unlock;
416 }
417
418 ret = chip->ops->substream_alloc_pages(chip, substream,
419 params_buffer_bytes(hw_params));
420unlock:
421 dsp_unlock(get_azx_dev(substream));
422 return ret;
423}
424
425static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
426{
427 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
428 struct azx_dev *azx_dev = get_azx_dev(substream);
429 struct azx *chip = apcm->chip;
430 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
431 int err;
432
433 /* reset BDL address */
434 dsp_lock(azx_dev);
435 if (!dsp_is_locked(azx_dev)) {
436 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
437 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
438 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
439 azx_dev->bufsize = 0;
440 azx_dev->period_bytes = 0;
441 azx_dev->format_val = 0;
442 }
443
444 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
445
446 err = chip->ops->substream_free_pages(chip, substream);
447 azx_dev->prepared = 0;
448 dsp_unlock(azx_dev);
449 return err;
450}
451
452static int azx_pcm_prepare(struct snd_pcm_substream *substream)
453{
454 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
455 struct azx *chip = apcm->chip;
456 struct azx_dev *azx_dev = get_azx_dev(substream);
457 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
458 struct snd_pcm_runtime *runtime = substream->runtime;
459 unsigned int bufsize, period_bytes, format_val, stream_tag;
460 int err;
461 struct hda_spdif_out *spdif =
462 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
463 unsigned short ctls = spdif ? spdif->ctls : 0;
464
465 dsp_lock(azx_dev);
466 if (dsp_is_locked(azx_dev)) {
467 err = -EBUSY;
468 goto unlock;
469 }
470
471 azx_stream_reset(chip, azx_dev);
472 format_val = snd_hda_calc_stream_format(runtime->rate,
473 runtime->channels,
474 runtime->format,
475 hinfo->maxbps,
476 ctls);
477 if (!format_val) {
478 dev_err(chip->card->dev,
479 "invalid format_val, rate=%d, ch=%d, format=%d\n",
480 runtime->rate, runtime->channels, runtime->format);
481 err = -EINVAL;
482 goto unlock;
483 }
484
485 bufsize = snd_pcm_lib_buffer_bytes(substream);
486 period_bytes = snd_pcm_lib_period_bytes(substream);
487
488 dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
489 bufsize, format_val);
490
491 if (bufsize != azx_dev->bufsize ||
492 period_bytes != azx_dev->period_bytes ||
493 format_val != azx_dev->format_val ||
494 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
495 azx_dev->bufsize = bufsize;
496 azx_dev->period_bytes = period_bytes;
497 azx_dev->format_val = format_val;
498 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
499 err = azx_setup_periods(chip, substream, azx_dev);
500 if (err < 0)
501 goto unlock;
502 }
503
504 /* when LPIB delay correction gives a small negative value,
505 * we ignore it; currently set the threshold statically to
506 * 64 frames
507 */
508 if (runtime->period_size > 64)
509 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
510 else
511 azx_dev->delay_negative_threshold = 0;
512
513 /* wallclk has 24Mhz clock source */
514 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
515 runtime->rate) * 1000);
516 azx_setup_controller(chip, azx_dev);
517 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
518 azx_dev->fifo_size =
519 azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
520 else
521 azx_dev->fifo_size = 0;
522
523 stream_tag = azx_dev->stream_tag;
524 /* CA-IBG chips need the playback stream starting from 1 */
525 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
526 stream_tag > chip->capture_streams)
527 stream_tag -= chip->capture_streams;
528 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
529 azx_dev->format_val, substream);
530
531 unlock:
532 if (!err)
533 azx_dev->prepared = 1;
534 dsp_unlock(azx_dev);
535 return err;
536}
537
538static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
539{
540 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
541 struct azx *chip = apcm->chip;
542 struct azx_dev *azx_dev;
543 struct snd_pcm_substream *s;
544 int rstart = 0, start, nsync = 0, sbits = 0;
545 int nwait, timeout;
546
547 azx_dev = get_azx_dev(substream);
548 trace_azx_pcm_trigger(chip, azx_dev, cmd);
549
550 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
551 return -EPIPE;
552
553 switch (cmd) {
554 case SNDRV_PCM_TRIGGER_START:
555 rstart = 1;
556 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
557 case SNDRV_PCM_TRIGGER_RESUME:
558 start = 1;
559 break;
560 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
561 case SNDRV_PCM_TRIGGER_SUSPEND:
562 case SNDRV_PCM_TRIGGER_STOP:
563 start = 0;
564 break;
565 default:
566 return -EINVAL;
567 }
568
569 snd_pcm_group_for_each_entry(s, substream) {
570 if (s->pcm->card != substream->pcm->card)
571 continue;
572 azx_dev = get_azx_dev(s);
573 sbits |= 1 << azx_dev->index;
574 nsync++;
575 snd_pcm_trigger_done(s, substream);
576 }
577
578 spin_lock(&chip->reg_lock);
579
580 /* first, set SYNC bits of corresponding streams */
581 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
582 azx_writel(chip, OLD_SSYNC,
583 azx_readl(chip, OLD_SSYNC) | sbits);
584 else
585 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
586
587 snd_pcm_group_for_each_entry(s, substream) {
588 if (s->pcm->card != substream->pcm->card)
589 continue;
590 azx_dev = get_azx_dev(s);
591 if (start) {
592 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
593 if (!rstart)
594 azx_dev->start_wallclk -=
595 azx_dev->period_wallclk;
596 azx_stream_start(chip, azx_dev);
597 } else {
598 azx_stream_stop(chip, azx_dev);
599 }
600 azx_dev->running = start;
601 }
602 spin_unlock(&chip->reg_lock);
603 if (start) {
604 /* wait until all FIFOs get ready */
605 for (timeout = 5000; timeout; timeout--) {
606 nwait = 0;
607 snd_pcm_group_for_each_entry(s, substream) {
608 if (s->pcm->card != substream->pcm->card)
609 continue;
610 azx_dev = get_azx_dev(s);
611 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
612 SD_STS_FIFO_READY))
613 nwait++;
614 }
615 if (!nwait)
616 break;
617 cpu_relax();
618 }
619 } else {
620 /* wait until all RUN bits are cleared */
621 for (timeout = 5000; timeout; timeout--) {
622 nwait = 0;
623 snd_pcm_group_for_each_entry(s, substream) {
624 if (s->pcm->card != substream->pcm->card)
625 continue;
626 azx_dev = get_azx_dev(s);
627 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
628 SD_CTL_DMA_START)
629 nwait++;
630 }
631 if (!nwait)
632 break;
633 cpu_relax();
634 }
635 }
636 spin_lock(&chip->reg_lock);
637 /* reset SYNC bits */
638 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
639 azx_writel(chip, OLD_SSYNC,
640 azx_readl(chip, OLD_SSYNC) & ~sbits);
641 else
642 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
643 if (start) {
644 azx_timecounter_init(substream, 0, 0);
645 if (nsync > 1) {
646 cycle_t cycle_last;
647
648 /* same start cycle for master and group */
649 azx_dev = get_azx_dev(substream);
650 cycle_last = azx_dev->azx_tc.cycle_last;
651
652 snd_pcm_group_for_each_entry(s, substream) {
653 if (s->pcm->card != substream->pcm->card)
654 continue;
655 azx_timecounter_init(s, 1, cycle_last);
656 }
657 }
658 }
659 spin_unlock(&chip->reg_lock);
660 return 0;
661}
662
663/* get the current DMA position with correction on VIA chips */
664static unsigned int azx_via_get_position(struct azx *chip,
665 struct azx_dev *azx_dev)
666{
667 unsigned int link_pos, mini_pos, bound_pos;
668 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
669 unsigned int fifo_size;
670
671 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
672 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
673 /* Playback, no problem using link position */
674 return link_pos;
675 }
676
677 /* Capture */
678 /* For new chipset,
679 * use mod to get the DMA position just like old chipset
680 */
681 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
682 mod_dma_pos %= azx_dev->period_bytes;
683
684 /* azx_dev->fifo_size can't get FIFO size of in stream.
685 * Get from base address + offset.
686 */
687 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
688
689 if (azx_dev->insufficient) {
690 /* Link position never gather than FIFO size */
691 if (link_pos <= fifo_size)
692 return 0;
693
694 azx_dev->insufficient = 0;
695 }
696
697 if (link_pos <= fifo_size)
698 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
699 else
700 mini_pos = link_pos - fifo_size;
701
702 /* Find nearest previous boudary */
703 mod_mini_pos = mini_pos % azx_dev->period_bytes;
704 mod_link_pos = link_pos % azx_dev->period_bytes;
705 if (mod_link_pos >= fifo_size)
706 bound_pos = link_pos - mod_link_pos;
707 else if (mod_dma_pos >= mod_mini_pos)
708 bound_pos = mini_pos - mod_mini_pos;
709 else {
710 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
711 if (bound_pos >= azx_dev->bufsize)
712 bound_pos = 0;
713 }
714
715 /* Calculate real DMA position we want */
716 return bound_pos + mod_dma_pos;
717}
718
719unsigned int azx_get_position(struct azx *chip,
720 struct azx_dev *azx_dev,
721 bool with_check)
722{
723 struct snd_pcm_substream *substream = azx_dev->substream;
724 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
725 unsigned int pos;
726 int stream = substream->stream;
727 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
728 int delay = 0;
729
730 switch (chip->position_fix[stream]) {
731 case POS_FIX_LPIB:
732 /* read LPIB */
733 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
734 break;
735 case POS_FIX_VIACOMBO:
736 pos = azx_via_get_position(chip, azx_dev);
737 break;
738 default:
739 /* use the position buffer */
740 pos = le32_to_cpu(*azx_dev->posbuf);
741 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
742 if (!pos || pos == (u32)-1) {
743 dev_info(chip->card->dev,
744 "Invalid position buffer, using LPIB read method instead.\n");
745 chip->position_fix[stream] = POS_FIX_LPIB;
746 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
747 } else
748 chip->position_fix[stream] = POS_FIX_POSBUF;
749 }
750 break;
751 }
752
753 if (pos >= azx_dev->bufsize)
754 pos = 0;
755
756 /* calculate runtime delay from LPIB */
757 if (substream->runtime &&
758 chip->position_fix[stream] == POS_FIX_POSBUF &&
759 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
760 unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
761 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
762 delay = pos - lpib_pos;
763 else
764 delay = lpib_pos - pos;
765 if (delay < 0) {
766 if (delay >= azx_dev->delay_negative_threshold)
767 delay = 0;
768 else
769 delay += azx_dev->bufsize;
770 }
771 if (delay >= azx_dev->period_bytes) {
772 dev_info(chip->card->dev,
773 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
774 delay, azx_dev->period_bytes);
775 delay = 0;
776 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
777 }
778 delay = bytes_to_frames(substream->runtime, delay);
779 }
780
781 if (substream->runtime) {
782 if (hinfo->ops.get_delay)
783 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
784 substream);
785 substream->runtime->delay = delay;
786 }
787
788 trace_azx_get_position(chip, azx_dev, pos, delay);
789 return pos;
790}
791EXPORT_SYMBOL_GPL(azx_get_position);
792
793static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
794{
795 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
796 struct azx *chip = apcm->chip;
797 struct azx_dev *azx_dev = get_azx_dev(substream);
798 return bytes_to_frames(substream->runtime,
799 azx_get_position(chip, azx_dev, false));
800}
801
802static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
803 struct timespec *ts)
804{
805 struct azx_dev *azx_dev = get_azx_dev(substream);
806 u64 nsec;
807
808 nsec = timecounter_read(&azx_dev->azx_tc);
809 nsec = div_u64(nsec, 3); /* can be optimized */
810 nsec = azx_adjust_codec_delay(substream, nsec);
811
812 *ts = ns_to_timespec(nsec);
813
814 return 0;
815}
816
817static struct snd_pcm_hardware azx_pcm_hw = {
818 .info = (SNDRV_PCM_INFO_MMAP |
819 SNDRV_PCM_INFO_INTERLEAVED |
820 SNDRV_PCM_INFO_BLOCK_TRANSFER |
821 SNDRV_PCM_INFO_MMAP_VALID |
822 /* No full-resume yet implemented */
823 /* SNDRV_PCM_INFO_RESUME |*/
824 SNDRV_PCM_INFO_PAUSE |
825 SNDRV_PCM_INFO_SYNC_START |
826 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
827 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
828 .formats = SNDRV_PCM_FMTBIT_S16_LE,
829 .rates = SNDRV_PCM_RATE_48000,
830 .rate_min = 48000,
831 .rate_max = 48000,
832 .channels_min = 2,
833 .channels_max = 2,
834 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
835 .period_bytes_min = 128,
836 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
837 .periods_min = 2,
838 .periods_max = AZX_MAX_FRAG,
839 .fifo_size = 0,
840};
841
842static int azx_pcm_open(struct snd_pcm_substream *substream)
843{
844 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
845 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
846 struct azx *chip = apcm->chip;
847 struct azx_dev *azx_dev;
848 struct snd_pcm_runtime *runtime = substream->runtime;
849 unsigned long flags;
850 int err;
851 int buff_step;
852
853 mutex_lock(&chip->open_mutex);
854 azx_dev = azx_assign_device(chip, substream);
855 if (azx_dev == NULL) {
856 mutex_unlock(&chip->open_mutex);
857 return -EBUSY;
858 }
859 runtime->hw = azx_pcm_hw;
860 runtime->hw.channels_min = hinfo->channels_min;
861 runtime->hw.channels_max = hinfo->channels_max;
862 runtime->hw.formats = hinfo->formats;
863 runtime->hw.rates = hinfo->rates;
864 snd_pcm_limit_hw_rates(runtime);
865 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
866
867 /* avoid wrap-around with wall-clock */
868 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
869 20,
870 178000000);
871
872 if (chip->align_buffer_size)
873 /* constrain buffer sizes to be multiple of 128
874 bytes. This is more efficient in terms of memory
875 access but isn't required by the HDA spec and
876 prevents users from specifying exact period/buffer
877 sizes. For example for 44.1kHz, a period size set
878 to 20ms will be rounded to 19.59ms. */
879 buff_step = 128;
880 else
881 /* Don't enforce steps on buffer sizes, still need to
882 be multiple of 4 bytes (HDA spec). Tested on Intel
883 HDA controllers, may not work on all devices where
884 option needs to be disabled */
885 buff_step = 4;
886
887 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
888 buff_step);
889 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
890 buff_step);
891 snd_hda_power_up_d3wait(apcm->codec);
892 err = hinfo->ops.open(hinfo, apcm->codec, substream);
893 if (err < 0) {
894 azx_release_device(azx_dev);
895 snd_hda_power_down(apcm->codec);
896 mutex_unlock(&chip->open_mutex);
897 return err;
898 }
899 snd_pcm_limit_hw_rates(runtime);
900 /* sanity check */
901 if (snd_BUG_ON(!runtime->hw.channels_min) ||
902 snd_BUG_ON(!runtime->hw.channels_max) ||
903 snd_BUG_ON(!runtime->hw.formats) ||
904 snd_BUG_ON(!runtime->hw.rates)) {
905 azx_release_device(azx_dev);
906 hinfo->ops.close(hinfo, apcm->codec, substream);
907 snd_hda_power_down(apcm->codec);
908 mutex_unlock(&chip->open_mutex);
909 return -EINVAL;
910 }
911
912 /* disable WALLCLOCK timestamps for capture streams
913 until we figure out how to handle digital inputs */
914 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
915 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
916
917 spin_lock_irqsave(&chip->reg_lock, flags);
918 azx_dev->substream = substream;
919 azx_dev->running = 0;
920 spin_unlock_irqrestore(&chip->reg_lock, flags);
921
922 runtime->private_data = azx_dev;
923 snd_pcm_set_sync(substream);
924 mutex_unlock(&chip->open_mutex);
925 return 0;
926}
927
928static int azx_pcm_mmap(struct snd_pcm_substream *substream,
929 struct vm_area_struct *area)
930{
931 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
932 struct azx *chip = apcm->chip;
933 if (chip->ops->pcm_mmap_prepare)
934 chip->ops->pcm_mmap_prepare(substream, area);
935 return snd_pcm_lib_default_mmap(substream, area);
936}
937
938static struct snd_pcm_ops azx_pcm_ops = {
939 .open = azx_pcm_open,
940 .close = azx_pcm_close,
941 .ioctl = snd_pcm_lib_ioctl,
942 .hw_params = azx_pcm_hw_params,
943 .hw_free = azx_pcm_hw_free,
944 .prepare = azx_pcm_prepare,
945 .trigger = azx_pcm_trigger,
946 .pointer = azx_pcm_pointer,
947 .wall_clock = azx_get_wallclock_tstamp,
948 .mmap = azx_pcm_mmap,
949 .page = snd_pcm_sgbuf_ops_page,
950};
951
952static void azx_pcm_free(struct snd_pcm *pcm)
953{
954 struct azx_pcm *apcm = pcm->private_data;
955 if (apcm) {
956 list_del(&apcm->list);
957 kfree(apcm);
958 }
959}
960
961#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
962
963int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
964 struct hda_pcm *cpcm)
965{
966 struct azx *chip = bus->private_data;
967 struct snd_pcm *pcm;
968 struct azx_pcm *apcm;
969 int pcm_dev = cpcm->device;
970 unsigned int size;
971 int s, err;
972
973 list_for_each_entry(apcm, &chip->pcm_list, list) {
974 if (apcm->pcm->device == pcm_dev) {
975 dev_err(chip->card->dev, "PCM %d already exists\n",
976 pcm_dev);
977 return -EBUSY;
978 }
979 }
980 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
981 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
982 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
983 &pcm);
984 if (err < 0)
985 return err;
986 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
987 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
988 if (apcm == NULL)
989 return -ENOMEM;
990 apcm->chip = chip;
991 apcm->pcm = pcm;
992 apcm->codec = codec;
993 pcm->private_data = apcm;
994 pcm->private_free = azx_pcm_free;
995 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
996 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
997 list_add_tail(&apcm->list, &chip->pcm_list);
998 cpcm->pcm = pcm;
999 for (s = 0; s < 2; s++) {
1000 apcm->hinfo[s] = &cpcm->stream[s];
1001 if (cpcm->stream[s].substreams)
1002 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1003 }
1004 /* buffer pre-allocation */
1005 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1006 if (size > MAX_PREALLOC_SIZE)
1007 size = MAX_PREALLOC_SIZE;
1008 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1009 chip->card->dev,
1010 size, MAX_PREALLOC_SIZE);
1011 /* link to codec */
1012 pcm->dev = &codec->dev;
1013 return 0;
1014}
1015EXPORT_SYMBOL_GPL(azx_attach_pcm_stream);
1016
1017MODULE_LICENSE("GPL");
1018MODULE_DESCRIPTION("Common HDA driver funcitons");
diff --git a/sound/pci/hda/hda_controller.h b/sound/pci/hda/hda_controller.h
new file mode 100644
index 000000000000..a62cdde93a2b
--- /dev/null
+++ b/sound/pci/hda/hda_controller.h
@@ -0,0 +1,57 @@
1/*
2 * Common functionality for the alsa driver code base for HD Audio.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __SOUND_HDA_CONTROLLER_H
16#define __SOUND_HDA_CONTROLLER_H
17
18#include <sound/core.h>
19#include <sound/initval.h>
20#include "hda_codec.h"
21#include "hda_priv.h"
22
23/* PCM setup */
24int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
25 struct hda_pcm *cpcm);
26static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
27{
28 return substream->runtime->private_data;
29}
30unsigned int azx_get_position(struct azx *chip,
31 struct azx_dev *azx_dev,
32 bool with_check);
33
34/* Stream control. */
35void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev);
36void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev);
37void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev);
38int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev);
39int setup_bdle(struct azx *chip,
40 struct snd_dma_buffer *dmab,
41 struct azx_dev *azx_dev, u32 **bdlp,
42 int ofs, int size, int with_ioc);
43
44/* DSP lock helpers */
45#ifdef CONFIG_SND_HDA_DSP_LOADER
46#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
47#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
48#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
49#define dsp_is_locked(dev) ((dev)->locked)
50#else
51#define dsp_lock_init(dev) do {} while (0)
52#define dsp_lock(dev) do {} while (0)
53#define dsp_unlock(dev) do {} while (0)
54#define dsp_is_locked(dev) 0
55#endif
56
57#endif /* __SOUND_HDA_CONTROLLER_H */
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index aa8b765c9299..f86ee2bb4529 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -63,6 +63,7 @@
63#include <linux/firmware.h> 63#include <linux/firmware.h>
64#include "hda_codec.h" 64#include "hda_codec.h"
65#include "hda_i915.h" 65#include "hda_i915.h"
66#include "hda_controller.h"
66#include "hda_priv.h" 67#include "hda_priv.h"
67 68
68 69
@@ -203,22 +204,6 @@ MODULE_DESCRIPTION("Intel HDA driver");
203/* 204/*
204 */ 205 */
205 206
206/* DSP lock helpers */
207#ifdef CONFIG_SND_HDA_DSP_LOADER
208#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
209#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
210#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
211#define dsp_is_locked(dev) ((dev)->locked)
212#else
213#define dsp_lock_init(dev) do {} while (0)
214#define dsp_lock(dev) do {} while (0)
215#define dsp_unlock(dev) do {} while (0)
216#define dsp_is_locked(dev) 0
217#endif
218
219#define CREATE_TRACE_POINTS
220#include "hda_intel_trace.h"
221
222/* driver types */ 207/* driver types */
223enum { 208enum {
224 AZX_DRIVER_ICH, 209 AZX_DRIVER_ICH,
@@ -296,12 +281,6 @@ static char *driver_short_names[] = {
296 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 281 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
297}; 282};
298 283
299/* for pcm support */
300static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
301{
302 return substream->runtime->private_data;
303}
304
305#ifdef CONFIG_X86 284#ifdef CONFIG_X86
306static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 285static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
307{ 286{
@@ -880,42 +859,6 @@ static void azx_int_clear(struct azx *chip)
880 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 859 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
881} 860}
882 861
883/* start a stream */
884static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
885{
886 /*
887 * Before stream start, initialize parameter
888 */
889 azx_dev->insufficient = 1;
890
891 /* enable SIE */
892 azx_writel(chip, INTCTL,
893 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
894 /* set DMA start and interrupt mask */
895 azx_sd_writeb(chip, azx_dev, SD_CTL,
896 azx_sd_readb(chip, azx_dev, SD_CTL) |
897 SD_CTL_DMA_START | SD_INT_MASK);
898}
899
900/* stop DMA */
901static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
902{
903 azx_sd_writeb(chip, azx_dev, SD_CTL,
904 azx_sd_readb(chip, azx_dev, SD_CTL) &
905 ~(SD_CTL_DMA_START | SD_INT_MASK));
906 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
907}
908
909/* stop a stream */
910static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
911{
912 azx_stream_clear(chip, azx_dev);
913 /* disable SIE */
914 azx_writel(chip, INTCTL,
915 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
916}
917
918
919/* 862/*
920 * reset and start the controller registers 863 * reset and start the controller registers
921 */ 864 */
@@ -1088,198 +1031,6 @@ static irqreturn_t azx_interrupt(int irq, void *dev_id)
1088 return IRQ_HANDLED; 1031 return IRQ_HANDLED;
1089} 1032}
1090 1033
1091
1092/*
1093 * set up a BDL entry
1094 */
1095static int setup_bdle(struct azx *chip,
1096 struct snd_dma_buffer *dmab,
1097 struct azx_dev *azx_dev, u32 **bdlp,
1098 int ofs, int size, int with_ioc)
1099{
1100 u32 *bdl = *bdlp;
1101
1102 while (size > 0) {
1103 dma_addr_t addr;
1104 int chunk;
1105
1106 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1107 return -EINVAL;
1108
1109 addr = snd_sgbuf_get_addr(dmab, ofs);
1110 /* program the address field of the BDL entry */
1111 bdl[0] = cpu_to_le32((u32)addr);
1112 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1113 /* program the size field of the BDL entry */
1114 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1115 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1116 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1117 u32 remain = 0x1000 - (ofs & 0xfff);
1118 if (chunk > remain)
1119 chunk = remain;
1120 }
1121 bdl[2] = cpu_to_le32(chunk);
1122 /* program the IOC to enable interrupt
1123 * only when the whole fragment is processed
1124 */
1125 size -= chunk;
1126 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1127 bdl += 4;
1128 azx_dev->frags++;
1129 ofs += chunk;
1130 }
1131 *bdlp = bdl;
1132 return ofs;
1133}
1134
1135/*
1136 * set up BDL entries
1137 */
1138static int azx_setup_periods(struct azx *chip,
1139 struct snd_pcm_substream *substream,
1140 struct azx_dev *azx_dev)
1141{
1142 u32 *bdl;
1143 int i, ofs, periods, period_bytes;
1144 int pos_adj = 0;
1145
1146 /* reset BDL address */
1147 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1148 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1149
1150 period_bytes = azx_dev->period_bytes;
1151 periods = azx_dev->bufsize / period_bytes;
1152
1153 /* program the initial BDL entries */
1154 bdl = (u32 *)azx_dev->bdl.area;
1155 ofs = 0;
1156 azx_dev->frags = 0;
1157
1158 if (chip->bdl_pos_adj)
1159 pos_adj = chip->bdl_pos_adj[chip->dev_index];
1160 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1161 struct snd_pcm_runtime *runtime = substream->runtime;
1162 int pos_align = pos_adj;
1163 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1164 if (!pos_adj)
1165 pos_adj = pos_align;
1166 else
1167 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1168 pos_align;
1169 pos_adj = frames_to_bytes(runtime, pos_adj);
1170 if (pos_adj >= period_bytes) {
1171 dev_warn(chip->card->dev,"Too big adjustment %d\n",
1172 pos_adj);
1173 pos_adj = 0;
1174 } else {
1175 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1176 azx_dev,
1177 &bdl, ofs, pos_adj, true);
1178 if (ofs < 0)
1179 goto error;
1180 }
1181 } else
1182 pos_adj = 0;
1183
1184 for (i = 0; i < periods; i++) {
1185 if (i == periods - 1 && pos_adj)
1186 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1187 azx_dev, &bdl, ofs,
1188 period_bytes - pos_adj, 0);
1189 else
1190 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1191 azx_dev, &bdl, ofs,
1192 period_bytes,
1193 !azx_dev->no_period_wakeup);
1194 if (ofs < 0)
1195 goto error;
1196 }
1197 return 0;
1198
1199 error:
1200 dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
1201 azx_dev->bufsize, period_bytes);
1202 return -EINVAL;
1203}
1204
1205/* reset stream */
1206static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1207{
1208 unsigned char val;
1209 int timeout;
1210
1211 azx_stream_clear(chip, azx_dev);
1212
1213 azx_sd_writeb(chip, azx_dev, SD_CTL,
1214 azx_sd_readb(chip, azx_dev, SD_CTL) |
1215 SD_CTL_STREAM_RESET);
1216 udelay(3);
1217 timeout = 300;
1218 while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1219 SD_CTL_STREAM_RESET) && --timeout)
1220 ;
1221 val &= ~SD_CTL_STREAM_RESET;
1222 azx_sd_writeb(chip, azx_dev, SD_CTL, val);
1223 udelay(3);
1224
1225 timeout = 300;
1226 /* waiting for hardware to report that the stream is out of reset */
1227 while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1228 SD_CTL_STREAM_RESET) && --timeout)
1229 ;
1230
1231 /* reset first position - may not be synced with hw at this time */
1232 *azx_dev->posbuf = 0;
1233}
1234
1235/*
1236 * set up the SD for streaming
1237 */
1238static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1239{
1240 unsigned int val;
1241 /* make sure the run bit is zero for SD */
1242 azx_stream_clear(chip, azx_dev);
1243 /* program the stream_tag */
1244 val = azx_sd_readl(chip, azx_dev, SD_CTL);
1245 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1246 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1247 if (!azx_snoop(chip))
1248 val |= SD_CTL_TRAFFIC_PRIO;
1249 azx_sd_writel(chip, azx_dev, SD_CTL, val);
1250
1251 /* program the length of samples in cyclic buffer */
1252 azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
1253
1254 /* program the stream format */
1255 /* this value needs to be the same as the one programmed */
1256 azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
1257
1258 /* program the stream LVI (last valid index) of the BDL */
1259 azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
1260
1261 /* program the BDL address */
1262 /* lower BDL address */
1263 azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1264 /* upper BDL address */
1265 azx_sd_writel(chip, azx_dev, SD_BDLPU,
1266 upper_32_bits(azx_dev->bdl.addr));
1267
1268 /* enable the position buffer */
1269 if (chip->position_fix[0] != POS_FIX_LPIB ||
1270 chip->position_fix[1] != POS_FIX_LPIB) {
1271 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1272 azx_writel(chip, DPLBASE,
1273 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1274 }
1275
1276 /* set the interrupt enable bits in the descriptor control register */
1277 azx_sd_writel(chip, azx_dev, SD_CTL,
1278 azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
1279
1280 return 0;
1281}
1282
1283/* 1034/*
1284 * Probe the given codec address 1035 * Probe the given codec address
1285 */ 1036 */
@@ -1301,8 +1052,6 @@ static int probe_codec(struct azx *chip, int addr)
1301 return 0; 1052 return 0;
1302} 1053}
1303 1054
1304static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1305 struct hda_pcm *cpcm);
1306static void azx_stop_chip(struct azx *chip); 1055static void azx_stop_chip(struct azx *chip);
1307 1056
1308static void azx_bus_reset(struct hda_bus *bus) 1057static void azx_bus_reset(struct hda_bus *bus)
@@ -1449,663 +1198,6 @@ static int azx_codec_configure(struct azx *chip)
1449 return 0; 1198 return 0;
1450} 1199}
1451 1200
1452
1453/*
1454 * PCM support
1455 */
1456
1457/* assign a stream for the PCM */
1458static inline struct azx_dev *
1459azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1460{
1461 int dev, i, nums;
1462 struct azx_dev *res = NULL;
1463 /* make a non-zero unique key for the substream */
1464 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1465 (substream->stream + 1);
1466
1467 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1468 dev = chip->playback_index_offset;
1469 nums = chip->playback_streams;
1470 } else {
1471 dev = chip->capture_index_offset;
1472 nums = chip->capture_streams;
1473 }
1474 for (i = 0; i < nums; i++, dev++) {
1475 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1476 dsp_lock(azx_dev);
1477 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1478 res = azx_dev;
1479 if (res->assigned_key == key) {
1480 res->opened = 1;
1481 res->assigned_key = key;
1482 dsp_unlock(azx_dev);
1483 return azx_dev;
1484 }
1485 }
1486 dsp_unlock(azx_dev);
1487 }
1488 if (res) {
1489 dsp_lock(res);
1490 res->opened = 1;
1491 res->assigned_key = key;
1492 dsp_unlock(res);
1493 }
1494 return res;
1495}
1496
1497/* release the assigned stream */
1498static inline void azx_release_device(struct azx_dev *azx_dev)
1499{
1500 azx_dev->opened = 0;
1501}
1502
1503static cycle_t azx_cc_read(const struct cyclecounter *cc)
1504{
1505 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1506 struct snd_pcm_substream *substream = azx_dev->substream;
1507 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1508 struct azx *chip = apcm->chip;
1509
1510 return azx_readl(chip, WALLCLK);
1511}
1512
1513static void azx_timecounter_init(struct snd_pcm_substream *substream,
1514 bool force, cycle_t last)
1515{
1516 struct azx_dev *azx_dev = get_azx_dev(substream);
1517 struct timecounter *tc = &azx_dev->azx_tc;
1518 struct cyclecounter *cc = &azx_dev->azx_cc;
1519 u64 nsec;
1520
1521 cc->read = azx_cc_read;
1522 cc->mask = CLOCKSOURCE_MASK(32);
1523
1524 /*
1525 * Converting from 24 MHz to ns means applying a 125/3 factor.
1526 * To avoid any saturation issues in intermediate operations,
1527 * the 125 factor is applied first. The division is applied
1528 * last after reading the timecounter value.
1529 * Applying the 1/3 factor as part of the multiplication
1530 * requires at least 20 bits for a decent precision, however
1531 * overflows occur after about 4 hours or less, not a option.
1532 */
1533
1534 cc->mult = 125; /* saturation after 195 years */
1535 cc->shift = 0;
1536
1537 nsec = 0; /* audio time is elapsed time since trigger */
1538 timecounter_init(tc, cc, nsec);
1539 if (force)
1540 /*
1541 * force timecounter to use predefined value,
1542 * used for synchronized starts
1543 */
1544 tc->cycle_last = last;
1545}
1546
1547static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1548 u64 nsec)
1549{
1550 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1551 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1552 u64 codec_frames, codec_nsecs;
1553
1554 if (!hinfo->ops.get_delay)
1555 return nsec;
1556
1557 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1558 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1559 substream->runtime->rate);
1560
1561 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1562 return nsec + codec_nsecs;
1563
1564 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1565}
1566
1567static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1568 struct timespec *ts)
1569{
1570 struct azx_dev *azx_dev = get_azx_dev(substream);
1571 u64 nsec;
1572
1573 nsec = timecounter_read(&azx_dev->azx_tc);
1574 nsec = div_u64(nsec, 3); /* can be optimized */
1575 nsec = azx_adjust_codec_delay(substream, nsec);
1576
1577 *ts = ns_to_timespec(nsec);
1578
1579 return 0;
1580}
1581
1582static struct snd_pcm_hardware azx_pcm_hw = {
1583 .info = (SNDRV_PCM_INFO_MMAP |
1584 SNDRV_PCM_INFO_INTERLEAVED |
1585 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1586 SNDRV_PCM_INFO_MMAP_VALID |
1587 /* No full-resume yet implemented */
1588 /* SNDRV_PCM_INFO_RESUME |*/
1589 SNDRV_PCM_INFO_PAUSE |
1590 SNDRV_PCM_INFO_SYNC_START |
1591 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1592 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1593 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1594 .rates = SNDRV_PCM_RATE_48000,
1595 .rate_min = 48000,
1596 .rate_max = 48000,
1597 .channels_min = 2,
1598 .channels_max = 2,
1599 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1600 .period_bytes_min = 128,
1601 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1602 .periods_min = 2,
1603 .periods_max = AZX_MAX_FRAG,
1604 .fifo_size = 0,
1605};
1606
1607static int azx_pcm_open(struct snd_pcm_substream *substream)
1608{
1609 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1610 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1611 struct azx *chip = apcm->chip;
1612 struct azx_dev *azx_dev;
1613 struct snd_pcm_runtime *runtime = substream->runtime;
1614 unsigned long flags;
1615 int err;
1616 int buff_step;
1617
1618 mutex_lock(&chip->open_mutex);
1619 azx_dev = azx_assign_device(chip, substream);
1620 if (azx_dev == NULL) {
1621 mutex_unlock(&chip->open_mutex);
1622 return -EBUSY;
1623 }
1624 runtime->hw = azx_pcm_hw;
1625 runtime->hw.channels_min = hinfo->channels_min;
1626 runtime->hw.channels_max = hinfo->channels_max;
1627 runtime->hw.formats = hinfo->formats;
1628 runtime->hw.rates = hinfo->rates;
1629 snd_pcm_limit_hw_rates(runtime);
1630 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1631
1632 /* avoid wrap-around with wall-clock */
1633 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1634 20,
1635 178000000);
1636
1637 if (chip->align_buffer_size)
1638 /* constrain buffer sizes to be multiple of 128
1639 bytes. This is more efficient in terms of memory
1640 access but isn't required by the HDA spec and
1641 prevents users from specifying exact period/buffer
1642 sizes. For example for 44.1kHz, a period size set
1643 to 20ms will be rounded to 19.59ms. */
1644 buff_step = 128;
1645 else
1646 /* Don't enforce steps on buffer sizes, still need to
1647 be multiple of 4 bytes (HDA spec). Tested on Intel
1648 HDA controllers, may not work on all devices where
1649 option needs to be disabled */
1650 buff_step = 4;
1651
1652 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1653 buff_step);
1654 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1655 buff_step);
1656 snd_hda_power_up_d3wait(apcm->codec);
1657 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1658 if (err < 0) {
1659 azx_release_device(azx_dev);
1660 snd_hda_power_down(apcm->codec);
1661 mutex_unlock(&chip->open_mutex);
1662 return err;
1663 }
1664 snd_pcm_limit_hw_rates(runtime);
1665 /* sanity check */
1666 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1667 snd_BUG_ON(!runtime->hw.channels_max) ||
1668 snd_BUG_ON(!runtime->hw.formats) ||
1669 snd_BUG_ON(!runtime->hw.rates)) {
1670 azx_release_device(azx_dev);
1671 hinfo->ops.close(hinfo, apcm->codec, substream);
1672 snd_hda_power_down(apcm->codec);
1673 mutex_unlock(&chip->open_mutex);
1674 return -EINVAL;
1675 }
1676
1677 /* disable WALLCLOCK timestamps for capture streams
1678 until we figure out how to handle digital inputs */
1679 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1680 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1681
1682 spin_lock_irqsave(&chip->reg_lock, flags);
1683 azx_dev->substream = substream;
1684 azx_dev->running = 0;
1685 spin_unlock_irqrestore(&chip->reg_lock, flags);
1686
1687 runtime->private_data = azx_dev;
1688 snd_pcm_set_sync(substream);
1689 mutex_unlock(&chip->open_mutex);
1690 return 0;
1691}
1692
1693static int azx_pcm_close(struct snd_pcm_substream *substream)
1694{
1695 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1696 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1697 struct azx *chip = apcm->chip;
1698 struct azx_dev *azx_dev = get_azx_dev(substream);
1699 unsigned long flags;
1700
1701 mutex_lock(&chip->open_mutex);
1702 spin_lock_irqsave(&chip->reg_lock, flags);
1703 azx_dev->substream = NULL;
1704 azx_dev->running = 0;
1705 spin_unlock_irqrestore(&chip->reg_lock, flags);
1706 azx_release_device(azx_dev);
1707 hinfo->ops.close(hinfo, apcm->codec, substream);
1708 snd_hda_power_down(apcm->codec);
1709 mutex_unlock(&chip->open_mutex);
1710 return 0;
1711}
1712
1713static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1714 struct snd_pcm_hw_params *hw_params)
1715{
1716 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1717 struct azx *chip = apcm->chip;
1718 int ret;
1719
1720 dsp_lock(get_azx_dev(substream));
1721 if (dsp_is_locked(get_azx_dev(substream))) {
1722 ret = -EBUSY;
1723 goto unlock;
1724 }
1725
1726 ret = chip->ops->substream_alloc_pages(chip, substream,
1727 params_buffer_bytes(hw_params));
1728unlock:
1729 dsp_unlock(get_azx_dev(substream));
1730 return ret;
1731}
1732
1733static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1734{
1735 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1736 struct azx_dev *azx_dev = get_azx_dev(substream);
1737 struct azx *chip = apcm->chip;
1738 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1739 int err;
1740
1741 /* reset BDL address */
1742 dsp_lock(azx_dev);
1743 if (!dsp_is_locked(azx_dev)) {
1744 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1745 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1746 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1747 azx_dev->bufsize = 0;
1748 azx_dev->period_bytes = 0;
1749 azx_dev->format_val = 0;
1750 }
1751
1752 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1753
1754 err = chip->ops->substream_free_pages(chip, substream);
1755 azx_dev->prepared = 0;
1756 dsp_unlock(azx_dev);
1757 return err;
1758}
1759
1760static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1761{
1762 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1763 struct azx *chip = apcm->chip;
1764 struct azx_dev *azx_dev = get_azx_dev(substream);
1765 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1766 struct snd_pcm_runtime *runtime = substream->runtime;
1767 unsigned int bufsize, period_bytes, format_val, stream_tag;
1768 int err;
1769 struct hda_spdif_out *spdif =
1770 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1771 unsigned short ctls = spdif ? spdif->ctls : 0;
1772
1773 dsp_lock(azx_dev);
1774 if (dsp_is_locked(azx_dev)) {
1775 err = -EBUSY;
1776 goto unlock;
1777 }
1778
1779 azx_stream_reset(chip, azx_dev);
1780 format_val = snd_hda_calc_stream_format(runtime->rate,
1781 runtime->channels,
1782 runtime->format,
1783 hinfo->maxbps,
1784 ctls);
1785 if (!format_val) {
1786 dev_err(chip->card->dev,
1787 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1788 runtime->rate, runtime->channels, runtime->format);
1789 err = -EINVAL;
1790 goto unlock;
1791 }
1792
1793 bufsize = snd_pcm_lib_buffer_bytes(substream);
1794 period_bytes = snd_pcm_lib_period_bytes(substream);
1795
1796 dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1797 bufsize, format_val);
1798
1799 if (bufsize != azx_dev->bufsize ||
1800 period_bytes != azx_dev->period_bytes ||
1801 format_val != azx_dev->format_val ||
1802 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
1803 azx_dev->bufsize = bufsize;
1804 azx_dev->period_bytes = period_bytes;
1805 azx_dev->format_val = format_val;
1806 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
1807 err = azx_setup_periods(chip, substream, azx_dev);
1808 if (err < 0)
1809 goto unlock;
1810 }
1811
1812 /* when LPIB delay correction gives a small negative value,
1813 * we ignore it; currently set the threshold statically to
1814 * 64 frames
1815 */
1816 if (runtime->period_size > 64)
1817 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
1818 else
1819 azx_dev->delay_negative_threshold = 0;
1820
1821 /* wallclk has 24Mhz clock source */
1822 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1823 runtime->rate) * 1000);
1824 azx_setup_controller(chip, azx_dev);
1825 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1826 azx_dev->fifo_size =
1827 azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
1828 else
1829 azx_dev->fifo_size = 0;
1830
1831 stream_tag = azx_dev->stream_tag;
1832 /* CA-IBG chips need the playback stream starting from 1 */
1833 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1834 stream_tag > chip->capture_streams)
1835 stream_tag -= chip->capture_streams;
1836 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1837 azx_dev->format_val, substream);
1838
1839 unlock:
1840 if (!err)
1841 azx_dev->prepared = 1;
1842 dsp_unlock(azx_dev);
1843 return err;
1844}
1845
1846static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1847{
1848 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1849 struct azx *chip = apcm->chip;
1850 struct azx_dev *azx_dev;
1851 struct snd_pcm_substream *s;
1852 int rstart = 0, start, nsync = 0, sbits = 0;
1853 int nwait, timeout;
1854
1855 azx_dev = get_azx_dev(substream);
1856 trace_azx_pcm_trigger(chip, azx_dev, cmd);
1857
1858 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
1859 return -EPIPE;
1860
1861 switch (cmd) {
1862 case SNDRV_PCM_TRIGGER_START:
1863 rstart = 1;
1864 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1865 case SNDRV_PCM_TRIGGER_RESUME:
1866 start = 1;
1867 break;
1868 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1869 case SNDRV_PCM_TRIGGER_SUSPEND:
1870 case SNDRV_PCM_TRIGGER_STOP:
1871 start = 0;
1872 break;
1873 default:
1874 return -EINVAL;
1875 }
1876
1877 snd_pcm_group_for_each_entry(s, substream) {
1878 if (s->pcm->card != substream->pcm->card)
1879 continue;
1880 azx_dev = get_azx_dev(s);
1881 sbits |= 1 << azx_dev->index;
1882 nsync++;
1883 snd_pcm_trigger_done(s, substream);
1884 }
1885
1886 spin_lock(&chip->reg_lock);
1887
1888 /* first, set SYNC bits of corresponding streams */
1889 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1890 azx_writel(chip, OLD_SSYNC,
1891 azx_readl(chip, OLD_SSYNC) | sbits);
1892 else
1893 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1894
1895 snd_pcm_group_for_each_entry(s, substream) {
1896 if (s->pcm->card != substream->pcm->card)
1897 continue;
1898 azx_dev = get_azx_dev(s);
1899 if (start) {
1900 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1901 if (!rstart)
1902 azx_dev->start_wallclk -=
1903 azx_dev->period_wallclk;
1904 azx_stream_start(chip, azx_dev);
1905 } else {
1906 azx_stream_stop(chip, azx_dev);
1907 }
1908 azx_dev->running = start;
1909 }
1910 spin_unlock(&chip->reg_lock);
1911 if (start) {
1912 /* wait until all FIFOs get ready */
1913 for (timeout = 5000; timeout; timeout--) {
1914 nwait = 0;
1915 snd_pcm_group_for_each_entry(s, substream) {
1916 if (s->pcm->card != substream->pcm->card)
1917 continue;
1918 azx_dev = get_azx_dev(s);
1919 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
1920 SD_STS_FIFO_READY))
1921 nwait++;
1922 }
1923 if (!nwait)
1924 break;
1925 cpu_relax();
1926 }
1927 } else {
1928 /* wait until all RUN bits are cleared */
1929 for (timeout = 5000; timeout; timeout--) {
1930 nwait = 0;
1931 snd_pcm_group_for_each_entry(s, substream) {
1932 if (s->pcm->card != substream->pcm->card)
1933 continue;
1934 azx_dev = get_azx_dev(s);
1935 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
1936 SD_CTL_DMA_START)
1937 nwait++;
1938 }
1939 if (!nwait)
1940 break;
1941 cpu_relax();
1942 }
1943 }
1944 spin_lock(&chip->reg_lock);
1945 /* reset SYNC bits */
1946 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1947 azx_writel(chip, OLD_SSYNC,
1948 azx_readl(chip, OLD_SSYNC) & ~sbits);
1949 else
1950 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1951 if (start) {
1952 azx_timecounter_init(substream, 0, 0);
1953 if (nsync > 1) {
1954 cycle_t cycle_last;
1955
1956 /* same start cycle for master and group */
1957 azx_dev = get_azx_dev(substream);
1958 cycle_last = azx_dev->azx_tc.cycle_last;
1959
1960 snd_pcm_group_for_each_entry(s, substream) {
1961 if (s->pcm->card != substream->pcm->card)
1962 continue;
1963 azx_timecounter_init(s, 1, cycle_last);
1964 }
1965 }
1966 }
1967 spin_unlock(&chip->reg_lock);
1968 return 0;
1969}
1970
1971/* get the current DMA position with correction on VIA chips */
1972static unsigned int azx_via_get_position(struct azx *chip,
1973 struct azx_dev *azx_dev)
1974{
1975 unsigned int link_pos, mini_pos, bound_pos;
1976 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1977 unsigned int fifo_size;
1978
1979 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
1980 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1981 /* Playback, no problem using link position */
1982 return link_pos;
1983 }
1984
1985 /* Capture */
1986 /* For new chipset,
1987 * use mod to get the DMA position just like old chipset
1988 */
1989 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1990 mod_dma_pos %= azx_dev->period_bytes;
1991
1992 /* azx_dev->fifo_size can't get FIFO size of in stream.
1993 * Get from base address + offset.
1994 */
1995 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1996
1997 if (azx_dev->insufficient) {
1998 /* Link position never gather than FIFO size */
1999 if (link_pos <= fifo_size)
2000 return 0;
2001
2002 azx_dev->insufficient = 0;
2003 }
2004
2005 if (link_pos <= fifo_size)
2006 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2007 else
2008 mini_pos = link_pos - fifo_size;
2009
2010 /* Find nearest previous boudary */
2011 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2012 mod_link_pos = link_pos % azx_dev->period_bytes;
2013 if (mod_link_pos >= fifo_size)
2014 bound_pos = link_pos - mod_link_pos;
2015 else if (mod_dma_pos >= mod_mini_pos)
2016 bound_pos = mini_pos - mod_mini_pos;
2017 else {
2018 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2019 if (bound_pos >= azx_dev->bufsize)
2020 bound_pos = 0;
2021 }
2022
2023 /* Calculate real DMA position we want */
2024 return bound_pos + mod_dma_pos;
2025}
2026
2027static unsigned int azx_get_position(struct azx *chip,
2028 struct azx_dev *azx_dev,
2029 bool with_check)
2030{
2031 struct snd_pcm_substream *substream = azx_dev->substream;
2032 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2033 unsigned int pos;
2034 int stream = substream->stream;
2035 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2036 int delay = 0;
2037
2038 switch (chip->position_fix[stream]) {
2039 case POS_FIX_LPIB:
2040 /* read LPIB */
2041 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2042 break;
2043 case POS_FIX_VIACOMBO:
2044 pos = azx_via_get_position(chip, azx_dev);
2045 break;
2046 default:
2047 /* use the position buffer */
2048 pos = le32_to_cpu(*azx_dev->posbuf);
2049 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2050 if (!pos || pos == (u32)-1) {
2051 dev_info(chip->card->dev,
2052 "Invalid position buffer, using LPIB read method instead.\n");
2053 chip->position_fix[stream] = POS_FIX_LPIB;
2054 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2055 } else
2056 chip->position_fix[stream] = POS_FIX_POSBUF;
2057 }
2058 break;
2059 }
2060
2061 if (pos >= azx_dev->bufsize)
2062 pos = 0;
2063
2064 /* calculate runtime delay from LPIB */
2065 if (substream->runtime &&
2066 chip->position_fix[stream] == POS_FIX_POSBUF &&
2067 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2068 unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2069 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2070 delay = pos - lpib_pos;
2071 else
2072 delay = lpib_pos - pos;
2073 if (delay < 0) {
2074 if (delay >= azx_dev->delay_negative_threshold)
2075 delay = 0;
2076 else
2077 delay += azx_dev->bufsize;
2078 }
2079 if (delay >= azx_dev->period_bytes) {
2080 dev_info(chip->card->dev,
2081 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
2082 delay, azx_dev->period_bytes);
2083 delay = 0;
2084 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2085 }
2086 delay = bytes_to_frames(substream->runtime, delay);
2087 }
2088
2089 if (substream->runtime) {
2090 if (hinfo->ops.get_delay)
2091 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2092 substream);
2093 substream->runtime->delay = delay;
2094 }
2095
2096 trace_azx_get_position(chip, azx_dev, pos, delay);
2097 return pos;
2098}
2099
2100static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2101{
2102 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2103 struct azx *chip = apcm->chip;
2104 struct azx_dev *azx_dev = get_azx_dev(substream);
2105 return bytes_to_frames(substream->runtime,
2106 azx_get_position(chip, azx_dev, false));
2107}
2108
2109/* 1201/*
2110 * Check whether the current DMA position is acceptable for updating 1202 * Check whether the current DMA position is acceptable for updating
2111 * periods. Returns non-zero if it's OK. 1203 * periods. Returns non-zero if it's OK.
@@ -2190,95 +1282,6 @@ static void azx_clear_irq_pending(struct azx *chip)
2190 spin_unlock_irq(&chip->reg_lock); 1282 spin_unlock_irq(&chip->reg_lock);
2191} 1283}
2192 1284
2193static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2194 struct vm_area_struct *area)
2195{
2196 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2197 struct azx *chip = apcm->chip;
2198 if (chip->ops->pcm_mmap_prepare)
2199 chip->ops->pcm_mmap_prepare(substream, area);
2200 return snd_pcm_lib_default_mmap(substream, area);
2201}
2202
2203static struct snd_pcm_ops azx_pcm_ops = {
2204 .open = azx_pcm_open,
2205 .close = azx_pcm_close,
2206 .ioctl = snd_pcm_lib_ioctl,
2207 .hw_params = azx_pcm_hw_params,
2208 .hw_free = azx_pcm_hw_free,
2209 .prepare = azx_pcm_prepare,
2210 .trigger = azx_pcm_trigger,
2211 .pointer = azx_pcm_pointer,
2212 .wall_clock = azx_get_wallclock_tstamp,
2213 .mmap = azx_pcm_mmap,
2214 .page = snd_pcm_sgbuf_ops_page,
2215};
2216
2217static void azx_pcm_free(struct snd_pcm *pcm)
2218{
2219 struct azx_pcm *apcm = pcm->private_data;
2220 if (apcm) {
2221 list_del(&apcm->list);
2222 kfree(apcm);
2223 }
2224}
2225
2226#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2227
2228static int
2229azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2230 struct hda_pcm *cpcm)
2231{
2232 struct azx *chip = bus->private_data;
2233 struct snd_pcm *pcm;
2234 struct azx_pcm *apcm;
2235 int pcm_dev = cpcm->device;
2236 unsigned int size;
2237 int s, err;
2238
2239 list_for_each_entry(apcm, &chip->pcm_list, list) {
2240 if (apcm->pcm->device == pcm_dev) {
2241 dev_err(chip->card->dev, "PCM %d already exists\n",
2242 pcm_dev);
2243 return -EBUSY;
2244 }
2245 }
2246 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2247 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2248 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2249 &pcm);
2250 if (err < 0)
2251 return err;
2252 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2253 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2254 if (apcm == NULL)
2255 return -ENOMEM;
2256 apcm->chip = chip;
2257 apcm->pcm = pcm;
2258 apcm->codec = codec;
2259 pcm->private_data = apcm;
2260 pcm->private_free = azx_pcm_free;
2261 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2262 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2263 list_add_tail(&apcm->list, &chip->pcm_list);
2264 cpcm->pcm = pcm;
2265 for (s = 0; s < 2; s++) {
2266 apcm->hinfo[s] = &cpcm->stream[s];
2267 if (cpcm->stream[s].substreams)
2268 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2269 }
2270 /* buffer pre-allocation */
2271 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2272 if (size > MAX_PREALLOC_SIZE)
2273 size = MAX_PREALLOC_SIZE;
2274 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2275 chip->card->dev,
2276 size, MAX_PREALLOC_SIZE);
2277 /* link to codec */
2278 pcm->dev = &codec->dev;
2279 return 0;
2280}
2281
2282/* 1285/*
2283 * mixer creation - all stuff is implemented in hda module 1286 * mixer creation - all stuff is implemented in hda module
2284 */ 1287 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 14:23:12 -0500